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Re: [f-cpu] Tr:[ff] Syntetisation d'un FCPU?
On Mon, Jul 08, 2002 at 01:01:26PM +0000, Nicolas Boulay wrote:
> A french guy have access to a big FPGA board (XCV1000) until the 20
> july. Maybe it's possible to write some executable testbench ? Does it
> have an interrest compare to the simulated one ? Maybe it's have an
> interrest for timing test ? (all unit must run at the same speed)
Try the one below. It continuously calculates
Y := A * Y + B
with user-defined A and B and an initial Y of 0. A, B and the clock
must be supplied externally. The Y output should change every 8 cycles.
You can also run a simulation of the second entity (Test_Test) and watch
the numbers flow by... but don't wait for it to finish; it runs forever.
(Yann, *now* you have reason to complain that my testbenches take too
long ;)
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
-- eu_timing_test.vhdl - IMU/ASU timing test
-- Copyright (C) 2002 Michael Riepe <michael@stud.uni-hannover.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- $Id$
library IEEE;
use IEEE.std_logic_1164.all;
use work.FCPU_config.all;
entity EU_Timing_Test is
port (
A, B : in F_VECTOR;
Clk : in std_ulogic;
Y : out F_VECTOR
);
end EU_Timing_Test;
architecture Struct_1 of EU_Timing_Test is
component EU_ASU
port(
Din_0 : in F_VECTOR;
Din_1 : in F_VECTOR;
Subtract : in std_ulogic;
Flags : in std_ulogic_vector(13 downto 8);
Size : in std_ulogic_vector(LOGMAXSIZE-1 downto 0);
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
--
Dout_0 : out F_VECTOR;
Dout_1 : out F_VECTOR;
Dout_2 : out F_VECTOR;
Dout_3 : out F_VECTOR
);
end component;
component EU_IMU
port(
Din_0 : in F_VECTOR; -- multiplicand
Din_1 : in F_VECTOR; -- multiplicator
Din_2 : in F_VECTOR; -- summand (optional)
MacLo : in std_ulogic;
MacHi : in std_ulogic;
MacAlt : in std_ulogic;
Flags : in std_ulogic_vector(13 downto 8);
Size : in std_ulogic_vector(LOGMAXSIZE-1 downto 0);
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
--
Dout_0 : out F_VECTOR;
Dout_1 : out F_VECTOR;
Dout_2 : out F_VECTOR;
Dout_3 : out F_VECTOR;
Dout_4 : out F_VECTOR;
Dout_5 : out F_VECTOR;
Dout_6 : out F_VECTOR;
Dout_7 : out F_VECTOR
);
end component;
constant zero : std_ulogic := '0';
constant one : std_ulogic := '1';
constant v0 : F_VECTOR := (others => '0');
constant v1 : F_VECTOR := (others => '1');
signal T, X : F_VECTOR;
signal r_T, r_X : F_VECTOR;
signal En_IMU, En_ASU : std_ulogic;
signal State : integer := 0;
begin
multiplier : EU_IMU
port map (
Din_0 => A,
Din_1 => r_X,
Din_2 => v0,
MacLo => zero,
MacHi => zero,
MacAlt => zero,
Flags => v0(13 downto 8),
Size => v1(LOGMAXSIZE-1 downto 0),
Clk => Clk,
Rst => zero,
En => En_IMU,
Dout_6 => T
);
adder : EU_ASU
port map (
Din_0 => r_T,
Din_1 => B,
Subtract => zero,
Flags => v0(13 downto 8),
Size => v1(LOGMAXSIZE-1 downto 0),
Clk => Clk,
Rst => zero,
En => En_ASU,
Dout_2 => X
);
-- output
Y <= r_X;
control : process (Clk, State, T, X)
variable nextstate : integer;
begin
if rising_edge(Clk) then
En_ASU <= '0';
En_IMU <= '0';
nextstate := State + 1;
case State is
when 0 =>
r_X <= (others => '0');
En_IMU <= '1';
when 6 =>
r_T <= T;
En_ASU <= '1';
when 8 =>
r_X <= X;
En_IMU <= '1';
nextstate := 1;
when others =>
null;
end case;
State <= nextstate;
end if;
end process;
end Struct_1;
-- pragma synthesis_off
library IEEE;
use IEEE.std_logic_1164.all;
use work.FCPU_config.all;
entity Test_Test is
end Test_Test;
architecture Blah of Test_Test is
component EU_Timing_Test
port (
A, B : in F_VECTOR;
Clk : in std_ulogic;
Y : out F_VECTOR
);
end component;
signal A, B, Y : F_VECTOR;
signal Clk : std_ulogic;
begin
mut : EU_Timing_Test
port map (A => A, B => B, Clk => Clk, Y => Y);
A <= X"0000000000000003";
B <= X"0000000000000001";
monitor : process (Y)
use std.textio.all;
use ieee.std_logic_textio.all;
variable lout : line;
begin
write(lout, string'("Y = "));
write(lout, Y);
writeline(output, lout);
end process;
clock : process
begin
Clk <= '0';
wait for 1 ns;
Clk <= '1';
wait for 1 ns;
end process;
end Blah;
-- pragma synthesis_on
-- vi: set ts=4 sw=4 equalprg="fmt -72 -p--": please