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Rep:Re: Rep:[f-cpu] Coding for Synthesis
- To: <f-cpu@seul.org>
- Subject: Rep:Re: Rep:[f-cpu] Coding for Synthesis
- From: "Nicolas Boulay" <nicolas.boulay@ifrance.com>
- Date: Wed, 10 Jul 2002 22:45:10 GMT
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- Delivery-Date: Wed, 10 Jul 2002 18:45:20 -0400
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i need a nap sorry...
nicO
-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 11/07/02
Objet: Re: Rep:[f-cpu] Coding for Synthesis
On Wed, Jul 10, 2002 at 10:18:35PM +0000, Nicolas Boulay wrote:
> Nice resume but...
[...]
> - pipeline enable:
>
> If your unit has more than two pipeline stages, you probably want
> to chain the enable signal. That is, the enable signal `travels'
> through the pipeline together with the data `wavefront' (I used
> that trick in the IMU in order to save power). To do so, provide
an
> `enable out' signal in each stage:
>
> if to_X01(async_reset) = '1' then
> some_signal <= '0';
> enable_out <= '0';
> elsif rising_edge(clock_signal) then
> if to_X01(enable_in) = '1' then
> some_signal <= some_expression;
> end if;
> enable_out <= enable_in;
> end if;
>
> Then, connect `enable_out' of stage <n> to `enable_in' of stage
> <n+1>.
>
> >>>Gloups ! i don't like that at all : a new asynch signal (that's
> introduice slew rate problem). I think that such signal must be under
> the rising_edge of the process.
`enable' is a synchronous signal.
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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