Re: [f-cpu] Free synthesis tool for Verilog and other links

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Jul 19, 2002 at 12:00:03PM +0200, Just an Illusion wrote:
[...]
> The problem with schematics is that they are in proprietary format, 
> which are incompatible between tools.
> More, synthesizer don't like them (I don't no why but when I try to give 
> them circuit like postscript, jpeg, png files... They crush :-D).

Of course you have to convert them to *text* before you feed them to
the VHDL tools. Try uuencode.

(SCNR)

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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