Re: [f-cpu] Conditionnal Load and Store

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

----- Original Message -----
From: "Yann Guidon" <whygee@f-cpu.org>
To: <f-cpu@seul.org>
Sent: Friday, July 26, 2002 4:57 PM
Subject: Re: [f-cpu] Conditionnal Load and Store


> hi,
>
> Cedric BAIL wrote:
> > Why didn't we have conditionnal load and store. I mean somtehing like
storez,
> > storenz, loadz, loadnz, ... It can be really usefull and we can do with
that
> > all what we can do with predicate I think.
> <snip>
>
> conditional loads/stores are a corollary of the conditional moves.
>
> IIRC it appeared that these instructions were in fact needed,
> when we were discussing about the semaphores done with LL/SC.
> "Store conditional" is this thing.
>
> By the way : condition 3 is still reserved for FP, but we could
> simply connect it to the LSU : LL/SC would then not need any specific
> opcode. it sounds easy and logical, what do others think ?
>

I don't really understand how you plan to do so.

retry:
LL [r1],r2 ==> loading [r1] in r2 and set a lock bit in matching LSU entry.
...
SC r2,[r1],r3 ==> storing r2 in [r1] if lock bit in matching LSU entry is
set and set r3 to 1, otherwise just set r3 to 0. Then lock bit in matching
LSU entry is reset.
IF (r3 == 0) JUMP ... // goto retry;

As you can see, you need to set this special bit with a LOAD operation and
check it and report it in register with a STORE operation

So I wonder how you can use condition 3 with LOAD/STORE to do so since STORE
would also need to report if storing really occured or not..

NOTE: the given syntax for LL/SC is absolutely not mandatory. They are just
an example but the idea still remains the same.


*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/