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[f-cpu] MUL question




the manual is not very clear on the latency of
the MUL EU.
from the VHDL i understand it's like:

 size:  reult(low) result(high)
 8 bit      3          4
16 bit      4          5
32 bit      5          5
64 bit      6          6

my question is, (even if the actual numbers change)
are we going to have seperate latencies for each
output ?

and what if the used write slots look like this:
(i know a very big if)
w0    w1
used used
free free
used used
free free
used used
free free
used used

we would never be able to start the MUL, unles we
delay one of the MUL EU outputs to pull it strait.
(of corce this also hapens the other way around,
when none of the write slots are aligned, and we
need two aligned slots (like ADD+carry))

do we delay one of the outputs, or just wait for
a free pair of slots that "fits" the units output?

PS i'm not sure if this would be a real problem, or
if it's only going to hapen in rare conditions.

also, using a seperate latency for each write port
shoeld not be to compilcated.

jaap.


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