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Re: [f-cpu] MUL question



hi !

Michael Riepe wrote:
> On Sat, Jul 27, 2002 at 06:03:40AM -0700, jaap stolk wrote:
> >
> > the manual is not very clear on the latency of the MUL EU.
> > from the VHDL i understand it's like:
> >
> >  size:  reult(low) result(high)
> >  8 bit      3          4
> > 16 bit      4          5
> > 32 bit      5          5
> > 64 bit      6          6
> Correct.

???

i thought that it was 2-4-6-8 ?
so i have to modify the f-cpu/CAPABILITIES file.

> > my question is, (even if the actual numbers change)
> > are we going to have seperate latencies for each
> > output ?
> In most units, no. In this unit, yes.
multiplies are often a critical operation when it is used.

> > and what if the used write slots look like this:
> > (i know a very big if)
> > w0    w1
> > used used
> > free free
> > used used
> > free free
> > used used
> > free free
> > used used
> >
> > we would never be able to start the MUL, unles we
> > delay one of the MUL EU outputs to pull it strait.
> > (of corce this also hapens the other way around,
> > when none of the write slots are aligned, and we
> > need two aligned slots (like ADD+carry))
> 
> I guess that's an Xbar question.
> 
> > do we delay one of the outputs, or just wait for
> > a free pair of slots that "fits" the units output?
> Delaying one output seems to be the better solution.
i don't think it's necessary, however.

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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