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Re: [f-cpu] condition flag location



hi !

jaap stolk wrote:
> hi,
<snip>
> > Concerning the assembler : i wonder if that was a
> > good idea to get back at it now. in fact it opens a
> > whole new (old) can of stincky worms and we haven't
> > even  solved many problems yet. My priority now is to
> > finish all the EUs, both in C and VHDL, so they work
> > in SIMD and pass the same tests whatever the langage.
> ok. if i need anything, i'll just hack one of your
> old YGASM's or more likely: hexedit the bin file. :-)
that's it. As long as the other units are not ready
(and worse : the register is not OK), there is no
use for a complex ASM.

> > register set has problemsin the VHDL version.
> ouch ! :-(
i had identified some timing problems.
But now i have to repair the ROP2 because you
addedd signals :-/ Usually, in the VHDL, these
signals should have been propagated in the Xbar.

> i made the depth of the scheduling queue defined
> at one pont, its now on 6 cycles (MUL), but can be
> changed to whateverr you like :)
i #think# there was such a definition somewhere,
look at the configuration files...

> just out of interest, is there going to be a real
> score bord in hardware, or just a small table ?
> (there are never more than a couple of registers
> "being computed") i gess its a timging problem.
currently, and for a single-issue FC0, all we need
is a bunch of comparators tied to the scheduler's queue.
My original idea (long ago) was to have one bit per
register, but the data (whether a register can be used)
would have been duplicated. And the SQ provides much
more precise information : not only whether it can
be used, but also when :-)

> jaap.
WHYGEE
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