Re: [f-cpu] Whats going to happen when the VHDL is done?

[Yann Guidon <whygee@f-cpu.org>]

hi !

Marco Al wrote:
> What about the design of custom cells/manual floorplanning/static&dynamic timing
> analysis etc? AFAIK the big boy's dont even use the commonly available stuff for
> this, high performance processors are in a class of their own... especially if
> you want to compete with something like the P4 (which you do seem to, otherwise
> having pipeline stages that shallow makes no sense).
At least it makes sense in some conditions
because up to now, on FPGA "cells", FF come almost for free.

> If you just want to plonk
> VHDL through a synthesizer worrying about 10th's of ns is futile.
:-)

> I know its a bit counterproductive bringing this up... but somoene has to have
> some idea what to do once you get there right? Just curious...
when VHDL is "done" (validated, verified, compiled and synthesised),
going to full custom is maybe going to take... years ? :-)
unless much more people join (people from all the major AND minor companies :
HP, IBM, INTEL, MOTOROLA, etc etc etc...) because at the current rate,
it's not going far otherwise.

Personally i don't care that much about cell libraries because the technology
is going to evolve much faster than our work. I try to look at the far future,
not the mid-term (a technology lives around 3 years maximum).

If others want to make a subproject around that, fine.
However, without much support from the industry, it's going to be very difficult
for the people doing it. At least, if someone/some people want to attack
this problem, it would be very cool if they made a draft about the
design style and methodology. Writing good sources from the start
is important, isn't it ?


> Marco
WHYGEE
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