SYSTEM OVERVIEW
The objective is to produce a
low cost, hign performance, user operated
Lightpen/Mouse-controlled Display Terminal System
having TWO embedded
ERIN32 Processor chip SETS.
The resulting system may be used
in virtually any Commercial Small/Large
Business Application including but not limited to
Federal/State/Local Government,
where present day usage is the Personal Computer
(PC) with or without Network Server Hardware/Software. Simply discard the
Tower/Server with whatever they contain; retain the remaining devices, and plug
in the new Processing Hardware and Application Programs. This system is
open-ended to all types of Peripheral devices.
A typical application could be
ALL Departments and ALL associated functions in a Hospital or GROUP of
Hospitals. Or it could be used by NASA as pre/post launch Systems Monitor
and Remote Control System. If you ask the question - CAN IT DO? - tHE
ANSWER IS yes.
The system is programmed in a
language called TIPS. TIPS is an ancronym for TOTAL INFORMATION
PROGRAMMING SYSTEM. TIPS is an interpretive language which provides
the Application Programmer with the capabilities to Collect, Store, Manipulate,
Structure and Retrieve blocks of data. The language is therefore FILE,
FORM, PAGE, and PART oriented. TIPS has been specifically designed to
function in a Multi-User, Multi-port environment and occupies only 20,000 bytes
of Memory - more specifically 9,967 INSTRUCTIONS. The Application
Programmer may create Forms at any User Station; enter related Programs; Test
and Modify as needed, before or after the system is On-Line. These
features are not inherent in present day PC's. The system is designed to
accomodate from 1 to 128 User Stations. A parallel expansion port is
provided for "N" sub-subsystems.
Data reduction techniques are
used such that a FORM is stored in Compressed Mode only ONCE on the Hard Drive
Disk. Any variable data that is entered on the Form is extracted and
stored in an Appropriate FILE with a descriptor that attaches the data to a
specific Form or series of Forms where the data fields are identical. For
example: Name = John Doe. This provides for a VERY significant reduction
in system storage requirements and Data Entry.
GENERAL FEATURES:
The QL6600 of the Quicklogic Eclipse family of
FPGA's
a. 0.25u CMOS
b. 2.5V Vcc; 1.5
Watts
c. Max Gates =
583.008
d. Logic Cells =
4,032
e. Max Flip-Flops =
9600
f. Max I/O pins =
512
g. RAM Modules =
36
h. RAM BITS =
82,900
i. Package = BGA (1.0mm),
672 pin
j. Power ON Reset all
FF's
k. 4 - Phase Lock Loop;
1x, 2x, 4x
l. 9 Global Clock
Networks
REFERENCES:
1. The Logic of Computer
Arithmetic, 1963 by Ivan Flores,
Library of
Congress Card Number:63-14727
2. The TTL Data Book for
Design Engineers, Texas Instruments First Edition
3. Bipolar Microprocessor
Logic and Interface, AMD 1983 Data Book
4. Fairchild Advanced
Schottky TTL, FAST Data Book 1985
5. Quickworks User's Guide
with SpDE Reference
Quicklogic Corporation 1991 - 1999
6. Programmer's Reference
Manual, DDP-516
7. TIPS Software
Listing
8. Application Programmers
Reference Manual (TIPS)
Presented by:
First presentation; others possible
Erin Greene &
Associates
Business Information Management
Systems
2613 North 11th
Street
Ocean Springs, MS
39564-8364
Richard E. Hartney
Research Director
Phone:
228-875-6003
e-mail: rhartney@bellsouth.net
BIOGRAPHY: abbreviated, reverse
chronolgy
1980 - 1990 LITTON DATA SYSTEMS - Engineering
Specialist
Designs for Combat
Simulator AN/SSQ-91 used on all LHD
Aircraft
Cariers
Comparator Card
IFF
Comparator
Radar Signal Simular
Multi-Beam Comparator
SHARE 7 Processing
System
Micro-Programmed Emulation of the AN/UYK-7V Military Comp.
Single Board Computer
using 68020 & 68881 Motorola Chip Sets
1978 - 1980 HONEYWELL INFORMATION
SYSTEMS - Senior Engineer
Floating Point
Processor
Hardware Design - Instruction Entry, Sign Control, Multi-way
Conditional Branch Mux
Micro-Code - Write, Assemble, and debug using a 104 Bit
Control Word, Interrupt Handler, Self Test and I/O
Test
1975 - 1978 SANDERS ASSOCIATES
INC. - Associate Engineer
Hardware Design - General Purpose Microprocessor using
AM2901A Bit Slice, having DMA break cycle, micro-programmed
Timing and Translate PROM for Emulation of PDP-11, MIP-16,
and
NOVA-3 Mini-Computers
1974 - 1975
Self Employed
Designed Hardware Emulation of Honeywell DDP-516 Mini
1964 1974
SANDERS ASSOCIATES INC. Associate Engineer
Designed a Micro-programmed CRT Edit Function Processor,
Interrupt Controller, DMC Controller, Character Generator and
Refresh Memory, Raster Scan Timing Generator and wrote the
Acceptance Test Procedure and Program for the Deepwell Prog
1944 -
1964 U.S.Navy - Retired with Rank of
Senior Chief Aviation Electronics
Technician. Instructed/Maintained/Supervised Aviation
Electronics
Equipments, including communications, navigation, radar and
Semi-Automatic Test Equipment
Presentation using Transparencies (will require a
Projector)
NOTE: All design is SCHEMATIC INPUT only - no
VHDL
1. KAISER CLINI-CALL* SYSTEM, AUGUST
1971
A. LANGUAGE &
PERIPHERAL PROCESSOR
B. APPLICATION
AREAS
2. ERIN GREENE & ASSOCIATES SYSTEM
FUNCTIONAL BLOCK DIAGRAM
A. ERIN32 is an Emulation
of DDP-516, expanded to 32 Bits
3. MEMORY MANAGEMENT
A. MODIFIED HARVARD
Architecture
B. Program Memory, Local
Memory, Global Memory
4. Micro Instruction Format
A. 36 Bit Instruction, 18
Bit Source Address, 18 Bit Destination Address
B. Timing Control (T1 - T4
)
5. ERIN32 Instruction Set
A. Move
Instruction
6. Data Processor Block Diagram
A. Shift Logic, Sheet 1
& 2 (Barrel Shifter)
B; The AMD 25S10
Shifter
C. NCOD Logic - Priority
Encodes SN74148 Equivalent
D. CAS Logic (Compare
Instruction) SN7485 Equivalent
(1)
CMP2
(2) CMP3,
Sheet 1 & 2
7. Address Processor
A. 128 x 18 Index
Registers
B. Addressing
Modes
(1)
Direct
(2)
Indirect
(3)
Indexed
C. Eight (8) Vectored
Priority Interrupts
(1) Enable/Disable (ENB & INH Instructions
D. Store
Address
E. Non-Restoring, Unsigned
Divide
F. Time Sequenced Multiply
with Nibble Skip
(1) 64
Bit Adder - AN74283 Equivalent
(2)
Carry Generation - SN74182 Equivalent
G. Square
ROOT
8. The TIPS Lexicon
The following Functions will be
added
(For Secure Visable Data
Environments
A. BLANK ( till
UNBLANK )
B. UNBLANK ( till
BLANK )
C. CLEAR BLANK ( Display
All )
D. DISPLAY BLANK
(Display only the Blanked Fields )
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