[f-cpu] I need some explanation

[Andreas Romeyke <art1@it-netservice.de>]

Hello,

first, can anybody explain me how in an SIMD-division the
division-by-zero-exception works? Will be all data in pE. 8bit-Chunks
thrashed? Or is this a problem of the exceptionhandlerroutine?


second, I readed the F-CPU can be scaled up to 128 Bits and so on, and the
units are doubled... What is with the xbar? Will it handle 128 bit, or is
it also doubled? If is it 128 Bit, we need 4 cycles to handle? Means a
scaled CPU also two or more pipelines? Will the registersize scale up or 
the count of register doubled? Or have I misreaded about?

Thanks.

Bye Andreas

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