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Re: (LSU!) Re: [f-cpu] manual update
On Mon, Jun 10, 2002 at 01:55:50AM +0200, Yann Guidon wrote:
> hi,
>
> nico wrote:
>
> > In fact, it's very easy to explain. But It's not the strong point of
> > Whygee ;D
> it's a problem with more people than you'd agree...
>
> And please read this post carefully, it's probably the clearest
> thing i could write. The invalidation problem is certainly
> a big point that you have not yet addressed and that has forced
> me to abandon the rough idea you have.
[...]
Unfortunately, it's not at all clear what you two are talking about.
Maybe if I had attended your meetings in Paris on a regular basis...
Let me see if I get things straight.
When the instruction decoder encounters a load or store instruction, it
extracts the register number (r2) and tries to find the associated LSU
line (or lets the LSU do it). That is, there is a 64 -> 8 (or 6-bit ->
3-bit) mapping required if we have 8 LSU lines. Right so far?
If the register has no associated LSU line, the least recently used
line is flushed, its current association to a register is `broken',
then data is fetched from the cache into the LSU, and finally the line
is linked to the new register. Still right?
I understand that this is a shortcut for the normal
read register -> lookup LSU line by address -> read/write LSU line
procedure which will take a lot of cycles (decode, register read,
Xbar, LSU lookup, LSU read/write). I also understand that the process
of associating a register with an LSU line is normally triggered by the
`loadaddr' instruction, not by a `load' or `store'. And I understand that
the `reverse mapping' from LSU lines to register numbers is necessary
in order to clear any `forward' mappings when an LSU line is flushed. But
is that really a timing-critical operation? Isn't it sufficient to
invalidate the line immediately and clear the forward mappings later,
before the line is re-validated?
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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