Re: [f-cpu] use of 1r1w regfile for our 3r2w regfile

[Anup Gangwar <anup@cse.iitd.ernet.in>]

Hi,

	I have been reading posts on this list for long but have never
posted any message myself. In my opinion going for simpler (less R+W
ports) RF's will be advantageous from two viewpoints:

1. If we stick to at most 2R+2W ports then the CPU could easily work with 
FPGA technology a big+ while prototyping.

2. The larger the RF the slower it will be. Everyone is breaking up the RF 
into smaller chunks (clusters of FUs). As per one heuristic estimate the 
power, delay and max freq grow as atleast N^1.5 where N is the no. of FUs 
per RF.

6. The compiler complexity will not grow too much if each of the 
individual clusters is connected to the other in a homogeneous fashion. 
Though a variety of interconnect strategies are possible.

Regards,

Anup
-- 


On Sun, 15 Jun 2003 nicolas.boulay@ifrance.com wrote:

> Le Samedi 14 Juin 2003 10:37, Michael Riepe a écrit :
> > On Sat, Jun 14, 2003 at 08:56:42AM +0000, Nicolas Boulay wrote:
> > [...]
> >
> > > > This is what I consider the "worst case".
> > >
> > > But is that good or not ? 4x 1r1w regifile will be ~30% faster than a
> > > true 3r2w.
> >
> > The worst case is, by definition, always bad (or even worse ;).
> 
> There is a miss understanding. The worst case the case where it slower. 3r2w 
> SRAM memory are ~30% slower than 1r1w SRAM. But if we use 1r1w SRAM bank 
> there is some collision that "could" be avoid by the compiler (otherwise you 
> loose one cycle).
> 
> I can't say was is worst. It fully depend on compiler.
> 
> So big latches array will be oustandly slow.
> 
> nicO
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