Re: [f-cpu] use of 1r1w regfile for our 3r2w regfile

[Michael Riepe <michael@stud.uni-hannover.de>]

On Sun, Jun 15, 2003 at 11:14:27AM +0000, nicolas.boulay@ifrance.com wrote:
[...]
> There is a miss understanding. The worst case the case where it slower. 3r2w 
> SRAM memory are ~30% slower than 1r1w SRAM. But if we use 1r1w SRAM bank 
> there is some collision that "could" be avoid by the compiler (otherwise you 
> loose one cycle).

And what about the extra logic you'll have to put around the 1r1w banks?
Every bank needs its own 2:1 input selection MUX, and you'll also
require three <n>:1 output selector MUXes to connect <n> banks to our
three read ports.  Since all of them contribute to the CDP, your ~30%
speed advantage may already be gone.

> I can't say was is worst. It fully depend on compiler.
> 
> So big latches array will be oustandly slow.

The point is that it's not big -- only 64x63 (since r0 is hardwired).
There are more flip-flops at the end of the first stage of the integer
multiplier.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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