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Re: [f-cpu] was 1r1w 3r2w



Hi,

> here you propose an architecture where the core is
> split into "clusters"
> with each a small register set and some "Execution
> Units".
> right ? (if yes, then it has already been discussed
> ....)
> 

i don't want to get into the discussion of on-chip
clusters, but i have been walking around with this
idea for a while:

can we have a separate cpu core between external
memory
and cache memory ? the main core has ONLY access to
the
cache memory, and the extra core has access to both
memory's.

the extra core runs a (short!) program, and is
controlled
by the main core. (but this program can be changed for
specific situations.

the extra core can:
-compress code/data from cache memory to main memory.
-decompress code/data from main memory to cache
memory.
-schedule memory loads, (in co-operation with the main
 scheduler) so we can reach much lower worst -case
 situations in a hard-real-time system.
 (like a prefetch instruction, but more intelligent)
-do all to distributed memory stuff.
-work as a co-processor when there is nothing else to
 do.

compression can be as simple as bit stuffing. if you
know that your data is in a 0..500 range, you can tell
the extra core to store it in a 9 bit format.
(i have run some experiments in the past on using
bit-pointers instead of byte pointers)

external memory is cheep, but this would also lower
the needed external bandwidth, and the needed
pincount,
witch could have a big effect on the total cost.

i should stop now...

jaap.



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