Re: SHL II (Re: [f-cpu] DATE2002, day 1 report)

[Yann Guidon <whygee@f-cpu.org>]

hello !

Michael Riepe wrote:
> On Wed, Mar 06, 2002 at 02:32:10AM +0100, Yann Guidon wrote:
> > hi !
> >
> > Michael Riepe wrote:
> > > On Wed, Mar 06, 2002 at 12:49:12AM +0100, Yann Guidon wrote:
> > > [...]
> > > > PS2: i found a new/better barrel shifter structure
> > > > this morning in the metro :-)
> > > Faster? Details?
> > :-D what a quick answer !
> After all those off-topic discussions, I'm glad to hear something
> about f-cpu development again ;)

same with me ;-)

> > btw, i met people from the Hannover university,
> > i talked about you with someone :-)
> He probably didn't know me, did he?
he said he did, but you don't belong to the same part of the university.
If he meets you, i told him to say "hi" :-)

> > For the shifter idea, it is very simple, maybe easier
> > to understand than the reversed Omega network.
> [...]
> > I use a more straight-forward (naive ?) way, but the unit is
> > split into three : one performs SDUP (so one register operand can
> > serve to control the shift amount), the other part is a 2-stage
> > 4-mux shift/rotate for doing 8-bit and 16-bit shifts/rotates,
> > and the last part is a series of 16-bit (only 16 bits left, 16-bits
> > right or no shift) blocks. Because we have still to shift 64-16 bits,
> > there are 48/16=3 16-bit shift block layers.
> 
> How do you build the bit-shifter - full 16x16 matrix?

not "full" because these shifter only shift 16|0|-16 bits,
so there's a stage that performs the fine shifts.

However having limited-length wires (crossing a maximum of 16 bits,
whatever the size) certainly helps from the signal point of view.
Since the propagation delay is roughly proportional to the square
of the distance, having a minimal-stage barrel shifter is not the
best solution anymore because some wires are very long.
So i designed the shifter with that idea in mind.

My mistake was maybe to want to reuse existing networks
and modify them. Instead, the solution appeared logical
to me when i wasn't influenced by the self-routing properties
and the limitation to 2-port routers. A 3-port switch element
requires 3 metal levels but the signal routing (the control's
design) is not a real problem either.

> > But i'll have to rest a bit before i write
> > documentation, code and draw stuffs. be patient, DATE has only begun :-)
> Please let me know when you have some code to look at.

before that, i have to install and test some demo software that
exhibitors from DATE have given to me. Soon, there is potential
support of 3 other tools. The existing software are Simili and
Vanilla under Linux (hmmmm, un*x) and the new ones are : ncsim
(from Cadence, the exhibitors shown me how to use the tools),
ALDEC's Riviera (i saw a live demo today and i have to install
it), and another tool (not synthesis or compilation but an
entry tool, i would be curious to see it "understand" our code
and verify that the vendor is right ...)

Then comes the register set problem ! i have some beginnings
of answers and EUROPRACTICE proposed to integrate F-CPU in their
design kit CDROM : this way, universities and laboratories who have
the proper software can do the synthesis themselves and report
the results. It's a bit far fetched (feedback or even attempts
are not 100% probable) but worth trying and we could
reach a very specific target at no cost.
Before this happens, let's just stick to the "least common
denominator" and make something clean.

oh, and i have to sleep tonight, too :-)

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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