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Re: [f-cpu] CAS in FC0

On Tue, Mar 19, 2002 at 03:29:28AM +0100, Yann Guidon wrote:
> in fact, the real problem is to think of CAS as an "instruction".
> Things become _so_easy_ if we use a combination of instructions !!!
> We do not need any "CAS instruction" but a variant of the usual
> load and store instructions, just like the locked versions in ALPHA
> (and other CPUs).
> * "load locked" will "tag" the line it selected for reading. it's just a bit
> that the issue logic has to set after decoding the instruction.

Or a bunch of bits (e.g. one per byte, or maybe 64-bit word, inside the line).

> * "store conditional" will proceed if two conditions are met : the specified
> condition is true (we can check for LSB, MSB, zero...) and the "tag" is still
> set. I often wondered if it was worth it to add a conditional store, but now
> i'm convinced. Except that we need a version that checks the "tag".

> What about the scheduling ? it's almost as fast, if there are all the
> bypass networks !
>   load_tag [r1],r2
>   xor  r2,r3,r4
>   if r4==0 store_locked [r1],r3
> (or something like that)

If a task switch (or IRQ service) occurs between load_tag and
store_locked, the tag may change behind the program's back (it might
be cleared and set again - the ABA problem). In order to avoid that,
a task switch should reset all tags.

Oh btw: store_locked must return an indication that the store succeeded
(that is, it's a 3r1w instruction), and of course it has to clear the tag.

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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