Rep:Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

It's my turn !

-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 20/03/02
Objet: Re: CAS and spinlocks (was: Re: [f-cpu] another DATE report)

On Tue, Mar 19, 2002 at 10:21:38PM +0100, Christophe wrote:
[...]
> > Please go ahead... which details?
> 
> There is no LSU source for example. What are its signals, its
internals ? how
> are the register set and other functional units connected ? etc.

That's something we still have to work on.  I have to admit that I
don't have an exact picture either, so we will have to talk about it,
preferably on this mailing list.

The LSU will probably have

- an interface to the Xbar, similar to the execution units:

>>>I don't like the use of Xbar, we will not use Xbar but buses. Whygee
agree but continue to use the word. I repeat that a Xbar is a matrix of
wire connected by pass-transistor. The 2 main drawback are the slow
speed and the very udge size. Such design are used for routing but we
haven't any routing to do here.

  - a 64-bit address input port
  - a 64-bit data input port (write port)
  - a 64-bit data output port (read port)

>>>Hum. It's depend how you react with it.
From the core point of view, you access it as a "cache" (Whygee(TM)) or
as memory adresse by the register field of instruction for Icache and by
the stream flag for the Dcache (we need that to fight against alias).
Dcache (LSU or L0) could use to 2 line of the L1 cache. So double
buffernig/prefetching could be done.

>>>With this kind of implementation, i don't beleive that we need the
adress of the cached data. It will depend on the invalidating system for
coherency.

>>>From the memory system point of view, the data buses with has the
size of the cache line of the L1 cache. There is a mecanism to give the
adresse from instructions word (prefetch,...) and/or the load and store
unit.

  - mode control lines coming directly from the opcode
   (load/store, operand size, endian, stream hints, flush)
  - an `enable' line indicating that the inputs are valid
 - an interface to the data cache
  (this is not yet clear at all)
 - a number of additional control lines
  (not clear either)

Feel free to add more details...
>>> Done !
nicO

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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