Tr:[f-cpu] usage of 64 registers

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: Martin Devera <devik@cdi.cz>
A: f-cpu@seul.org
Date: 27/03/02
Objet: [f-cpu] usage of 64 registers

Hello,

I'm fairly new in this area as I focus mainly on linux
kernel developement.
But this project impressed me and I started to learn more
about it. I've some question and I hope someone can answer
them (and yes I looked archives first to not repeat FAQ).

First during my developement days I never seen algorithm
(except unrolled loops) which can use 64 regs in one stack
frame range.

>>> Most of the time, if you want to put n (pipeline depth) cycles
between the write of a register and it's read and if you use cmove trick
(to avoid jump), you will have great pressure on the register set, so
you will need so much register (there is no OOO in fcpu). 

Why didn't you consider register rotation ala ia-64 which
allows you to simply generate function calls without memory
ops and to do sw pipelining ?
Also I've heard that there are problems with SPARC's register
window usage, can someone clearify it ?

>>> I beleive it's the same problem : the handler to make room in case
of overflow in the stack of register. In the future, we must consider
such rolling fence.

Second question is, how can be the XBar constructed in CMOS ?
Is 4*64 to 4*64 xbar simply 1024 pass-thru gates (N-P mos pair)
plus tree of invertors to accomodate this fanout ?
Or will it consist of latches per port ?

>>> From my point of view, we can't use that. We will use simples buses,
we don't need a true Xbar !
nicO

Thanks,
devik

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