Re: [f-cpu] delayed issue

[Yann Guidon <whygee@f-cpu.org>]

hi,

Christophe Avoinne wrote:

> From: "Yann Guidon" <whygee@f-cpu.org>
>  
> > > > 2) If you map SRs to memory, you will face race conditions and
> > > > synchronisation problems,
> > > > and protection will not be enforced on a register or register group
> > > > granularity basis.
> > > It's exaclty the same problem for IO register, and it's soon solved.
> > SRs are not for I/O (because it would become a bottleneck).
> > The problem, hence the solution, is not the same.
> >    
> Quite now, I suspected SR to be equivalent to Intel SMR register, that is,
> PUT/GET are equivalent to Intel WSMR/RSMR and not to Intel IN/OUT.
>
> Am I wrong ?
>  
you're right, it is almost the same principle as the MSR (as "Machine 
Specific Registers")
except that the model is much more cleaned. The map preserves 
compatibility across machines
so it's not "Machine Specific". Additionally, it helps keep the 
instruction set simple and short :
there is not a bunch of particular registers with particular instructions
to access them (like : Interrupt table management, page table management 
etc.)
-> everything is in a single, serializing (-> no border effect) space that
is independent for each CPU.

YG

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/