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Re: SR [was:Re: [f-cpu] delayed issue]



hi,

Christophe Avoinne wrote:

Just a precision, the ARM has a coprocessor interface : it can handle with
16 (or 15) coprocessors and has an small uniform set of instruction to help
to communicate between itself and a coprocessor. For example, the MMU
handling is done with the coprocessor number 15. It is a very good idea
because you can transfer ARM registers and CP15 registers to and fro, make
CP15 load or store address, etc. Whygee, if interested, just have a look on
S3C2410, ARM9 isa part and MMU part, where they explain how to handle MMU
coprocessor. That kind of interface could be very interesting for F-CPU to
add external coprocessor and have a more tighly coupled functions.


This idea has also been used by MIPS. Probably SPARC (but i don't remember).

MIPS used this on the R2000 to communicate with the external FPU chip.
They probably had to modify the ISA when the R4000 came with its integrated
superscalar FP pipeline.

If communication with a "coprocessor" is necessary, then i don't see why it can't
go through the SRs. So a more complex "coprocessor interface" doesn't solve
anything. On top of that, the ARM is an in-order CPU, i don't see how it could
go OOOE and still still support the coproc interface at no cost.
F-CPU's SRs imply serialisation so it's safe for the future.

YG

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