Re: SR [was:Re: [f-cpu] delayed issue]

[devik <devik@cdi.cz>]

> >Humm... i think about "true" 4r2w (on liw) but with 1r1w split register
> >bank. The first problem is the use of 3r2w reg bank but 90% of the
> >instruction are 2r1w.
> >
> >
> but not all instructions have the same latency !
> so there are many cases where a "long" instruction will prevent short
> ones to complete.
> The 2nd write port is here to remove 90% of the compiler's pressure to
> detect when
> this situation occurs.

Just one small note. When I played with my simulator I found
that adding 4 entry "delay" buffer at output of EUs it is
possible to about 4/5 of all write contention related stalls.
I onlu don't know whether is it possible to write scheduler
in way it could handle it.
But because you issue AT MOST one insn/cycle (assuming no stalls)
then for 1w ops you should be always able to find free write
cycle.
When I think about it just now, one could simply write results
to delay buffers if there is no free write cycle and introduce
stall when one such buffer is almost full. But can't imagine
complexity just now.

good night,
devik

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