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[f-cpu] New VHDL Stuff
Hi F-gang!
I'm going to upload my latest sources to seul.org tonight; look for
http://f-cpu.seul.org/~f-cpu/new/fcpu-mr-20030327.tar.gz.
As I already mentioned, there are new INC and CMP units. I also improved
the adders in EU_ASU and EU_IMU, and added new functions to the ASU and
SHL units (see the list of changes below).
While playing with the multiplier again, I noticed that it may be possible
to integrate a `scalar product' function without increasing the latency
of the unit. That function would multiply its operands in SIMD mode,
delivering double-width temporary results, and then add all the temporary
results and produce a 128-bit sum, with only minimal hardware overhead.
The latency will be 6 cycles regardless of the chunk size, with chunk
sizes of 8...64 bits supported (in 64-bit mode, the function is identical
to `mulh'). I don't know if it will support signed multiplications,
but I guess it should be possible. Does that sound useful? I believe
it may be an alternative to mac/amac in some cases.
Changes:
* eu_asu/iadd.vhdl:
- auto-sizing unit (WIDTH must be a multiple of 64)
- new increment-and-add and average operations
- improved adder stages
* eu_asu/iatest7.vhdl:
- new (faster) testbench for iadd.vhdl
* eu_imu/imul64.vhdl:
- improved adder stages
- 8/16/32/64 bit timing is now 3/4/5/6 cycles for both outputs
* eu_imu/im64test4.vhdl:
- additional testbench for imul64.vhdl
* eu_imu/im64testconf.vhdl:
- configuration file for IMU testbenches
* eu_shl/shuffle64.vhdl:
- fixed bitrev operation
- added permute and cshift functions
* eu_cmp/*:
- new integer compare unit (handles cmp/min/max/msb0/msb1)
- auto-sizing unit (WIDTH must be a multiple of 64)
* eu_inc/*:
- new integer increment unit (handles inc/dec/neg/abs/lsb0/lsb1)
- auto-sizing unit (WIDTH must be a multiple of 64)
--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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