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Re: [f-cpu] New VHDL Stuff - Xilinx synteheis report



hi !

devik wrote:

Hi,
I tested to synthetize units for relatively cheap Xilinx
Spartan xc2s200-5 with 2352 slices. In all tests I used
about 100 slices for testing environment. Numbers below
are totals with my logic included.

ASU: 601 slices, 69 MHz
MUL: out of memory (have only 150MB swap in vmware)
SHL: recursion detected in 'shift_map'
INC: many messages like
Signal <a59<34>> is used but never assigned. Tied to value 0.
WARNING:Xst:821 - C:/xilinx_webpack/ISEexamples/fcpu/bit_manipulation.vhd
(Line 269). Loop body will iterate zero times
258 slices, 128 MHz but I expect problems here
CMP the same.

Loop body will iterate zero times error can be fixed by adding explicit
IF to reduce_or. But other errors :( Probably XST synthetizer can't
handle some things.

at least the ASU works ;-D

-------------------------------
Martin Devera aka devik

YG

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