Re: [f-cpu] Status quo

[Christophe Avoinne <christophe.avoinne@xxxxxxxxxxx>]

> All I can think of is "bit field extraction/insertion"
> (though it's
> not used by arithmetic coding)
> and I think
> it's more or less possible to have it in the
> instruction set. I don't
> remember if we have that instruction

Just my two cents:

for zero extension of 8, 16 or 32-bit word into 64-bit word, a bit field 
extraction instruction is enough:

x86                  <=> new CPU
movzx rax, al <=> BEXT(ZX) r0, r1, 0, 8 : r0[63-8] = 0, r0[7-0] = r1[7-0]
movzx rax, ah <=> BEXT(ZX) r0, r1, 8, 8 : r0[63-8] = 0, r0[7-0] = r1[15-8],
movzx rax, ax <=> BEXT(ZX) r0, r1, 0, 16 : r0[63-16] = 0, r0[15-0] = 
r1[15-0]
movzx rax, eax <=> BEXT(ZX) r0, r1, 0, 32 : r0[63-32] = 0, r0[31-0] = 
r1[31-0]

it could be interesting to have a bit field extract with sign extension 
as well:

x86                  <=> new CPU
movsx rax, al <=> BEXTSX r0, r1, 0, 8 : r0[63-8] = r1[7], r0[7-0] = r1[7-0]
movsx rax, ah <=> BEXTSX r0, r1, 8, 8 : r0[63-8] = r1[15], r0[7-0] = 
r1[15-8],
movsx rax, ax <=> BEXTSX r0, r1, 0, 16 : r0[63-16] = r1[15], r0[15-0] = 
r1[15-0]
movsx rax, eax <=> BEXTSX r0, r1, 0, 32 : r0[63-32] = r1[31], r0[31-0] = 
r1[31-0]

It would also be fine to have :

BEXT[S|Z]X r0, r1, r2, r3 : r0 is destination (write-only), r1 is source 
(read-only), r2 is lsb position (only-read), r3 is bit count or msb 
position (only-read)

if too many read registers, merge lsb and msb into one register : 
r2[5-0] = lsb, r2[11-6] = msb or count.

Bit field insertion :

BINS r0 (read/write), r1 (read-only), lsb, msb or count ?
BINS r0 (read/write), r1 (read-only),  r3 (lsb ? read-only),  r3 (msb or 
count ? read-only)


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