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Re: [f-cpu] Comment on Manual 0.2.6

A longer reply,

> On the content, I have see one big error on the
> instruction set and some minor mistake :

> * The big error is on the function description of
> "expand" instruction (p.140), it is give :

> " This is the reverse operation of the "mix"
> instruction..."

> This is false, if we look the figure 2.2, take the
> following example :

> r1="12345678" r2="abcdefgh"

> mixl r1,r2,r3 => r3="1a2b3c4d"
> mixh r1,r2,r4 => r4="5e6f7g8h"

> expandl r3,r4,r1 => r1="15263748"
> expandh r3,r4,r2 => r2="aebfcgdh"

> If expand is the reverse operation of mix then r1
> before and after mix and expand sequence must be
> equals.

It's true, and I wanted to start a discussion about this problem. Normally, if 
expand is the reverse opertion of the mix operation, it must be a 1r2w. So we 
must correct the manual. I don't know how currently, perhaps by saying that 
mix is used with expand to pack/unpack data in SIMD operation.

> * Some minor errors are into example of "sub" and
> "addsub" instructions (p.80 and 93).

> I am not a genius;-), but if r1=r2-r3 and r3 <= r2
> then r1 >= 0 :-P.

> With : r1=0x05 and r2=0x07
> We have : sub.b r1,r2,r3 => r3=0x02 in any case

> and if (r1)+1=r2-r3 and r3 <= r2 then (r1)+1 >= 0 :-P.

> with : r1=0x23 and r2=0x36
> We have : addsub.b r1,r2,r3 => r3=0x59 and r4=0x13

I never take the time to read sample, but that a good idea.

> * In chapter 3.3 (p.54) in paragraph 4, the text
> "...number is cleared : 0>1, 11>10..."  must be
> replaced by "...number is cleared : 1>0, 11>10..."

> On the presentation aspect, I have many remarks :

> * It is better if chapter (and Part title) begin on
> the right page (I have made a recto-verso printing and
> lot of chapter began on left page).

I will look what the result of a recto-verso printing is and correct it if 
necessary for next result.

> * In part IV - advanced topics, the text before the
> chapter 1 (p.59) can be included into a chapter named
> Overview.

> * It seems missing a mandatory package into the tex
> header, because all the mathematic symbols like sqrt
> is transforme, likewise with "r1+1" (to say the r1's
> follower register) wich become : r1&1circ;

I think you read an old manual, currently it's r1 ^ 1, that mean r1 xor 1.

> * It is better if we begin the Instruction Set section
> by a "notation" section where we gave the syntax
> legend, like "When an instruction is given into the
> description of function object, it is write into
> italic bold" in example. In that case, we can remove 
> the " into description of addi (p.95) into "...to the add"
> instruction..." ;-)

It's an idea.

> * In Performance section of each instruction, the
> "Execution Unit" name could be followed by its short
> abbrev.


> * Into chapter VI.2, the "Flag" definition tables
> overflow on the right side (and I miss the end of the
> definition)

> * For "bitop" and "bitopi", the F tables aren't
> similar of presentation used with other instruction,
> more the "bitopi" and the "bitop" format presentation
> are different one give F only inside the "Flag"
> definition, the other give it into the flag and
> outside.

In fact we have an other problem with bitopi, it's an other form of 
instruction (6 bits immediate).

> * The following instructions haven't the same bits
> ordering, inconsistent with the the format description
> gived into chapter V.2, than others: "logic",
> "logici", "move", "loadaddr".

I don't see the problem with this instruction.

> * In chapter VI.4 on floating point operations, a
> default operator size must be given.

What did you mean by a "default operator size" ?

> * In chapter VI.5, to describe the endian flag, the
> presentation must be uniformized on the model of other
> parameter (1 if big endian => loade by example).
> * In paragraph VI.5.2.5, it missing the format
> description and the flag explanation.
> * In paragraph VI.5.2.6, the memory level postfix must
> be lowercase.

> * In "move" and "jump" instructions, the conditions
> postfix "-nz, -nm, -nl" are redundant with the Flag 10
> definition. More the Condition definition table and
> the Flag definition tables must be coherent => merge
> bit 10 to 12 under name Condition oder split them like
> negation/condition and adapt the second table.

I think it solved in manual 0.2.7.

> Some spelling mistakes:
> * In chapter III.3.4 (p.55): "...For these reason, it
> would is difficult..." must be replaced by "...For
> these reason, it would be difficult..."
> * In chapter IV.1 into the third cause (p.61):
> "...otherwise the result will sturate..." must be
> replaced by "...otherwise the result will saturate..."
> * In chapter V.1 (p.69) in second paragraph: "For the
> F-CPUU..." must be replaced by "For the F-CPU..." and

I think you read manual 0.2.6 ;-)

> "...(ISA) faces a lot of constraints and
> evolitivity..." must be replaced by "...(ISA) faces a
> lot of constraints and evolutivity..."
> * Into the Instruction set draft section, you have
> many "...wrap"..."

I will correct all this mistake during the week-end and I will post a new 
unstable manual (0.2.7b) monday or tuesday.

> Other topics:
> * In chapter IV.3-Scheduler (p.66), what meens: "On
> average, it is propable that the 2 write ports of the
> register set are used 70the data is actually
> available"
> I don't understand "70the" :-?

Me too...

> * In chapter V.1 (p.69), the figure 1.1 and the text
> are inconsistent with the instructions format
> description gived into chapter V.2 (p.71) (same
> remarks on chapter V.2 text).
> Into the description, the opcode is localized into bit
> 31 to bit 24 position, which is a MSB position, and
> the destination register is given on LSB position.

I forgot to correct this in 0.2.7...

> * In case of "popcounti" : If the Imm8 parameter is
> really optional, we can add a remark to signalized
> than "popcount" is functionnaly equivalent to
> "popcounti" without r3 and Imm8

I will update 0.2.7 manual with your remark. It's nice to know that somebody 
totally read the manual ;-) But did somebody read the 0.2.7 manual ?

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