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Re: [f-cpu] Glossary
On Mon, Nov 24, 2003 at 09:28:15PM +0100, Beat Steiner wrote:
> For my own convenience, I started to wirte a f-cpu glossary.
> <td valign="Top">CMB<br>
> <td valign="Top">Context Memory Block<br>
> The CMB holds the state of any task in such a way that it can be stopped<br>
More precisely: When a task is suspended, the -> SRB will save its
state to the CMB. When the task continues, the SRB restores its state
from the CMB. The CMB is NOT continuously updated to reflect the
current state of the running task.
> The CMB holds the access rights and the most important protection information<br>
Only in minimal form, I guess.
> The CMB holds the pointer to the task's page table (when paging is enabled).<br>
We don't use page tables. It's more likely that the CMB will hold an
-> ASI (Address Space Identifier). That's a not-too-small integer
(perhaps 8...16 bits) that will be combined with the virtual address
before the -> TLB lookup is performed.
> <td valign="Top">IPC<br>
> <td valign="Top">
> <li>Inter Process Communication</li>
> <td valign="Top">LFS<br>
> <td valign="Top"><br>
This usually means "Linux From Scratch" or "Log-structured File
> <td valign="Top">M2M<br>
> <td valign="Top">Memory to Memoy architecture<br>
> <td valign="Top">PFQ<br>
> <td valign="Top"><br>
That might be a "PreFetch Queue", but I'm not sure.
> <td valign="Top">Register<br>
> <td valign="Top">A variable directly stored on the CPU. Provides fastest
> data access.<br>
Well, registers aren't strictly variables. One of them is actually a
constant (r0 always contains 0).
You should also mention Special Registers (SRs). They hold
miscelleanous information, configuration and status bits and so on.
Some of them are read-only, some are writable in "supervisor" mode,
and some are also writable in "user" mode.
> <li>Is a register waiting for being written to? If yes, an instruction
> wanting to read from it has to wait.</li>
Yes. There will be an "in flight" bit somewhere (though probably not
inside the scoreboard).
> <td valign="Top">SHL<br>
> <td valign="Top">Bit Scrambling Unit<br>
"Bit Shuffling Unit" is probably more intuitive.
There are also, in alphabetical order:
ASU - integer Add/Subtract Unit
CMP - integer CoMPare unit
FPU - Floating-Point Unit (not implemented yet)
IDU - Integer Divide Unit
IMU - Integer Multiply Unit
INC - INCrement unit
> <td valign="Top">Smooth Register Backup<br>
> <td valign="Top">On a -> context switch, the registers must be
> backed up before the new context can write to them. The old context assumes
> no foreign manipulation of the register contents and can only continue with
> restored registers it reads. The backup and restore process takes place out
> of order, i.e. the first register being written to by the new context is
> backed up first.<br>
"out of order" is correct. The exact "priority strategy" isn't cast
in stone yet, though. The SRB may begin saving/restoring registers
in-order until a "priority request" for a particular register arrives.
> <td valign="Top">SMP<br>
> <td valign="Top">Symmetric MultiProcessing<br>
Not appropriate. The F-CPU will not support the construction of SMP
systems. As in the AMD Opteron, there is no shared frontside bus,
and memory is local to the CPU. Multi-processor F-CPU systems will
therefore be NUMA (or probably COMA) systems.
> <td valign="Top">SMT<br>
> <td valign="Top">Simultaneous MultiThreading -> thread<br>
Some people also call this "Hype(r)Threading" ;)
> <td valign="Top">Thread<br>
> <td valign="Top">A sequence of instructions. A program consists of
> one or more threads.<br>
That's a user- or OS-level abstraction that is not really useful.
In CPU terms, we have an "execution context" that may map to a task
or a thread, depending on the OS and the application.
> <td valign="Top">TLB<br>
> <td valign="Top">
> <dt>Translation Lookaside Buffer. A -> cache for mapping virtual
> to physical addresses.<br>
"lookaside" is an Intel term, and on IA32, the TLB really is a cache
(for the page tables). In an F-CPU, it's an array of virtual->physical
mapping entries that is maintained by the OS. That is, it is directly
accessible (as opposed to a cache which is transparent to software).
> <td valign="Top">TTA<br>
> <td valign="Top">Transfer Triggered Architecture<br>
IMHO still interesting, but doesn't apply to the F-CPU.
> <td valign="Top">VHDL<br>
> <td valign="Top">V??? Hardware Description Language<br>
VHSIC Hardware Description Language, where VHSIC stands for
"Very High-Speed Integrated Circuit".
> <td valign="Top">VLIW<br>
> <td valign="Top">Very Large Instructon Word<br>
AFAIK, the attribute was "long", not "large".
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"
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