Re: Re: Re: [f-cpu] X-Bar replacement and PoC of massiv-parallel-computing, hint

[whygee@club-internet.fr]

hi !

Kim Enkovaara <kenkovaa@cc.hut.fi> :
>On Wed, 10 Oct 2001 whygee@club-internet.fr wrote:
>> >You'll have to decode two `tits' (Ternary digITS ;) into 3 bits, then.
>> >Everything else is too complex.
>> 
>> on top of that, "digital" CMOS is not suited to "analog" functions
>> (the tolerances and the library cells are not available).
>
>It is not well suited but there are analog cells that are used with
>digital processes. For example PLLs and higs speed LVDS links. Those are
>always full custom blocks and quite often provided by the vendor. I know
>that they are not fun to do with digital process :)
>
>For example 2.5Gbit/s LVDS link is quite normal stuff with 0.18u digital
>processes. Those blocks have even analog functionalities (pre-ephasis for
>the signal etc.)

You are certainly right but
 - i don't think that internal databuses can use LVDS :-)
 - three-level logic (or more) is not immune to all the R/C/L problems
   (Xtalk, power noise, etc)
 - we don't have any widespread library and support tool for this...
And our goal is to develop a CPU, not a processing technology :-)

read you soon,

>Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
YG

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