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Re: [f-cpu] registers



hi !

Christophe Avoinne wrote:

>>Mohamed Ali Kilani wrote:
>>
>>>Hi Michael, All,
>>>      
>>>
>><snip division>
>>
>>    
>>
>>>By the way, I have a general question about SIMD registers. I have
>>>read in the manual that any 64 bit general purpose register would have
>>>a flag indicating if it is a SIMD register or not. how about the SIMD
>>>mode? i.e: 8x8 bits vs 4x16 bits vs 2x32 bits ? Are we assuming a
>>>default mode or any of the three is allowed?
>>>      
>>>
>>i am not sure to understand you, here.
>>are you speaking about the internal units or the register set ?
>>
>>- The instructions contain 3 bits : 1 SIMD flag and 2 size flags
>>- These flags are converted in any other necessary representation,
>>    for example 3-bit or 4-bit encoded, and sent to the EUs.
>>- The register set does not contain flags about whether data is SIMD or not.
>>    
>>
>>   there are flags indicating whether each register is a pointer (and
>>whether
>>   it is a valid one) but that's all.
>>
>
>okay, the SIMD flag is not stored in the register-bank but in the opcode of
>an instruction to tell the unit if it must compute in SIMD mode or not.
>  
>
yup.

>for 64-bit architecture :
>
>add.8 R1,R2,R3 -> bit SIMD = 0 => R3[31..0] = R1[31..0] + R2[31..0]
>  
>
not exactly : it's R3[7..0] = R1[7..0] + R2[7..0]
(copy-paste error ?)

>add.16 R1,R2,R3 -> bit SIMD = 0 => R3[15..0] = R1[15..0] + R2[15..0]
>add.32 R1,R2,R3 -> bit SIMD = 0 => R3[31..0] = R1[31..0] + R2[31..0]
>add.64 R1,R2,R3 -> bit SIMD = 0 => R3[63..0] = R1[63..0] + R2[63..0]
>
>sadd.8 R1,R2,R3 -> bit SIMD = 1 => R3[7..0] = R1[7..0] + R2[7..0]
>                              and R3[15..8] = R1[15..8] + R2[15..8]
>                             and R3[23..16] = R1[23..16] + R2[23..16]
>                             and R3[31..24] = R1[31..24] + R2[31..24]
>                             ...
>                             and R3[63..56] = R1[63..56] + R2[63..56]
>
>sadd.16 R1,R2,R3 -> bit SIMD = 1 => R3[15..0] = R1[15..0] + R2[15..0]
>                               and R3[31..16] = R1[31..16] + R2[31..16]
>                               and R3[47..32] = R1[47..32] + R2[47..32]
>                               and R3[63..48] = R1[63..48] + R2[63..48]
>
>sadd.32 R1,R2,R3 -> bit SIMD = 1 => R3[31..0] = R1[31..0] + R2[31..0]
>                               and R3[63..32] = R1[63..32] + R2[63..32]
>
>Now do you understand better ?
>  
>

Now it should be even more clear :-)

Concerning the flags that go to the units, they can be transcoded in the 
decoder.
One is not forced to using the 3-bit field coming from the opcode, there 
are 2 clock
cycles before the operation starts (decoder + Xbar) and it is enough to 
do the fanout
and recoding.

YG

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