Re: [f-cpu] New way of doing testbench

[Kim Enkovaara <kenkovaa@cc.hut.fi>]

On Mon, 10 Sep 2001, nicO wrote:

> Kim Enkovaara a écrit :
> > 
> > Usually the interfaces to simulators are the difficult part of new
> > Verification languages and class libraries. The biggest commercial
> > simulators are usually well supported. Altough all features are not
> > supported in all simulators. For example Vera supports Temporal
> > expressions only with VCS currently. With Verilog the interfaces are
> > usually easier because PLI is well standardized. There is not yet standard
> > FLI for VHDL.
> > 
> 
> I think that they used the PLI interface, it's quite easy to interface
> it to the vhdl signal.

At least in commercial simulators PLI can be only used with Verilog code.
They have different interfaces for VHDL. For example with Modelsim Vera
used PLI interface for Verilog and FLI for VHDL. I know that in dual
language simulators you can use Verilog wrapper around VHDL code and that
enables PLI.

Also one problem is that usually these languages use quite extensivily the
PLI interface and require almost complete implementation. Also the
wrappers contain fixes for bugs in commercial simulators (at least used to
contain).

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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