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Re: [f-cpu] binary streams


Kim Enkovaara :
> On Thu, 13 Sep 2001, Yann Guidon wrote:
> > > > by the following code :
> > > ...
> > > >     variable c : character;
> > >
> > > I think this is the problem. Define this as bit_vector or
> > > std_logic_vector. After that binary mode reading should work. Character is
> > > defined differently.
> >
> > i am not sure to understand what you said.
> >
> > I have already tried (well, with simili) to output std-ulogic_vectors
> > and it uses one byte per bit (each bytt represents the different possible
> > states of the corresponding bit). i don't understand what you mean by
> > "Character is defined differently." I have read two (rather exhaustive) VHDL
> > books in the subject and they did not address that point.
> For character definition check the VHDL language definition. Character is
> defined as:
> type character is ( nul,soh,stx,etx.....);

yes, i have read that. also, i remember that VHDL'87 defines the 7'bit
ASCII code while '93 uses the whole 256-code map (IIRC)

> In some simulators I remeber seeing bug reports about the behavior of
> character when considered as just byte. I just tried with Modelsim 5.5d
> and the character version works just fine also.
glad to know that :-)

> On the other hand
> the version I tought (type foo is range 0 to 255) was little odd. It read
> whole integers and didn't even complain that the values were out of
> range, but that might be OK, the files were identical. I don't have LRM in
> my shelf. The bit_vector came from one of my old test benches and that
> actually was reading bits directly, sorry.
> And about VHDL books, the only good one I have found is "The Designers
> Guide to VHDL, Peter J Ashenden" There is a new edition of the book also,
> that just came.
Graham has the 2nd edition and it is very good :-)

There's another one, i think the titke was "Designers's guide to VHDL"
or something like that (dark green book with around 600 pages). This one
is almost exhaustive and also helped me well.

> And the Students guide to VHDL by the same writer is also
> good book, but quite limited. For synthesis the best material is from
> Synopsys training courses and FPGA tool manuals.
these are not free or available to the non-customer, i presume :-/

> =============================================================================
> Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
> Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
> 02630 Espoo         |                      | write-only file system
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