Re: [f-cpu] Re: genereic_adder patch

[Yann Guidon <whygee@f-cpu.org>]

hi,

Michael Riepe wrote:
> On Sun, Sep 16, 2001 at 01:43:56AM +0200, Yann Guidon wrote:
> > Here is a tiny modification to Michael's generic adder package.
> > The newest version of simili doesn't like the way the agregate
> > was used, but it is not too difficult to work around it.
> Yep... I had to do this several times, too.
i'm waiting for your updated "MR official" version :-)

> > Concerning the different way to initialize the signals
> > with random, i search an elegant and cheap way to bypass
> > the limitation imposed by Vanilla.
> >
> > As written before, Simili accepts this :
> >   Signal s : std_ulogic_vector(N downto M) := random(s);
> You mean, you use `s' before the definition is finished?
> That looks broken, somehow.
that #should# work. i don't remember why and how, or where i have
read it. At least Simili does it.

> > But i am forced to write this if i want to use Vanilla :
> >   Subtype t is std_ulogic_vector(N downto M);
> >   Signal  s is t := random(t'(others=>'0'));
> 
> Try to overload random, like this:
> 
>         function random (bits : natural) return std_ulogic_vector is
>                 constant tmp : std_ulogic_vector(bits-1 downto 0) := (others => '0');
>         begin
>                 return random(tmp);     -- this is the original function
>         end random;
> 
> and then write
> 
>         signal s : std_ulogic_vector(N downto M) := random(N-M+1);
> 
> or maybe
> 
>         signal s : std_ulogic_vector(N downto M) := random(s'length);
> 
> if the tools grok it.

mmmmm overloading comes to rescue us :-)
that's what i call irony :-P
[i mean : it is sad that a complex and misleading feature comes
 to relieve you from the non-implementation of a simple feature]

i'll try your trick, thank you :-)

>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
WHYGEE
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