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Re: [f-cpu] Something new to play with :)

hi !

Michael Riepe wrote:

thanks. I did not look at it (yet) though.

When i was at Graham's library, her, home,
i read a few books about networks and interco.
In the F-CPU we have a very tough environment.
I think that an Omega network would be the
minimum degree of 'smartnes'. However i would
like to design a network with an increased
number of stages but "thinner" stages than Omega.
The problem is that when you have a 64-bit wide
omega network, the "critical datapath" can be
represented as the lenght of the longest wire
in the slice, and Omega needs to cross at least
32 wires in the CDP (and that's a lot). If what
books say is true, the delay through an IC wire
is roughly proportional to the square of the
length (which can be modeled as a string of RC cells).

If we adopt a "cell" composed of 4* 4-input
multiplexers, we will "need" 3 Omega slices but
it is not dangerous to increase the depth (to 5 or 6)
if we reduce the crossings and wire lengths.
If we reduce the length of one wire by two, there's
a 4x win.

However Omega has a very very interesting feature :
it belongs to a family where the "address" (binary number
that says how much you shift) needs almost no decoding
before feeding the mux inputs.
One hidden drawback that is inherent with the first
naive approach of the transistor array is that the
decoding of the individual 4096 transistor gates
"takes" much time.

I believe (warning : gut feeling ahead) that if we have more
than 3 stages made of 16*4* 4-input muxes, the decoding
will not be too hard. below that point (the "naive approach"
being an example) we need a significant decoding logic
(time and space).

Food for thought.

Once the MDK8.0 is installed on my laptop, i'll integrate
Michael's latest files. And Cadence, too.
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