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[f-cpu] Barrel Shifter

The conversation today seems related to the Barrel Shifter.  Keep in mind that my design is M2M with a 32 Bit Shifter.  The Shifter uses 4-input Multiplexers and requires three logic levels, plus a 32 bit, two input mux on both the input and output.  The two input mux's are for Bit Reversal to use the array for both left and right shifts.  A Normalize function is burried in there for BOTH the Normalize and Arithmetic Shift Left.
With the above in mind-----the array has an execute time of 13.0 NS.  This is
77 MHZ if talking about stand alone time.  It requires 181 Logic Cells including Buffers for circuit loading of Max 8 loads. 
For your info - an And/Or function is a Two input mux.  And - - -
        An 8 Bit Shifter = 1 logic level
        An 16 Bit Shifter = 2 logic levels
        An 32 Bit Shifter = 3 logic levels
        An 64 Bit Shifter = 4 logic levels
        An 128 Bit Shifter = 5 logic levels
The above uses the Quicklogic data from the QL6600 printout.
Dick Hartney