Re: [f-cpu] Something new to play with :)

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:
> On Mon, Sep 24, 2001 at 12:59:39PM +0200, Yann Guidon wrote:
> > hi !
> > Kim Enkovaara wrote:
> > > On Sat, 22 Sep 2001, Michael Riepe wrote:
<ciao>
> > > Speed: 66MHz (optimized for speed, no special tricks)
> > wow :-)
> > what is the fastest thing you have synthesised for this device ?
> That's nothing -- the multiplier was faster :)
> But I'm quite satisfied with that result.
does that mean that you have something better in mind ? :-)

> > > Utilization: 30%
> > wow :-/
> > How big is it btw ?
> The multiplier also took something like 30%.  The SHL EU is very
> space-consuming...
yep. From the other mail i wrote, i might come from the wires
(which btw make P&R more difficult in a 2D frame).

> > > btw. the muxes are quite huge :) FPGA architectures usually have some
> > > problems with complex multiplexer structures.
> > this is why i prefered to use 4-in muxes :-)
> Too big for most FPGAs.  All you can do with 4-input cells is a 2:1 mux.
read my other mail that answers to Richard. This puts the pressure
on the decoder, OTOH. With some smart thinking it maybe be possible
to find a suitable trade of between the cascade of OR and the decoder
complexity.

> > Can you track where the critical datapaths are located ?
> I guess it's in the control logic for stage 2.
ggggrrrrrr i'll have to look at the sources :-)

read you soon,
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE who got himself a 20-bit Flying Calf for a nice price :-)
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