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Re: [f-cpu] Bit Shuffler (Take 2)
Kim Enkovaara wrote:
> On Sat, 29 Sep 2001, Yann Guidon wrote:
> > > Synplify usually likes as high level descriptions as possible. But I think
> > > that optimizing for speed at this stage is not wise thing to do.
> > how do you tell Synplify to pipeline the multiplier ? and how do you instruct it
> > to provide partial results ?
> Easiest way to do that is to write a*b in the VHDL and add as many
> fliflops after the operation as you need pipeline stages. Then just ask
> the Synplify to balance the registers. In that way it creates very well
> optimized pipelined multiplier. Also if the FPGA architecture includes HW
> multipliers it uses them during the synthesis. In VirtexII architecture
> synplify can't use the internal flipflops of the 18x18 multiplier, but
> those flipflops are not documented or characterized at the monent, but
> they are there.
coool ! i didn't know this trick :-) So we can try to "fit" the multiplier
depth according to the clock speed and vice versa, simply by "tuning" one
constant in the source ? i like that :-)
> > > First you need a working chip and testbenches around it. After that it is easy to
> > > recode some blocks for ASIC and FPGA for example.
> > it won't be easy if we did not foresee the necessary requirements.
> Good rule of the thumb is that best ASIC processes are 10 times faster
> than the fastest FPGAs for normal logic. For example one vendor promises
> about 30 levels of logic at 600MHz with 0.13u process. And the fastest
> FPGAs are quite expensive, you can buy a small car with few of them :)
i know. However F-CPU is "superpipelined" so the ratio is reduced a bit.
The goal is more to "use whatever ressource we have" rather than competing
at the high level (we would never win).
> > Today, now that i see that i can code something, i wonder : what is the best
> > way to write stuff so it runs as fast as possible. I know that if i start to
> > write VHDL "the usual way", the result might be disapointing. If a large part
> > of the CPU is designed this way, it won't hold its promise. People will work
> > on underefficient designs and it will be too late. This is particularly
> > worrying in the control path (scheduler). I trust Michael for the rest.
> I think the only way to see the results is to synthesize the results
> yourself and analyze the results from the shematics. It is very difficult
> to analyze the results if the code is not written by yourself.
I almost got the Cadence soft. In fact it still doesn't work, i have to
configure the Linux kernel... But it's only a matter of time !
Now i am pretty sure that i will be doing F-CPU as doctorate project.
This year is going to be VERY difficult but in the end the horizon is bright.
I will be concentrating on synthesis this year so most tools will be ready
> Mr. Kim Enkovaara
PS: who knows how to disable the kapm-idled deamon from Linux ?
it's eating up CPU power and heats the CPU of the laptop :-/
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