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Chuck & Support
I want to thank both of you for
your very good support. The Erin64 Processor gave me some very good performance
numbers. It was my original intent to use two of these in each system; one
for Language (9,976 instructions) and one for Peripheral processing. (System
Dependent)
I did a little brainstorming and
will use an almost total change of concept. I will still use the
Erin64 for Peripheral processing. Now comes the change of
concept.
I will use the On-Chip Ram for
Instructions and operands. I will use 12 Ram Blocks for instructions
(512 x 54), and 16 Ram Blocks for Source/Destination Data.
(512 x 64). This will almost negate the need
for SSRAM off chip. In addition I will use one Ql6600 for EACH of the
Operating system Language processes. This will require approx 30 - 35
devices where access to the Operator (chip) is accessed via Interrupt. The
device will contain ONLY those functions required by the
sub-routine
which it Emulates and contains a four instruction
pipeline. Scheduling these requests is a concern but not a major one, as the
software contains a Skedular. For highly re-entrant routines I will use
duplicate functions to prevent a log-jam; however a little math says it won't
happen. (128 Users typing at 100 Words per minute) or using mouse/lightpen
selections.
Back to work - QUESTIONS????
Dick Hartney
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