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Re: [f-cpu] F-CPU fetch unit
hi,
Bogdan Petrisor wrote:
Also it seems that there is a need to sometimes instruct the fetcher to begin fetchig from an
address that is in the register set. Is this right so far?
right.
This happens so that said register is "associated" or "mapped" to a Fetcher's line.
The allocation is quite complex because all the above feature work together at the same time.
unwanted side effects will maybe prove difficult to remove.
But this latency must be hidden by an explicit prefetch.
are there only N_LINES register that can be associated to the Fetcher or any register can be
associated with any line?
that's a big implementation headache ...
ideally, anything should be able to be "associated" to anything.
but electronics have their own rules and we have not yet found
a suitable solution yet. creating a one-way table is really easy,
BUT this is a two-way table and invalidation of an entry
(for example, when a register was previously mapped
to a Fetcher's line, and an instruction changes the contents
of this register, OR when a line is flushed by the LRU mechanism)
is difficult to do with a reduced number of transistors.
That's one reason why i started to play with the VSP :
the core is much more simpler than FC0 but the memory interface
is quite similar and keeps most complex features.
read you soon,
I took a look now over it. Is it only done in javascript or is there also some VHDL?
currently, there is Javascript stuffs, and some old VHLD attempts
for some execution units (adapted from existing FC0 sources)
but nothing to die for.
YG
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