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gEDA-bug: Adding Vdd caused schematic to fail DRC



Summary: adding a Vdd symbol to a schematic causes a DRC failure.

Description:
I have a schematic which contains both components that use Vcc and their power symbol and components which use Vdd as the power symbol.


I am attempting to place both a Vcc and a Vdd power object onto the output of the voltage regulator for the project to tie both nets to the power supply. Adding a Vcc-1 symbol causes no errors, but adding a Vdd-1 object causes the following warning on DRC:


WARNING: Trying to rename something twice: Vdd and Vdd are both a src and dest name This warning is okay if you have multiple levels of hierarchy! WARNING: Trying to rename something twice: Vdd and Vdd are both a src and dest name This warning is okay if you have multiple levels of hierarchy!