gEDA-bug: Lines and Vias allowed to fail Polygon Clearance DRC

[Hugo Elias <hugo@xxxxxxxxxxxxx>]

Hi there,

PCB seems to allow you to create lines which fail the DRC.

To reproduce this effect:
 Draw a polygon
 Draw a line through it.
 Press shift + K over the line, several times, to reduce the
 clearance, until the clearance stops reducing.
 Run the DRC.

The line fails the DRC.  Surely, if PCB provides a lower limit
to the clearance, that lower limit should pass the DRC?

The Minimum Copper Spacing in PCB preferences is 7.0 mil.

Looking at the file, the line is:
   Line[11900 34800 20400 34800 1000 1398 "clearline"]

The DRC setting at the top of the file is:
   DRC[699 400 800 800]

So, 1398 is exactly twice the DRC value of 699, so the line
should pass the DRC, but for some reason it fails.


Hugo Elias




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