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gEDA-bug: [Bug 821618] Re: Very basic concatenated net support for verilog netlister
** Patch added: "Updated gnet-verilog.scm to support basic concatenated net naming"
https://bugs.launchpad.net/bugs/821618/+attachment/2256752/+files/gnet-verilog.scm
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https://bugs.launchpad.net/bugs/821618
Title:
Very basic concatenated net support for verilog netlister
Status in GPL Electronic Design Automation tools:
New
Bug description:
I couldn't find a way to submit an updated netlister backend so
figured this was the best path. I modified gnet-verilog.scm to support
the basic verilog format concatenated net naming like {a,b,c[3:0]}.
Attached is my updated gnet-verilog.scm.
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