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gEDA-bug: Strange behavior in pcb regarding the DRC.



I have discovered a strange behavior in pcb's design rule checker.
There is a 5mil by 5mil square that If I cover with a polygon, the DRC complains about insufficient overlap, and says that another trace far away doesn't have enough clearance. It doesn't matter how large I make the rectangle that covers the 5x5 square.

I initially had two large rectangles covering the area in an L shape, with sufficient overlap, but I was getting the same behavior, so I decided to try and cover as much of the layer as I could without causing the DRC error to occur.Â

I've attached the PCB file.

The 5x5 square in question is @ 1995, 2530 on the layer named V5

Info from about:

This is PCB, an interactive
printed circuit board editor
version 20110918

Compiled on Dec 20 2011 at 21:57:26

by harry eaton

Copyright (C) Thomas Nau 1994, 1995, 1996, 1997
Copyright (C) harry eaton 1998-2007
Copyright (C) C. Scott Ananian 2001
Copyright (C) DJ Delorie 2003, 2004, 2005, 2006, 2007, 2008
Copyright (C) Dan McMahill 2003, 2004, 2005, 2006, 2007, 2008

It is licensed under the terms of the GNU
General Public License version 2
See the LICENSE file for more information

For more information see:

PCB homepage: http://pcb.gpleda.org
gEDA homepage: http://www.gpleda.org
gEDA Wiki: http://geda.seul.org/wiki/Â

----- Compile Time Options -----
GUI:
  gtk : Gtk - The Gimp Toolkit
Exporters:
  bom : Exports a Bill of Materials
  gcode : G-CODE export
  gerber : RS-274X (Gerber) export
  nelma : Numerical analysis package export
  png : GIF/JPEG/PNG export
  ps : Postscript export
  eps : Encapsulated Postscript
Printers:
  lpr : Postscript print

Attachment: dac-board.pcb.gz
Description: GNU Zip compressed data


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