gEDA-bug: [ geda-Feature Requests-2209940 ] Enhancement: Hierarchical Bus handling and netlisting

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Feature Requests item #2209940, was opened at 2008-10-30 15:22
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Category: gschem
Group: None
Status: Open
Priority: 5
Private: No
Submitted By: Nobody/Anonymous (nobody)
Assigned to: Nobody/Anonymous (nobody)
Summary: Enhancement: Hierarchical Bus handling and netlisting

Initial Comment:
From Dan Deisz at Rochester Electronics:
ddeisz@xxxxxxxxxxx

It would be great if gschem handled hierarchical bussing by enabling the bus notation to be more than just a graphic notation as it is today. This would have to include netlisting capability (preferrably for verilog). At my company, we have to re-enter schematics in a hierarchical fashion that includes bussing up and down the hierarchy. If we don't preserve the graphics as they were originally done (about 20 years ago), we won't be able to validate what we have done easily. In addition, the explosion of pins on a single page makes the schematic largely unreadable. Currently, it's looking like we need to go buy a package somewhere that can do this, but I would love to use gschem because it's easier to use.

I know that hierarchical bussing support can almost lead to religious wars as to how it should be handled. From my perspective, I would rather see something done than nothing done for this.

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You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=818429&aid=2209940&group_id=161080


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