gEDA-bug: [ geda-Patches-1566117 ] Script for non-flatten herarchical Verilog netlist

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Patches item #1566117, was opened at 2006-09-26 20:10
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Category: None
Group: None
Status: Open
Resolution: None
Priority: 5
Submitted By: Paul Tan (pt75234)
Assigned to: Nobody/Anonymous (nobody)
Summary: Script for non-flatten herarchical Verilog netlist

Initial Comment:
Description:  
  Generate non-flatten hierarchical Verilog netlist
FileName:   gnet_hier_verilog.sh
version 0.0.2

Usage: 
  [path]gnet_hier_verilog.sh [path]FileName.sch

Requires gawk and gEDA's gnetlist gnet-verilog.scm


1) This is a simple draft bash script to produce a 
hierarchical verilog netlist in a single file.  It 
gathers hierarchical information from a list of unique 
symbols/schematics originating from the top level 
schematic all the way down to the lowest level of the 
design hierarchy. It then successively invokes 
theexisting gEDA verilog netlister to produce each 
single level netlists, and concatinates all the unique 
module netlists into one single hierarchical netlist 
file. 

2) Currently, it assumes that one or more hierarchical 
symbol can be represented by a single schematic file. 
If needed, feature for mutiple schematic files mapped 
to a single symbol can be easily added. In that case, 
multiple source attribare used in that symbol.

3) It checks the follwoing errors while traversing 
down the hierarchy and terminates the netlisting if 
error is found.

3a) if a symbol's source attribute indicated schematic 
can not be found in the search paths defined by gafrc.

3b) if a symbol's device attribute value does not 
match its corresponding schematic's module_name 
attribute value.

4) This script assumes that there are no other errors 
in the entire hierarchy, and that the user has already 
run the DRC. Moreover, it assumes that the user has 
run the single level verilog netlister on each 
schematic in the hierarchy without any error. it also 
assumes that the hierarchy-traverse is disabled in 
gnetlistrc, thus disables flatten hierarchical netlist 
generation.

5) Netlist of modules are listed from top down, can 
easily be changed to do bottom up.

6) Symbol must contain "source=????.sch" attribute to 
have its schematic netlisted. Otherwise, symbol is 
treated just as primitive instances in the netlist.

7) It only uses the gafrc file in the folder where the 
top level schematic resides. The search path for the 
symbols and schematics should be defined in that gafrc 
file. The current implementation searches from the 
beginning of the file, it will be changed to conform 
to the gEDA practice of searching from the bottom 
first.

8) Hierarchy info is output to a report file for 
reference.


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