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gEDA-cvs: CVS update: JD-output.net



  User: sdb     
  Date: 07/04/21 13:14:32

  Added:       .        JD-output.net JD_Include-output.net
                        JD_Sort-output.net Makefile.am
                        TwoStageAmp-output.net
                        TwoStageAmp_Include-output.net
                        TwoStageAmp_Sort-output.net
  Log:
  Created regression test suite for spice-sdb.
  
  
  
  
  Revision  Changes    Path
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/JD-output.net
  
  Index: JD-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb LVDfoo.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  *vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
  *
  .model unknown_LVD (stuff)
  *^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
  *
  *==============  Begin SPICE netlist of main design ============
  V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
  Cm m 0 20p  
  Rt p m 1k  
  M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
  UX1 i 0 LVH m p Vdd1 0 unknown_LVD
  Rlp p Vdd1 1meg  
  Vdd Vdd1 0 DC 3.3V
  Rlm m 0 500k  
  Cp p 0 20p  
  Rb 0 LVH 5.6k  
  .end
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/JD_Include-output.net
  
  Index: JD_Include-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb -I LVDfoo.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  .INCLUDE ./models/openIP_5.cir
  *==============  Begin SPICE netlist of main design ============
  V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
  Cm m 0 20p  
  Rt p m 1k  
  M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
  UX1 i 0 LVH m p Vdd1 0 unknown_LVD
  Rlp p Vdd1 1meg  
  Vdd Vdd1 0 DC 3.3V
  Rlm m 0 500k  
  Cp p 0 20p  
  Rb 0 LVH 5.6k  
  .end
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/JD_Sort-output.net
  
  Index: JD_Sort-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb -s LVDfoo.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  *vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
  *
  .model unknown_LVD (stuff)
  *^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
  *
  *==============  Begin SPICE netlist of main design ============
  Cm m 0 20p  
  Cp p 0 20p  
  M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
  Rb 0 LVH 5.6k  
  Rlm m 0 500k  
  Rlp p Vdd1 1meg  
  Rt p m 1k  
  V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
  Vdd Vdd1 0 DC 3.3V
  UX1 i 0 LVH m p Vdd1 0 unknown_LVD
  .end
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/Makefile.am
  
  Index: Makefile.am
  ===================================================================
  EXTRA_DIST= \
       JD-output.net \
       JD_Include-output.net \
       JD_Sort-output.net \
       TwoStageAmp-output.net \
       TwoStageAmp_Include-output.net \
       TwoStageAmp_Sort-output.net
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/TwoStageAmp-output.net
  
  Index: TwoStageAmp-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb TwoStageAmp.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  *vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
  .model 2N3904   NPN(Stuff
  +               More stuff
  +               Yet more stuff
  +               Final line of stuff)
  *^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
  *
  *==============  Begin SPICE netlist of main design ============
  Cout VColl2 Vout 2.2uF  
  R5 Vin 1 10  
  R4 0 Vbase2 2.8K  
  RE2 0 Vem2 100  
  Q2 VColl2 Vbase2 Vem2 2N3904 
  .options TEMP=25
  R3 Vbase2 Vcc 28K  
  .INCLUDE Simulation.cmd
  RE1 0 Vem1 100  
  Q1 Vcoll1 Vbase1 Vem1 2N3904 
  R2 0 Vbase1 2K  
  Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
  R1 Vbase1 Vcc 28K  
  C2 2 Vbase2 2.2uF  
  CE2 0 Vem2 1pF  
  C1 1 Vbase1 2.2uF  
  CE1 0 Vem1 1pF  
  R8 Vcoll1 2 1  
  VCC Vcc 0 DC 15V
  RC2 VColl2 Vcc 1K  
  RC1 Vcoll1 Vcc 3.3K  
  RL 0 Vout 100K  
  .end
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include-output.net
  
  Index: TwoStageAmp_Include-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb -I TwoStageAmp.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  .INCLUDE ./models/2N3904.mod
  *==============  Begin SPICE netlist of main design ============
  Cout VColl2 Vout 2.2uF  
  R5 Vin 1 10  
  R4 0 Vbase2 2.8K  
  RE2 0 Vem2 100  
  Q2 VColl2 Vbase2 Vem2 2N3904 
  .options TEMP=25
  R3 Vbase2 Vcc 28K  
  .INCLUDE Simulation.cmd
  RE1 0 Vem1 100  
  Q1 Vcoll1 Vbase1 Vem1 2N3904 
  R2 0 Vbase1 2K  
  Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
  R1 Vbase1 Vcc 28K  
  C2 2 Vbase2 2.2uF  
  CE2 0 Vem2 1pF  
  C1 1 Vbase1 2.2uF  
  CE1 0 Vem1 1pF  
  R8 Vcoll1 2 1  
  VCC Vcc 0 DC 15V
  RC2 VColl2 Vcc 1K  
  RC1 Vcoll1 Vcc 3.3K  
  RL 0 Vout 100K  
  .end
  
  
  
  1.1                  eda/geda/gaf/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort-output.net
  
  Index: TwoStageAmp_Sort-output.net
  ===================================================================
  * /usr/local/src/geda/gaf/gnetlist/src/gnetlist -g spice-sdb -s TwoStageAmp.sch
  *********************************************************
  * Spice file generated by gnetlist                      *
  * spice-sdb version 2.10.2007 by SDB --                 *
  * provides advanced spice netlisting capability.        *
  * Documentation at http://www.brorson.com/gEDA/SPICE/   *
  *********************************************************
  *vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
  .model 2N3904   NPN(Stuff
  +               More stuff
  +               Yet more stuff
  +               Final line of stuff)
  *^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
  *
  *==============  Begin SPICE netlist of main design ============
  C1 1 Vbase1 2.2uF  
  C2 2 Vbase2 2.2uF  
  CE1 0 Vem1 1pF  
  CE2 0 Vem2 1pF  
  Cout VColl2 Vout 2.2uF  
  Q1 Vcoll1 Vbase1 Vem1 2N3904 
  Q2 VColl2 Vbase2 Vem2 2N3904 
  R1 Vbase1 Vcc 28K  
  R2 0 Vbase1 2K  
  R3 Vbase2 Vcc 28K  
  R4 0 Vbase2 2.8K  
  R5 Vin 1 10  
  R8 Vcoll1 2 1  
  RC1 Vcoll1 Vcc 3.3K  
  RC2 VColl2 Vcc 1K  
  RE1 0 Vem1 100  
  RE2 0 Vem2 100  
  RL 0 Vout 100K  
  VCC Vcc 0 DC 15V
  Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
  .INCLUDE Simulation.cmd
  .options TEMP=25
  .end
  
  
  


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