gEDA-cvs: pcb.git: branch: master updated (bae5dc1520e812145f6db94e8543315f88bb5e96)

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       via  bae5dc1520e812145f6db94e8543315f88bb5e96 (commit)
      from  c9b915d7f2f49f5ebde0abeb5756b1e11e756edc (commit)

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=========
 Summary
=========

 src/draw.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


=================
 Commit Messages
=================

commit bae5dc1520e812145f6db94e8543315f88bb5e96
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Commit: Peter Clifton <pcjc2@xxxxxxxxx>

    draw.c: Fix order of farside object drawing
    
    Backside silk should be drawn before bakside pads

:100644 100644 9f4a591... 7380beb... M	src/draw.c

=========
 Changes
=========

commit bae5dc1520e812145f6db94e8543315f88bb5e96
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Commit: Peter Clifton <pcjc2@xxxxxxxxx>

    draw.c: Fix order of farside object drawing
    
    Backside silk should be drawn before bakside pads

diff --git a/src/draw.c b/src/draw.c
index 9f4a591..7380beb 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -365,13 +365,13 @@ DrawEverything (BoxTypePtr drawn_area)
       && gui->set_layer ("invisible", SL (INVISIBLE, 0), 0))
     {
       side = SWAP_IDENT ? COMPONENT_LAYER : SOLDER_LAYER;
-      r_search (PCB->Data->pad_tree, drawn_area, NULL, pad_callback, &side);
       if (PCB->ElementOn)
 	{
 	  r_search (PCB->Data->element_tree, drawn_area, NULL, element_callback, &side);
 	  r_search (PCB->Data->name_tree[NAME_INDEX (PCB)], drawn_area, NULL, name_callback, &side);
 	  DrawLayer (&(PCB->Data->Layer[max_copper_layer + side]), drawn_area);
 	}
+      r_search (PCB->Data->pad_tree, drawn_area, NULL, pad_callback, &side);
     }
 
   /* draw all layers in layerstack order */




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