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gEDA-cvs: CVS update: .cvsignore

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  User: ahvezda 
  Date: 06/08/21 22:56:15

  Added:       .        .cvsignore 001geda_documentation.html
                        001geda_faq-attribs.html 001geda_faq-gnetlist.html
                        001geda_faq-gsch2pcb.html 001geda_faq-gschem.html
                        001geda_faq-simulation.html 001geda_faq.html
                        001geda_glossary.html 001geda_gschem_mp.html
                        001geda_gschem_ug.html 001geda_hse_howto.html
                        001geda_installation.html 001geda_kig_howto.html
                        001geda_pcb-quick_reference.html
                        001geda_pcb_tips.html 001geda_scg.html
                        001geda_tasks.html 001geda_todos.html
                        001geda_usage.html Makefile.am
                        docs_20060124_gschem_ug_app_a.html
                        docs_20060124_gschem_ug_app_b.html
                        docs_20060124_gschem_ug_app_c.html
                        docs_20060124_gschem_ug_components_symbols_objects_attributes.html
                        docs_20060124_gschem_ug_electrical_connectivity.html
                        docs_20060124_gschem_ug_how_to_ask_questions.html
                        docs_20060124_gschem_ug_installing_gschem.html
                        docs_20060124_gschem_ug_resources.html
                        docs_20060124_gschem_ug_the_main_window.html
                        docs_20060124_gschem_ug_the_status_window.html
                        geda_bom_readme.html geda_covered_mp.html
                        geda_covered_rv.html geda_csygas.html
                        geda_cygwin.html geda_documentation.html
                        geda_eagle_pcb_netlister_readme.html
                        geda_example_hsm.html geda_example_usbjtag.html
                        geda_faq-attribs.html geda_faq-gnetlist.html
                        geda_faq-gsch2pcb.html geda_faq-gschem.html
                        geda_faq-simulation.html geda_faq.html
                        geda_fbabgapp.html geda_fc1.html geda_fc2.html
                        geda_fc3.html geda_fc4.html
                        geda_file_format_spec.html
                        geda_footprint_creation.html
                        geda_gattrib_readme.html geda_gerbv_mp.html
                        geda_gerbv_pnp_readme.html geda_gfdl.html
                        geda_glossary.html geda_gnetlist_mp.html
                        geda_gnetlist_ug.html geda_grcsan.html
                        geda_grenum_mp.html geda_gsch2pcb_readme.html
                        geda_gschem2pcb_readme.html geda_gschem_mp.html
                        geda_gschem_ug.html geda_gsymcheck_mp.html
                        geda_gtkwave_lxt2miner_mp.html
                        geda_gtkwave_lxt2vcd_mp.html geda_gtkwave_mp.html
                        geda_gtkwave_mvl2lxt_mp.html
                        geda_gtkwave_mvl2vcd_mp.html
                        geda_gtkwave_tex2vcd_mp.html
                        geda_gtkwave_tla2vcd_mp.html
                        geda_gtkwave_vcd2lxt2_mp.html
                        geda_gtkwave_vcd2lxt_mp.html
                        geda_gtkwave_vcd2vzt_mp.html
                        geda_gtkwave_vzt2vcd_mp.html
                        geda_gtkwave_vztminer_mp.html geda_hse_howto.html
                        geda_icarus_anc.html geda_icarus_extensions.html
                        geda_icarus_glossary.html geda_icarus_ieee1364.html
                        geda_icarus_mp.html geda_icarus_opcodes.html
                        geda_icarus_quick_start.html
                        geda_icarus_readme.html geda_icarus_vpi_mp.html
                        geda_icarus_vpi_within_vvp.html
                        geda_icarus_vvp_runtime.html
                        geda_icarus_vvp_simulation.html
                        geda_icarus_xilinx_hints.html geda_icarus_xnf.html
                        geda_igarus_fpga_lcg.html geda_installation.html
                        geda_installed_plugins.html geda_kig_howto.html
                        geda_master_attributes_list.html
                        geda_mcalc_readme.html geda_na_howto.html
                        geda_ngnutmeg_mp.html geda_ngsconvert_mp.html
                        geda_ngspice_mp.html geda_olib_readme.html
                        geda_pcb-quick_reference.html geda_pcb.html
                        geda_pcb_mp.html geda_pcb_tips.html
                        geda_pcb_ug.html geda_scg.html geda_sdb_howto.html
                        geda_sn_readme.html geda_ssan.html
                        geda_style_guide.html geda_suse_10.html
                        geda_suse_9.html geda_syntax_features.html
                        geda_systemc_netlister_readme.html geda_tasks.html
                        geda_todos.html geda_tragesym_readme.html
                        geda_usage.html geda_vams_netlister_readme.html
                        geda_verilog_netlister_readme.html
                        geda_vhdl_netlister_readme.html geda_wcalc_mp.html
                        geda_wcalc_readme.html geda_wcalc_stdio_mp.html
                        index.html start_es.html start_fr.html
  Log:
  First checkin of the wiki snapshot, prep work for new version of gEDA/gaf
  
  
  
  
  Revision  Changes    Path
  1.1                  eda/geda/gaf/docs/wiki/.cvsignore
  
  Index: .cvsignore
  ===================================================================
  Makefile
  Makefile.in
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/001geda_documentation.html
  
  Index: 001geda_documentation.html
  ===================================================================
  <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
   "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd";>
  <html xmlns="http://www.w3.org/1999/xhtml"; xml:lang="en"
   lang="en" dir="ltr">
  <head>
    <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
    <title>geda:documentation.fr</title>
    <meta name="generator" content="DokuWiki Release 2006-03-09" />
    <link rel="start" href="http://geda.seul.org/wiki/"; />
    <link rel="contents" href="http://geda.seul.org/wiki/geda:documentation.fr?do=index"; title="" />
    <link rel="alternate" type="application/rss+xml" title="Recent Changes" href="http://geda.seul.org/wiki/feed.php"; />
    <link rel="alternate" type="application/rss+xml" title="Current Namespace" href="http://geda.seul.org/wiki/feed.php?mode=list&ns=geda"; />
    <link rel="alternate" type="text/html" title="Plain HTML" href="http://geda.seul.org/wiki/geda:documentation.fr?do=export_xhtml"; />
    <link rel="alternate" type="text/plain" title="Wiki Markup" href="http://geda.seul.org/wiki/geda:documentation.fr?do=export_raw"; />
    <meta name="date" content="2006-08-11T17:42:32-0400" />
    <meta name="robots" content="index,follow" />
    <link rel="stylesheet" media="screen" type="text/css" href="lib/exe/css" />
    <link rel="stylesheet" media="print" type="text/css" href="lib/exe/001css" />
  </head>
  <body>
  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#documentation_en_ligne_de_la_suite_d_outils_geda" class="toc">Documentation en ligne de la Suite d'Outils gEDA</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#for_document_authors" class="toc">For document authors</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gschem_-_saisie_de_schemas" class="toc">gschem - Saisie de SchÃ©mas</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gnetlist_-_netlister" class="toc">gnetlist - Netlister</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gsymcheck_-_symbol_checker" class="toc">gsymcheck - Symbol Checker</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#utils_-_geda_utilities" class="toc">utils - gEDA Utilities</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#examples" class="toc">Examples</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#attribute_file_format_details" class="toc">Attribute/File Format Details</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#spice" class="toc">SPICE</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#ngspice" class="toc">ngspice</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gnucap" class="toc">gnucap</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gspiceui" class="toc">gSpiceUI</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#pcb" class="toc">PCB</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gerbv" class="toc">gerbv</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#icarus_verilog" class="toc">Icarus Verilog</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gtkwave" class="toc">GTKWave</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#wcalc" class="toc">Wcalc</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#mcalc" class="toc">mcalc</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#covered" class="toc">covered</a></span></div></li></ul>
  </div>
  </div>
  
  <h1><a name="documentation_en_ligne_de_la_suite_d_outils_geda" id="documentation_en_ligne_de_la_suite_d_outils_geda">Documentation en ligne de la Suite d'Outils gEDA</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-64] -->
  <h2><a name="for_document_authors" id="for_document_authors">For document authors</a></h2>
  <div class="level2">
  
  <p>
  New features are available for document authors:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:syntax_features"; class="wikilink1" title="geda:syntax_features">Syntax features</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:installed_plugins"; class="wikilink1" title="geda:installed_plugins">Installed plugins</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:style_guide"; class="wikilink1" title="geda:style_guide">Style Guide</a> &ndash; A work in progress, please contribute</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [65-273] -->
  <h2><a name="gschem_-_saisie_de_schemas" id="gschem_-_saisie_de_schemas">gschem - Saisie de SchÃ©mas</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="001geda_gschem_ug.html" class="wikilink2" title="geda:gschem_ug.fr">Guide de l'Utilisateur gschem</a> &ndash; En cours, vous pouvez participer</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_gschem_mp.html" class="wikilink2" title="geda:gschem_mp.fr">page de manuel gschem</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_scg.html" class="wikilink2" title="geda:scg.fr">Guide de la CrÃ©ation de Symbole</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_hse_howto.html" class="wikilink2" title="geda:hse_howto.fr">Hooks/Scheme Extension HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_kig_howto.html" class="wikilink2" title="geda:kig_howto.fr">HOWTO du Keymapping dans gschem</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [274-620] -->
  <h2><a name="gnetlist_-_netlister" id="gnetlist_-_netlister">gnetlist - Netlister</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gnetlist_ug"; class="wikilink1" title="geda:gnetlist_ug">gnetlist User's Guide</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gnetlist_mp"; class="wikilink1" title="geda:gnetlist_mp">gnetlist man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:sdb_howto"; class="wikilink1" title="geda:sdb_howto">Spice netlisting (SDB) HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:na_howto"; class="wikilink1" title="geda:na_howto">net= attribute mini-HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:ssan"; class="wikilink1" title="geda:ssan">Switcap Symbols and Netlister</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:sn_readme"; class="wikilink1" title="geda:sn_readme">Switcap netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:fbabgapp"; class="wikilink1" title="geda:fbabgapp">Forward/Backward Annotation Between gEDA and Pads PowerPCB</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:grcsan"; class="wikilink1" title="geda:grcsan">gEDA RF Cascade Symbols and Netlister</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:bom_readme"; class="wikilink1" title="geda:bom_readme">Bill of Material netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gschem2pcb_readme"; class="wikilink1" title="geda:gschem2pcb_readme">gschem2pcb README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:verilog_netlister_readme"; class="wikilink1" title="geda:verilog_netlister_readme">Verilog netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:vhdl_netlister_readme"; class="wikilink1" title="geda:vhdl_netlister_readme">VHDL netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:vams_netlister_readme"; class="wikilink1" title="geda:vams_netlister_readme">VAMS netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:systemc_netlister_readme"; class="wikilink1" title="geda:systemc_netlister_readme">SystemC netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:eagle_pcb_netlister_readme"; class="wikilink1" title="geda:eagle_pcb_netlister_readme">Eagle PCB netlister README</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [621-1493] -->
  <h2><a name="gsymcheck_-_symbol_checker" id="gsymcheck_-_symbol_checker">gsymcheck - Symbol Checker</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gsymcheck_mp"; class="wikilink1" title="geda:gsymcheck_mp">gsymcheck man-page</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1494-1578] -->
  <h2><a name="utils_-_geda_utilities" id="utils_-_geda_utilities">utils - gEDA Utilities</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gsch2pcb_readme"; class="wikilink1" title="geda:gsch2pcb_readme">gsch2pcb (gschem to PCB) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">gsch2pcb tutorial</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:tragesym_readme"; class="wikilink1" title="geda:tragesym_readme">tragesym (symbol generator) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/tragesym/tragesym.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/tragesym/tragesym.html";  rel="nofollow">tragesym Tutorial</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:olib_readme"; class="wikilink1" title="geda:olib_readme">olib (OrCAD (TM) converter) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:grenum_mp"; class="wikilink1" title="geda:grenum_mp">grenum man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gattrib_readme"; class="wikilink1" title="geda:gattrib_readme">gattrib README</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1579-2087] -->
  <h2><a name="examples" id="examples">Examples</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:example_hsm"; class="wikilink1" title="geda:example_hsm">Hierarchical SPICE model</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:example_usbjtag"; class="wikilink1" title="geda:example_usbjtag">Example USB-based JTAG interface</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2088-2237] -->
  <h2><a name="attribute_file_format_details" id="attribute_file_format_details">Attribute/File Format Details</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:master_attributes_list"; class="wikilink1" title="geda:master_attributes_list">Master Attributes List</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:file_format_spec"; class="wikilink1" title="geda:file_format_spec">sym/sch File Format Specification</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2238-2403] -->
  <h1><a name="spice" id="spice">SPICE</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/papers/al-davis-dissertation.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/papers/al-davis-dissertation.pdf";  rel="nofollow">Implicit Mixed-Mode Simulation of VLSI Circuits</a> by Albert Tatum Davis (1991)<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> goes dead.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/SPICE/intro.html"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/intro.html";  rel="nofollow">Circuit Simulation using gEDA and SPICE - HOWTO</a> (<acronym title="HyperText Markup Language">HTML</acronym> version)<br/>
   by Stuart Brorson (20 December 2004).<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> is not the latest version.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/HOWTO/gEDA_Spice_HOWTO-20050103.pdf"; class="urlextern" title="http://www.brorson.com/gEDA/HOWTO/gEDA_Spice_HOWTO-20050103.pdf";  rel="nofollow">Circuit Simulation using gEDA and SPICE - HOWTO</a> (<acronym title="Portable Document Format">PDF</acronym> version)<br/>
   by Stuart Brorson ( 5 January 2005).</div>
  </li>
  </ul>
  
  <p>
   Testing:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:csygas"; class="wikilink1" title="geda:csygas">Circuit Simulation using gEDA and SPICE - HOWTO</a> &ndash; Done converting. Please comment on this conversion to a wiki-format.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2404-3153] -->
  <h1><a name="ngspice" id="ngspice">ngspice</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www-ti.informatik.uni-tuebingen.de/~bernauer/lehre/ti-1-0506/spice/ngspice.pdf"; class="urlextern" title="http://www-ti.informatik.uni-tuebingen.de/~bernauer/lehre/ti-1-0506/spice/ngspice.pdf";  rel="nofollow">NGSPICE User Manual</a> &ndash; describes ngspice-rework-17, Draft Version 0.2<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> is not the appropriated version, or if it goes dead.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:ngspice_mp"; class="wikilink1" title="geda:ngspice_mp">ngspice man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:ngnutmeg_mp"; class="wikilink1" title="geda:ngnutmeg_mp">ngnutmeg man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:ngsconvert_mp"; class="wikilink1" title="geda:ngsconvert_mp">ngsconvert man-page</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3154-3576] -->
  <h1><a name="gnucap" id="gnucap">gnucap</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/gnucap-man.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/gnucap-man.pdf";  rel="nofollow">The Gnu Circuit Analysis Package Users manual</a> &ndash; January 21,2004 version</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/papers/gnucap-model-compiler.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/papers/gnucap-model-compiler.pdf";  rel="nofollow">The Gnucap Model Compiler</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3577-3837] -->
  <h1><a name="gspiceui" id="gspiceui">gSpiceUI</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/shared/gEDA-20060124/Documents/gSpiceUI/gSpiceUI.html"; class="urlextern" title="file:///shared/gEDA-20060124/Documents/gSpiceUI/gSpiceUI.html"  rel="nofollow">GNU Spice GUI</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3838-3945] -->
  <h1><a name="pcb" id="pcb">PCB</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:pcb_ug"; class="wikilink2" title="geda:pcb_ug">Pcb-1.99q</a> &ndash; gEDA Suite version 20060123</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:footprint_creation"; class="wikilink2" title="geda:footprint_creation">footprint_creation</a> &ndash; Stuart Brorson&rsquo;s document, is this the latest?</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:pcb_mp"; class="wikilink1" title="geda:pcb_mp">PCB man-page</a></div>
  </li>
  <li class="level1"><div class="li"></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://pcb.sourceforge.net/manual.html"; class="urlextern" title="http://pcb.sourceforge.net/manual.html";  rel="nofollow">Recent development shapshot manuals and the current CVS version manual</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3946-4262] -->
  <h1><a name="gerbv" id="gerbv">gerbv</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gerbv_mp"; class="wikilink1" title="geda:gerbv_mp">gerbv man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gerbv_pnp_readme"; class="wikilink1" title="geda:gerbv_pnp_readme">Searching for Parts and marking them on screen (in gerbv)</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4263-4408] -->
  <h1><a name="icarus_verilog" id="icarus_verilog">Icarus Verilog</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_quick_start"; class="wikilink1" title="geda:icarus_quick_start">Getting Started with Icarus Verilog</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_mp"; class="wikilink1" title="geda:icarus_mp">Icarus Verilog compiler man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_vpi_mp"; class="wikilink1" title="geda:icarus_vpi_mp">Compile front end for VPI modules man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_vvp_runtime"; class="wikilink1" title="geda:icarus_vvp_runtime">Icarus Verilog vvp runtime engine man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_readme"; class="wikilink1" title="geda:icarus_readme">The Icarus Verilog Compilation System</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:igarus_fpga_lcg"; class="wikilink1" title="geda:igarus_fpga_lcg">FPGA Loadable Code Generator for Icarus Verilog</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_xilinx_hints"; class="wikilink1" title="geda:icarus_xilinx_hints">Xilinx Hints</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_xnf"; class="wikilink1" title="geda:icarus_xnf">Xilinx Netlist Format</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_ieee1364"; class="wikilink1" title="geda:icarus_ieee1364">Icarus Verilog vs. IEEE1364</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_anc"; class="wikilink1" title="geda:icarus_anc">Icarus Attribute Naming Conventions</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_extensions"; class="wikilink1" title="geda:icarus_extensions">Icarus Verilog Extensions</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_glossary"; class="wikilink1" title="geda:icarus_glossary">Icarus Verilog Glossary</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_opcodes"; class="wikilink1" title="geda:icarus_opcodes">Executable Instruction Opcodes</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_vpi_within_vvp"; class="wikilink1" title="geda:icarus_vpi_within_vvp">VPI_within_VVP</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:icarus_vvp_simulation"; class="wikilink1" title="geda:icarus_vvp_simulation">VVP Simulation Engine</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4409-5334] -->
  <h1><a name="gtkwave" id="gtkwave">GTKWave</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://home.nc.rr.com/gtkwave/"; class="urlextern" title="http://home.nc.rr.com/gtkwave/";  rel="nofollow">Welcome to GTKWave</a> &ndash; Now for version 3.0 (the promoted version 1.3)</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_mp"; class="wikilink1" title="geda:gtkwave_mp">Visualization tool for VCD, LXT, and VZT files (gtkwave)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_lxt2miner_mp"; class="wikilink1" title="geda:gtkwave_lxt2miner_mp">Data mining of LXT2 files (lxt2miner)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_lxt2vcd_mp"; class="wikilink1" title="geda:gtkwave_lxt2vcd_mp">Coverts LXT2 files to VCD (lxt2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_mvl2lxt_mp"; class="wikilink1" title="geda:gtkwave_mvl2lxt_mp">Coverts MVLSIM AET files to LXT (mvl2lxt)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_mvl2vcd_mp"; class="wikilink1" title="geda:gtkwave_mvl2vcd_mp">Coverts MVLSIM AET files to VCD (mvl2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_tex2vcd_mp"; class="wikilink1" title="geda:gtkwave_tex2vcd_mp">Coverts TEXSIM AET files to VCD (tex2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_tla2vcd_mp"; class="wikilink1" title="geda:gtkwave_tla2vcd_mp">Converts TLA to VCD or LST files (tla2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_vcd2lxt_mp"; class="wikilink1" title="geda:gtkwave_vcd2lxt_mp">Converts VCD files to interlaced or linear LXT files (vcd2lxt)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_vcd2lxt2_mp"; class="wikilink1" title="geda:gtkwave_vcd2lxt2_mp">Converts VCD files to LXT2 files (vcd2lxt2)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_vcd2vzt_mp"; class="wikilink1" title="geda:gtkwave_vcd2vzt_mp">Converts VCD files to VZT files
   (vcd2vzt)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_vzt2vcd_mp"; class="wikilink1" title="geda:gtkwave_vzt2vcd_mp">Coverts VZT files to VCD (vzt2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:gtkwave_vztminer_mp"; class="wikilink1" title="geda:gtkwave_vztminer_mp">Data mining of VZT files (vztminer)</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5335-6366] -->
  <h1><a name="wcalc" id="wcalc">Wcalc</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:wcalc_readme"; class="wikilink1" title="geda:wcalc_readme">Wcalc README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:wcalc_mp"; class="wikilink1" title="geda:wcalc_mp">Wcalc man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:wcalc_stdio_mp"; class="wikilink1" title="geda:wcalc_stdio_mp">stdio Wcalc man-page</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6367-6513] -->
  <h1><a name="mcalc" id="mcalc">mcalc</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://mcalc.sourceforge.net/"; class="urlextern" title="http://mcalc.sourceforge.net/";  rel="nofollow">Microstrip Analysis/Synthesis Calculator</a> &ndash; latest documentation from sourceforge</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:mcalc_readme"; class="wikilink1" title="geda:mcalc_readme">mcalc README</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6514-6693] -->
  <h1><a name="covered" id="covered">covered</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://covered.sourceforge.net/user/index.html"; class="urlextern" title="http://covered.sourceforge.net/user/index.html";  rel="nofollow">covered User Manual</a> &ndash; link to latest covered documentation on sourceforge</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:covered_rv"; class="wikilink2" title="geda:covered_rv">covered Report Viewer</a> &ndash; available in the Help menu of the <acronym title="Graphical User Interface">GUI</acronym> report utility</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/wiki/geda:covered_mp"; class="wikilink1" title="geda:covered_mp">covered man-page</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6694-] --></div>
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#faq_geda" class="toc">FAQ gEDA</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#qu_est_ce_que_le_projet_geda" class="toc">Qu'est ce que le projet gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_geda_gaf_and_how_does_it_relate_to_geda" class="toc">What is gEDA/gaf and how does it relate to gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_geda_suite" class="toc">What is the gEDA suite?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_what_makes_geda_so_different_from_other_eda_tools" class="toc">Why? What makes gEDA so different from other EDA tools?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application" class="toc">Why does the gEDA Suite seem like a collection of random programs, and not a single integrated application?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application" class="toc">So which is better, a suite (i.e. confederacy) of programs or an integrated application?</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#suite_confederacy_pros" class="toc">Suite (confederacy) pros:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#suite_confederacy_cons" class="toc">Suite (confederacy) cons:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#monolithic_application_pros" class="toc">Monolithic application pros:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#monolithic_application_cons" class="toc">Monolithic application cons:</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_license_does_geda_use" class="toc">What license does gEDA use?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#where_can_i_get_more_information_about_and_download_geda" class="toc">Where can I get more information about and download gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#okay_how_do_i_start_using_geda" class="toc">Okay, how do I start using gEDA?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="faq_geda" id="faq_geda">FAQ gEDA</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-24] -->
  <h2><a name="qu_est_ce_que_le_projet_geda" id="qu_est_ce_que_le_projet_geda">Qu'est ce que le projet gEDA?</a></h2>
  <div class="level2">
  
  <p>
  Le projet gEDA travaille Ã  produire une suite <acronym title="GNU General Public License">GPL</acronym> complÃ¨te d&rsquo;outils EDA (<em class="u">E</em>lectronic <em class="u">D</em>esign <em class="u">A</em>utomation). Ces outils sont utilisÃ©s pour la conception de circuits Ã©lectriques, la saisie de schÃ©mas, la simulation, le prototypage et la production. Le projet gEDA offre actuellement une suite mature dâ??applications de logiciels libres pour la conception Ã©lectronique, incluant le la saisie de schÃ©mas, la gestion dâ??attributs, la gÃ©nÃ©ration de bill of materials (BOM), le netlisting dans plus de 20 formats de netlist, la simulation analogique et numÃ©rique et le placement sur circuit imprimÃ© Â« printed circuit board (PCB) Â».
  </p>
  
  <p>
  The originator of gEDA project is Ales Hvezda. The gEDA project has grown quite a bit, since the Spring of 1998. It is no longer one person producing tools. Instead, there are many people involved. A few people are contributing to the original tools, while others are doing their own development on their own tools. So, gEDA does not refer to the original tools anymore (those tools now stand on their own now), but instead it refers to all the projects which are free and are somehow associated with this webpage or the geda-dev/geda-user mailing lists. By associating with gEDA, free software authors do not give up any control over their tools, but they gain a community which cares about quality and free (as in freedom) EDA tools.
  </p>
  
  <p>
  gEDA can be pronounced â??gee-daahhhâ?? (rhymes with cheetah) or â??g-dahhh (short g).
  </p>
  
  </div>
  <!-- SECTION [25-1540] -->
  <h2><a name="what_is_geda_gaf_and_how_does_it_relate_to_geda" id="what_is_geda_gaf_and_how_does_it_relate_to_geda">What is gEDA/gaf and how does it relate to gEDA?</a></h2>
  <div class="level2">
  
  <p>
  gaf stands for â??<em class="u">g</em>schem <em class="u">a</em>nd <em class="u">f</em>riendsâ??. It is a subset of the entire tool suite grouped together under the gEDA name. gEDA/gaf is a collection of tools which currently includes:
  </p>
  <ul>
  <li class="level1"><div class="li"> gschem: A schematic capture program</div>
  </li>
  <li class="level1"><div class="li"> gnetlist: A netlist generation program</div>
  </li>
  <li class="level1"><div class="li"> gsymcheck: A syntax checker for schematic symbols</div>
  </li>
  <li class="level1"><div class="li"> gattrib: A spreadsheet programm that manipulates the properties of symbols of a schematic</div>
  </li>
  <li class="level1"><div class="li"> libgeda: Libraries for gschem gnetlist and gsymcheck</div>
  </li>
  <li class="level1"><div class="li"> gsch2pcb: Forward annotation from your schematic to layout using <a href="http://geda.seul.org/wiki/geda:pcb"; class="wikilink2" title="geda:pcb">PCB</a>.</div>
  </li>
  <li class="level1"><div class="li"> some minor utils</div>
  </li>
  </ul>
  
  <p>
   The gEDA/gaf tools share a common file format (.sch) and also share a common link library (libgeda.so). The gEDA/gaf source distribution can be found on this website (geda.seul.org).
  </p>
  
  <p>
  Even though gaf is very much a part of gEDA, the gEDA name does not necessarily only apply to gaf â?? tools gathered under the â??gEDAâ?? moniker include many other programs. Indeed, gEDA refers to <strong>any</strong> <acronym title="GNU General Public License">GPL</acronym>&lsquo;d EDA tool which decides to associate itself with the gEDA website/mailing list. Important examples of gEDA tools include the layout program <a href="http://geda.seul.org/wiki/geda:pcb"; class="wikilink2" title="geda:pcb">PCB</a>, the Verilog complier <a href="http://www.icarus.com/eda/verilog/"; class="urlextern" title="http://www.icarus.com/eda/verilog/";  rel="nofollow">Icarus Verilog</a>, the analog circuit simulator <a href="http://www.gnucap.org/"; class="urlextern" title="http://www.gnucap.org/";  rel="nofollow">gnucap</a>, and the open-source SPICE simulator <a href="http://www.ngspice.org/"; class="urlextern" title="http://www.ngspice.org/";  rel="nofollow">ngspice</a>. Many other gEDA programs also exist.
  </p>
  
  <p>
  For historical reasons, on <a href="http://freshmeat.net/"; class="urlextern" title="http://freshmeat.net/";  rel="nofollow">freshmeat</a> gaf is known as the package â??gEDAâ??.
  </p>
  
  </div>
  <!-- SECTION [1541-3089] -->
  <h2><a name="what_is_the_geda_suite" id="what_is_the_geda_suite">What is the gEDA suite?</a></h2>
  <div class="level2">
  
  <p>
  The gEDA suite is a CDROM image (.iso) created by Stuart Brorson to make it easier to install all the various tools that are part of, associated with, or just plain work with the gEDA projectâ??s software. The vision is that the tools collected on the gEDA suite CDROM constitute a coherent, complete, open-source design environment gathered into one convenient download. Currently the gEDA suite CDROM includes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/"; class="urlextern" title="http://geda.seul.org/tools/";  rel="nofollow">gEDA/gaf</a> â?? schematic capture and netlisting</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/ngspice"; class="urlextern" title="http://geda.seul.org/tools/ngspice";  rel="nofollow">ngspice</a> â?? SPICE simulation</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gnucap"; class="urlextern" title="http://geda.seul.org/tools/gnucap";  rel="nofollow">gnucap</a> â?? Analog simulation</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gspiceui"; class="urlextern" title="http://geda.seul.org/tools/gspiceui";  rel="nofollow">gspiceui</a> â?? <acronym title="Graphical User Interface">GUI</acronym> front end for ngspice/gnucap</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/pcb"; class="urlextern" title="http://geda.seul.org/tools/pcb";  rel="nofollow">pcb</a> â?? PCB layout</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gerbv"; class="urlextern" title="http://geda.seul.org/tools/gerbv";  rel="nofollow">gerbv</a> â?? Gerber viewer</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/icarus"; class="urlextern" title="http://geda.seul.org/tools/icarus";  rel="nofollow">Icarus Verilog</a> â?? Verilog simulator</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gtkwave"; class="urlextern" title="http://geda.seul.org/tools/gtkwave";  rel="nofollow">GTKWave</a> â?? Digitial waveform viewer</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://wcalc.sourceforge.net/"; class="urlextern" title="http://wcalc.sourceforge.net/";  rel="nofollow">wcalc</a> â?? Transmission line and electromagnetic structure analysis</div>
  </li>
  </ul>
  
  <p>
   At the center of the gEDA suite CDROM is an easy to use installer that automates the building and installing of all the various packages from source â?? making it easy to install the whole suite for the first time user. The gEDA suite CDROM image is available from the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">download</a> page. <strong>Note: The installer works only with Linux!</strong>
  </p>
  
  </div>
  <!-- SECTION [3090-4612] -->
  <h2><a name="why_what_makes_geda_so_different_from_other_eda_tools" id="why_what_makes_geda_so_different_from_other_eda_tools">Why? What makes gEDA so different from other EDA tools?</a></h2>
  <div class="level2">
  
  <p>
  Tools in the gEDA suite and associated tools have the following characteristics:
  </p>
  <ul>
  <li class="level1"><div class="li"> Free in the monetary sense (no cost).</div>
  </li>
  <li class="level1"><div class="li"> All the file formats and all the source codes are available via the <acronym title="GNU General Public License">GPL</acronym> license. This license grants specific rights to the authors and users of <acronym title="GNU General Public License">GPL</acronym>&lsquo;d software.</div>
  </li>
  <li class="level1"><div class="li"> Independence from any one vendor. All gEDA tools come with full source. You can change, improve, port, and even distribute (if you follow the terms of the <acronym title="GNU General Public License">GPL</acronym>) the tools.</div>
  </li>
  <li class="level1"><div class="li"> No mechanism is used to restrict the use of the tools (like making use of hard disk serial numbers or ethernet addresses to force the software to only run on one machine).</div>
  </li>
  <li class="level1"><div class="li"> No arbitrary, marketeering-driven limitations. Free versions of commercial tools usually include capricious limitations (i.e. limited design size, inability to print, inability to export netlists, etc.) which cripple the program, and force the serious user to buy the real tool. In contrast, the gEDA tools are fully-featured, and do not arbitrarily impose limits on design as a way of extracting money from you.</div>
  </li>
  <li class="level1"><div class="li"> Legacy design protection. Since the software will always run forever (because of above), gEDA tool design files will always be viewable/editable (with the right versions of the software).</div>
  </li>
  <li class="level1"><div class="li"> Open design flow. This means that the tools talk to each other via known and documented means (files / APIs). It is easy to replace a tool or augment the tools with something else if you so desire.</div>
  </li>
  <li class="level1"><div class="li"> Stability - Bugs which cause crashes are investigated immediately and fixed as soon as possible.</div>
  </li>
  <li class="level1"><div class="li"> Minimize bloat and unnecessary features.</div>
  </li>
  <li class="level1"><div class="li"> Run on as many platforms as possible. For gEDA/gaf: GNU/Linux, various other Unix systems.</div>
  </li>
  <li class="level1"><div class="li"> Developed in an open (no secrets) fashion.</div>
  </li>
  <li class="level1"><div class="li"> Strive to be documented.</div>
  </li>
  </ul>
  
  <p>
   gEDA may not have all the latest cutting edge features found in other packages and may be viewed sometimes as being on the trailing edge of EDA technology, but the tools are becoming useful to a lot of people because the above mentioned reasons.
  </p>
  
  </div>
  <!-- SECTION [4613-6695] -->
  <h2><a name="why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application" id="why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application">Why does the gEDA Suite seem like a collection of random programs, and not a single integrated application?</a></h2>
  <div class="level2">
  
  <p>
  The gEDA suite is indeed a confederacy of somewhat independent programs. This happened for reasons of history: Ales Hvezda started the gEDA project more or less on his own. The original vision was to produce an end-to-end software suite for creating PC boards so that robotics hobbiests could design their own boards. However, as the gEDA project progressed the large magnitude of this task became clear â?? and coding many of the proposed apps had not even begun!
  </p>
  
  <p>
  Meanwhile, other software developers â?? with their own independently written applications â?? found the gEDA project vision compelling. The authors of those applications joined Ales and contributed their programs to the gEDA project. Amongst the contributed projects was â??pcbâ??, a ten year old (at that time) PCB layout program. With the contribution of â??pcbâ??, gEDAâ??s originally planned layout tool â??gpcbâ?? was scuttled. At the same time, other developers contributed analog and digital simulators, waveform viewers, and so on.
  </p>
  
  <p>
  In this way the gEDA suite came together. It is not shared code, or a common user interface which distinguishes the gEDA suite. Rather, the shared vision of an open-source EDA environment is the thread which holds the project together. Today, the gEDA Suite is a collection of many different programs contributed by many different authors. The apps strive to work together, and usually succeed. But the separate beginnings of each program in the suite are still observable. Nonetheless, with a little work the various components of the suite are interoperable, and many people have completed quite complex board designs using the gEDA suite.
  </p>
  
  </div>
  <!-- SECTION [6696-8466] -->
  <h2><a name="so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application" id="so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application">So which is better, a suite (i.e. confederacy) of programs or an integrated application?</a></h2>
  <div class="level2">
  
  <p>
  This is ultimately a matter of religion. Iâ??ll summarize some of the pros and cons (as I see them) of each approach here. 
  </p>
  
  </div>
  <!-- SECTION [8467-8690] -->
  <h3><a name="suite_confederacy_pros" id="suite_confederacy_pros">Suite (confederacy) pros:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> You can use â??best of breedâ?? applications for each part of the design flow. That is, you can use the standard gEDA flow gschem â?? gsch2pcb â?? pcb to create a PC Board. However, if you think that the open-source application â??pcbâ?? stinks, you can use the flow gschem â?? gnetlist â?? Protel (for example). Recall that gnetlist can output more than twenty different netlist formats! Moreover, if you donâ??t like one component of the flow, you can write another tool to replace it. Now at this time it is true that only a single application generally exists to perform a particular task. However, this situation will likely change with time â?? witness the forking of the â??pcbâ?? project, the contributed netlister <a href="http://www.viasic.com/opensource/"; class="urlextern" title="http://www.viasic.com/opensource/";  rel="nofollow">gnetman</a>, as well as the <a href="http://web.comhem.se/~u31829222/"; class="urlextern" title="http://web.comhem.se/~u31829222/";  rel="nofollow">HEC</a> project. As a general rule, the suite approach offers the greatest freedom to the user.</div>
  </li>
  <li class="level1"><div class="li"> The design flow has a lot of natural breakpoints. These occur where one design tool completes its job and writes out a file (i.e. gschem writes out a .sch file, or gnetlist writes out a SPICE netlist). At this point, you can easily break into the flow and write scripts which process and/or munge the design data. For big, advanced designs, this is a real advantage to the â??design suiteâ?? approach. This advantage may appeal only to the â??power userâ??, but note itâ??s importance: professional-grade EDA suites (Synopsys, Xilinx) also work the same way.</div>
  </li>
  <li class="level1"><div class="li"> Usage of an applications suite can be automated using a Makefile, or even a <acronym title="Practical Extraction and Report Language">Perl</acronym> script. ASIC designers do this all the time with their design and synthesis tools. Some gEDA users have publically disclosed (on the e-mail list) that they do this too, and point to it as an important feature of the gEDA suite.</div>
  </li>
  <li class="level1"><div class="li"> Scalability: A monolithic application is almost always developed by a lone developer who has a single-minded vision for his program. This developer can enforce stylistic and UI standards throughout all his tools. The problem with this is that a single developer â?? even one who is uniquely gifted â?? can only write one (or a couple of) parts of an EDA application. Therefore, any open-source, monolithic EDA app will likely always be limited in scope &amp; features by the abilities of a single developer. (I would love to be proven wrong on this point. I welcome counter-examples, but none have come to my attention as of this writing.) On the other hand, a confederacy of developers working independently on their own apps â?? but meanwhile contributing to a greater whole â?? can create a very large and capable EDA enviornment indeed.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [8691-11362] -->
  <h3><a name="suite_confederacy_cons" id="suite_confederacy_cons">Suite (confederacy) cons:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> More confusing to newbies, since they donâ??t know the flow right off the bat. That is, they actually need to <acronym title="Read The Fine Manual">RTFM</acronym> to know what tool to run next. Good documentation helps (thatâ??s why youâ??re reading this), but documentation is always second choice behind developing an intuitive application interface.</div>
  </li>
  <li class="level1"><div class="li"> Different programs have different UI conventions (i.e. menu organization is different, keyboard or mouse bindings are different). This can be uncomfortable to those who arenâ??t familiar with the programs.</div>
  </li>
  <li class="level1"><div class="li"> Since no assumptions are made about the design flow, schematic symbols are necessarily <a href="http://geda.seul.org/wiki/geda:faq-gschem#what_s_this_business_about_heavy_vs._light_symbols"; class="wikilink1" title="geda:faq-gschem">light</a>. This forces the user to spend more time attaching e.g. footprint attributes to his design. Moreover, the user must spend more time actually researching which footprints to use. However, a good suite (like the gEDA suite) will offer multiple methods to perform this task (e.g. gattrib, <acronym title="Practical Extraction and Report Language">Perl</acronym> scripts to populate footprints, etc.).</div>
  </li>
  <li class="level1"><div class="li"> Some developers are more energetic than others, or have more free time. Therefore, some programs in a suite will be more developed (and less buggy) than others. Unfortunately, a single buggy program in a suite can unfairly taint a new userâ??s perception of the entire suite.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [11363-12696] -->
  <h3><a name="monolithic_application_pros" id="monolithic_application_pros">Monolithic application pros:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> A single, unified design environment is easier for newbies to grasp. UI conventions may be harmonized. The tool might be intuitive enough that it can be driven without needing to <acronym title="Read The Fine Manual">RTFM</acronym>.</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture symbols can be heavy, so less work is required in attaching attributes to each symbol in a schematic.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [12697-13049] -->
  <h3><a name="monolithic_application_cons" id="monolithic_application_cons">Monolithic application cons:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Not infinitely scalable. One developer canâ??t do everything, no matter how smart. Therefore, a monolithic app will never approach the size or power of a suite developed by a confederacy of programmers.</div>
  </li>
  <li class="level1"><div class="li"> Lack of choice. If the developer doesnâ??t like your way of doing things, you have no choice. Even if you submit patches to enable your way of performing a task, there is a chance the main developer will ignore or reject your patches. This is probably not an issue for newbies, but for â??power usersâ?? it represents a problem.</div>
  </li>
  <li class="level1"><div class="li"> Risk. If the apps developer quits, the code becomes abandoned, and the users suffer. This effectively happened to the program <a href="http://sourceforge.net/projects/xtrkcad"; class="urlextern" title="http://sourceforge.net/projects/xtrkcad";  rel="nofollow">XTrkCAD</a>, a CAD program for designing model railroads. The author of this program quit developing it, but thankfully placed his stuff on Sourceforge so that the program wouldnâ??t simply disappear. Unfortunately, without the original developerâ??s involvement, the code languished. Patches contributed to the project went to /dev/null. Eventually, a coalition of concerned user/developers created a <a href="http://xtrkcad-fork.sourceforge.net/"; class="urlextern" title="http://xtrkcad-fork.sourceforge.net/";  rel="nofollow">fork</a> of the code to enable further development. However, work on the forked code has been piecemeal and sporadic. (Hopefully, this will change someday.) Meanwhile, for the ordinary user, the fact that the original developer quit represents a catastrophe.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [13050-14497] -->
  <h2><a name="what_license_does_geda_use" id="what_license_does_geda_use">What license does gEDA use?</a></h2>
  <div class="level2">
  
  <p>
  All of the tools and associated files in gEDA will be released under the GNU General Public License version 2 (<acronym title="GNU General Public License">GPL</acronym>), from Free Software Foundation
  </p>
  
  <p>
  From the license:
  </p>
  
  <p>
  When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.
  </p>
  
  <p>
  This cannot be stressed enough: <strong>gEDA is GPLed software</strong>. Therefore nothing proprietary can be distributed with gEDA like part libraries from proprietary EDA products. Conversion program for proprietary libraries will be available, but any converted files which are part of a proprietary product must never find their way into gEDA. Contributed files must be GPLable (or be placed under another free license). Please keep this in mind if you wish to contribute something.
  </p>
  
  <p>
  Even though the focus of gEDA is GPLed software, other software licenses are more than welcome to be mixed with the existing software, just as long as they are compatible with the <acronym title="GNU General Public License">GPL</acronym>.
  </p>
  
  </div>
  <!-- SECTION [14498-15776] -->
  <h2><a name="where_can_i_get_more_information_about_and_download_geda" id="where_can_i_get_more_information_about_and_download_geda">Where can I get more information about and download gEDA?</a></h2>
  <div class="level2">
  
  <p>
  The official website is <a href="http://geda.seul.org/"; class="urlextern" title="http://geda.seul.org/";  rel="nofollow">gEDA Project</a> hosted by the <a href="http://www.seul.org/"; class="urlextern" title="http://www.seul.org/";  rel="nofollow">SEUL Project</a>. The European mirror is at <a href="http://ftp.sunet.se/geda/"; class="urlextern" title="http://ftp.sunet.se/geda/";  rel="nofollow">European gEDA Project mirror</a> hosted by Swedish University Network - Sweden, Nothern Europe.
  </p>
  
  <p>
  There are several mailing lists. Please look at the mailing listâ??s <a href="http://geda.seul.org/mailinglist"; class="urlextern" title="http://geda.seul.org/mailinglist";  rel="nofollow">info page</a> for how to subscribe and post.
  </p>
  
  <p>
  You can download all the software, including the gEDA suite CDROM from the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">download</a> page.
  </p>
  
  <p>
  You can find the latest set of documentation on the toplevel <a href="http://geda.seul.org/docs/"; class="urlextern" title="http://geda.seul.org/docs/";  rel="nofollow">documentation</a> page.
  </p>
  
  <p>
  Come to the Free EDA Users Group (Freedog) meeeting in Cambridge, MA. The meeting is at 7PM on the first Wednesday of each month at the <a href="http://www.starbucks.com/retail/locator/MapResults.aspx?a=1&StoreKey=93728&IC_O=42.3599350625432%3a-71.1021394862385%3a32%3a02139+(postal+code)%2c+Massachusetts%2c+United+States&GAD1_O=&GAD2_O=&GAD3_O=02139+(postal+code)%2c+Massachusetts%2c+United+States&GAD4_O=&radius=5&countryID=244&dataSource=MapPoint.NA" class="urlextern" title="http://www.starbucks.com/retail/locator/MapResults.aspx?a=1&amp;StoreKey=93728&amp;IC_O=42.3599350625432%3a-71.1021394862385%3a32%3a02139+(postal+code)%2c+Massachusetts%2c+United+States&amp;GAD1_O=&amp;GAD2_O=&amp;GAD3_O=02139+(postal+code)%2c+Massachusetts%2c+United+States&amp;GAD4_O=&amp;radius=5&amp;countryID=244&amp;dataSource=MapPoint.NA"  rel="nofollow">Kendal Square Starbucks</a>.
  </p>
  
  </div>
  <!-- SECTION [15777-16977] -->
  <h2><a name="okay_how_do_i_start_using_geda" id="okay_how_do_i_start_using_geda">Okay, how do I start using gEDA?</a></h2>
  <div class="level2">
  
  <p>
  The most important thing to do is to read and understand Bill Wilsonâ??s excellent <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">gschem -&gt; gsch2pcb -&gt; PCB</a> tutorial. This should get you started.
  </p>
  
  <p>
  Also be sure to check out the other <a href="http://geda.seul.org/docs"; class="urlextern" title="http://geda.seul.org/docs";  rel="nofollow">gEDA documentation</a>. An installation guide is contained in this Wiki, as is some general information about how to use the tools. Spend some time browsing, download the gEDA Suite, and try it out for yourself! 
  </p>
  
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  1.1                  eda/geda/gaf/docs/wiki/001geda_usage.html
  
  Index: 001geda_usage.html
  ===================================================================
  <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
   "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd";>
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   lang="en" dir="ltr">
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  1.1                  eda/geda/gaf/docs/wiki/Makefile.am
  
  Index: Makefile.am
  ===================================================================
  ## $Id: Makefile.am,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
  ##
  
  docname=wiki
  docsdir = @GEDADOCDIR@/$(docname)
  
  EXTRA_DIST = @datawiki@
  
  install-data-hook: 
  	( $(INSTALL) -d $(DESTDIR)$(docsdir); \
            for i in $(EXTRA_DIST); do \
                  base=`dirname $$i`; \
  		if [ "$$base" != "." ]; then \
  			$(INSTALL) -d $(DESTDIR)$(docsdir)/$$base; \
  		fi; \
                  type=`file $$i | grep -i directory`; \
  		if [ "$$type" = "" ]; then \
  			$(INSTALL_DATA) $$i $(DESTDIR)$(docsdir)/$$i; \
  		fi; \
  	  done )
  
  uninstall-hook:
  	( for i in $(EXTRA_DIST); do \
  		rm -f $(DESTDIR)$(docsdir)/$$i; \
  	  done; )
  	  -rmdir $(DESTDIR)$(docsdir) 
  
  clean-local:
  	rm -f *~ 
  
  maintainer-clean-local:
  	rm -f *~ 
  
  dist-clean-local:
  	rm -f *~ 
  
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_app_a.html
  
  Index: docs_20060124_gschem_ug_app_a.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_app_b.html
  
  Index: docs_20060124_gschem_ug_app_b.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_app_c.html
  
  Index: docs_20060124_gschem_ug_app_c.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_components_symbols_objects_attributes.html
  
  Index: docs_20060124_gschem_ug_components_symbols_objects_attributes.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_electrical_connectivity.html
  
  Index: docs_20060124_gschem_ug_electrical_connectivity.html
  ===================================================================
  <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_how_to_ask_questions.html
  
  Index: docs_20060124_gschem_ug_how_to_ask_questions.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_installing_gschem.html
  
  Index: docs_20060124_gschem_ug_installing_gschem.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_resources.html
  
  Index: docs_20060124_gschem_ug_resources.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_the_main_window.html
  
  Index: docs_20060124_gschem_ug_the_main_window.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/docs_20060124_gschem_ug_the_status_window.html
  
  Index: docs_20060124_gschem_ug_the_status_window.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/geda_bom_readme.html
  
  Index: geda_bom_readme.html
  ===================================================================
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  <h1><a name="bill_of_material_netlister_readme" id="bill_of_material_netlister_readme">Bill of Material netlister README</a></h1>
  <div class="level1">
  <pre class="code">README for
  BOM - Bill Of Materials generater for gnetlist.
  
  --------------------------------------------------------------------------
  
  I (Matt) put together a quick bill of materials generator for gnetlist.
  It takes a configuration file which tells it what attributes you want
  netlisted (i.e. vendor, part number).
  
  This is a sample config file:
  
  device
  label
  name  
  
  Just call it with 
          gnetlist  -g bom -o test.bom test.sch 
  
  The config file must be called &quot;attribs&quot; and be in the pwd, because
  there is no way to pass arguments to the netlister (at least that I
  could find).
  
  Eventually I'd like to integrate this with some sort of a database for
  production purposes.  Let me know if you are interested in helping or
  have any ideas.
  
  Matt
  matt@xxxxxxxxx
  
  </pre>
  
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  <h1><a name="covered_man-page" id="covered_man-page">covered man-page</a></h1>
  <div class="level1">
  <pre class="code">Covered(1)			 Code Analysis			    Covered(1)
  
  
  
  NAME
         Covered - Verilog Code Coverage Analyzer
  
  SYNTAX
         covered [&lt;options&gt;] score [&lt;options&gt;]
         covered	   [&lt;options&gt;]	   merge    [&lt;options&gt;]	   &lt;existing_database&gt;
         &lt;database_to_merge&gt;
         covered [&lt;options&gt;] report [&lt;options&gt;] &lt;database_file&gt;
  
  DESCRIPTION
         Covered is a Verilog code coverage analysis tool that can be useful for
         determining  how	 well  a  diagnostic test suite is covering the design
         under test. Covered reads in the Verilog design files and a VCD or  LXT
         formatted  dumpfile from a diagnostic run and generates a database file
         called a Coverage Description Database (CDD) file, using the score com-
         mand.   This  file  can	be  merged  with other CDD files from the same
         design to create accummulated coverage, using the merge command.	  Once
         a  CDD  file  is	 created, the user can use Covered to generate various
         human-readable coverage reports in an ASCII format or use CoveredÃ¢â?¬â?¢s GUI
         to  interactively  look	at coverage results, using the report command.
         Additionally, as part of CoveredÃ¢â?¬â?¢s score command, race condition possi-
         bilities	 are  found  in	 the  design  files and can be either ignored,
         flagged as warnings or flagged as errors.  By  specifying  race	condi-
         tions  as errors, Covered can also be used as a race condition checker.
  
  GLOBAL OPTIONS
         These options are placed immediately after the keyword covered  in  the
         command-line.   They can be used for any command (with the exception of
         -v and -h) and have the same effect in each case.
  
         -D     Debug.  Display information helpful for debugging tool problems.
  	      Note:   This  option is now only available when covered is built
  	      with the --enable-debug configuration option.
  
         -h     Help.  Display this usage information.
  
         -Q     Quiet mode.  Causes all output to be suppressed.
  
         -v     Version.	Display current Covered version.
  
  COMMANDS
         score  Parses Verilog files and VCD/LXT dumpfiles  to  create  database
  	      file used for merging and reporting.
  
         merge  Merges two database files into one.
  
         report Generates	 human-readable coverage reports from database file or
  	      starts the coverage report GUI.
  
  SCORE COMMAND
         The following options are valid for the score command:
  
         -D define_name
  	      Defines the specified name to 1.
  
         -D define_name=value
  	      Defines the specified name to the specified value.
  
         -e block_name
  	      Name of module, task, function or named begin/end block  to  not
  	      score.   Causes  all  subblocks  in  the Verilog tree under this
  	      block to also not be scored.
  
         -ea    Excludes all always blocks from being considered for coverage.
  
         -ec    Excludes all continuous assignments from	being  considered  for
  	      coverage.
  
         -ei    Excludes	all initial blocks from being considered for coverage.
  
         -F module_name=(in_expr,)out_expr
  	      Indicates to the parser where to find the FSM located in	module
  	      module_name  which  has an input state expression called in_expr
  	      and output state expression called out_expr.  If in_expr is  not
  	      specified,  out_expr  is used as both the input and output state
  	      expression.
  
         -f filename
  	      Name of file containing additional arguments to parse.
  
         -h     Displays this help information.
  
         -I directory
  	      Directory to find included Verilog files.
  
         -i instance_name
  	      Verilog hierarchical reference to the module that is at the  top
  	      of the tree to be scored.	 This option is necessary if module to
  	      verify coverage is not the top-level module in the  design.   If
  	      not specified, -t value is used.
  
         -lxt filename
  	      Name  of LXT/LXT2 dumpfile to score design with.	If this or the
  	      -vcd option is not used, Covered will only create an initial CDD
  	      file from the design and will not attempt to score the design.
  
         -o database
  	      Name of database to write coverage information to.  If not spec-
  	      ified, the output database filename will be &quot;cov.cdd&quot;.
  
         -p filename
  	      Overrides default filename used to store intermediate preproces-
  	      sor output.
  
         -P parameter_scope=value
  	      Performs a defparam on the specified parameter with value.
  
         -r(S|W|E)
  	      Specifies	 action	 to  take  when	 race condition checking finds
  	      problems in design (-rS = Silent, -rW = Warning, -rE = Error).
  
         -S     Outputs simulation statistics after  simulation  has  completed.
  	      This  information is currently only useful for the developers of
  	      Covered.
  
         -t top-level module
  	      Specifies the module name of the top-most module	that  will  be
  	      measured.	  Note	that  this  module  does  not  need  to be the
  	      top-most module in the simulator.	 This field  is	 required  for
  	      all calls to the score command.
  
         -ts number
  	      When  scoring occurs, this option allows the user to see how far
  	      the simulator has progressed by outputting the current  timestep
  	      to  standard  output.  The  value	 of  number specifies how many
  	      timesteps are allowed to be simulated before outputting the cur-
  	      rent timestep (results in less calls to output stream).
  
         -T min|typ|max
  	      Specifies	 which	value to use when encountering a delay expres-
  	      sion in the form:	 min:typ:max.  If this option  is  not	speci-
  	      fied, Ã¢â?¬â?¢typÃ¢â?¬â?¢ select is used by default.
  
         -v filename
  	      Name of specific Verilog file to score.
  
         -vcd filename
  	      Name  of VCD dumpfile to score design with.  If this or the -lxt
  	      option is not used, Covered will only create an initial CDD file
  	      from the design and will not attempt to score the design.
  
         -y directory
  	      Directory to find unspecified Verilog files.
  
         +libext+.extension(+.extension)*+
  	      Extensions of Verilog files to allow in scoring.
  
  MERGE COMMAND
         The following options are valid for the merge command:
  
         -h     Displays this help information.
  
         -o filename
  	      File  to output new database to.	If this argument is not speci-
  	      fied, the existing_database is used as the output database name.
  
  REPORT COMMAND
         The following options are valid with the report command:
  
         -c     If  -v  is specified, displays covered line, toggle and combina-
  	      tional cases.  Default is to display uncovered information.
  
         -d (s|d|v)
  	      Level of detail to provide in coverage report information	 (s  =
  	      summary, d = detailed, v = verbose).  Default is summary.
  
         -h     Displays this help information.
  
         -i     Provides coverage information for instances instead of module.
  
         -m [l][t][c][f][r]
  	      Type(s) of metrics to report.  Default is ltcf.
  
         -o filename
  	      File  to output report information to.  Default is standard out-
  	      put.
  
         -v     Deprecated.  Replaced by Ã¢â?¬â?¢-d dÃ¢â?¬â?¢ or Ã¢â?¬â?¢-d vÃ¢â?¬â?¢.
  
         -view  Starts the GUI interface for interactive coverage reporting.
  
         -w (number)
  	      Specifies the maximum line width (in  characters)	 that  can  be
  	      used to output Verilog information.  If this option is not spec-
  	      ified, all Verilog code in the report will retain the same  for-
  	      matting  as was specified in the original Verilog code.  If this
  	      option is specified, Verilog code will be formatted  to  use  as
  	      much  of	the  current  line as possible, wrapping text when the
  	      line reaches the maximum line width.  The default	 maximum  line
  	      width  is	 115  characters  (this	 value is used if no number is
  	      specified with the -w option).  If a number  is  specified  with
  	      the -w option, this value is used for the maximum line width.
  
  AUTHORS
         Trevor Williams &lt;trevorw@xxxxxxxxxxx&gt;
  
         Arpan Sen &lt;arpan_sen@xxxxxxxxx&gt;
  
  SEE ALSO
         For  more  information  on  how	to use the Covered code coverage tool,
         please consult  the  on-line  UserÃ¢â?¬â?¢s  Guide  at	http://covered.source-
         forge.net/user/index.html.
  
  
  
  Trevor Williams		       covered-20060218			    Covered(1)</pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_covered_rv.html
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_csygas.html
  
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#circuit_simulation_using_geda_and_spice_-_howto" class="toc">Circuit Simulation using gEDA and SPICE - HOWTO</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#target_audience_for_this_howto" class="toc">Target audience for this HOWTO</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#acknowledgements" class="toc">Acknowledgements</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#the_big_picturethe_design_flow_in_geda" class="toc">The big picture: the design flow in gEDA</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#overview_of_spice_usage_with_geda" class="toc">Overview of SPICE usage with gEDA</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#detailed_design_simulation_flow_summary" class="toc">Detailed design/simulation flow summary</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#preliminary_workpreparing_your_symbols_and_spice_files" class="toc">Preliminary work: preparing your symbols and SPICE files</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#configuring_your_symbols" class="toc">Configuring your symbols</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#configuring_your_spice_files" class="toc">Configuring your SPICE files</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#creating_your_circuitschematic_capture" class="toc">Creating your circuit: schematic capture</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#gschem_attributes_for_spice_netlisting" class="toc">Gschem attributes for spice netlisting</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#component_attributes_and_meanings" class="toc">Component attributes and meanings</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#refdes_conventions" class="toc">refdes conventions</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#passives" class="toc">Passives</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#passives_with_additional_attributes" class="toc">Passives with additional attributes</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#passives_for_semiconductor_design" class="toc">Passives for semiconductor design</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#transistors_and_diodes" class="toc">Transistors and diodes</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#actives_--_integrated_circuits" class="toc">Actives -- integrated circuits</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#independent_sources" class="toc">Independent sources</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#dependent_sources" class="toc">Dependent sources</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#spice_components" class="toc">SPICE components</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#handling_hierarchical_models" class="toc">Handling hierarchical models</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#spice_netlist_generation" class="toc">SPICE netlist generation</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#using_gnetlist" class="toc">Using gnetlist</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#creating_the_netlist_using_gnetlist_and_spice-sdb" class="toc">Creating the netlist using gnetlist and spice-sdb</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#common_netlisting_problems" class="toc">Common netlisting problems</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#spice_simulation" class="toc">SPICE simulation</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#ltspice" class="toc">LTSpice</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#ngspice" class="toc">Ngspice</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#tclspice" class="toc">Tclspice</a></span></div></li>
  </ul>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_a" class="toc">Appendix A</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_b" class="toc">Appendix B</a></span></div></li></ul>
  </div>
  </div>
  
  <h1><a name="circuit_simulation_using_geda_and_spice_-_howto" id="circuit_simulation_using_geda_and_spice_-_howto">Circuit Simulation using gEDA and SPICE - HOWTO</a></h1>
  <div class="level1">
  
  <p>
  Stuart Brorson<br/>
   Electroniscript, inc.<br/>
   sdb@xxxxxxxxxxxxxxxxxxx<br/>
   <br/>
   5th January 2006
  </p>
  
  <p>
  <strong>abstract</strong><br/>
   Linux will become an increasingly popular engineering platform in the future. Professional-quality CAD applications for circuit design are becoming available  from programmers within the free-software community.  For electronics, the gEDA suite is the preferred tool set for circuit design.  Analog circuit simulation using SPICE is also now available on Linux.  This HOWTO describes the design flow employed to perform SPICE simulations  using gEDA tools on Linux.
  </p>
  
  <p>
  Permission is granted to copy, distribute and/or modify this document under  the terms of the GNU Free Documentation License, Version 2 or any later  version published by the Free Software Foundation with no Invariant Sections,  no Front-Cover Texts, and no Back-Cover Texts.  You may obtain a copy of the GNU Free Documentation License from the Free  Software Foundation by visiting their Web site (<a href="http://www.fsf.org/"; class="urlextern" title="http://www.fsf.org/";  rel="nofollow">http://www.fsf.org/</a>) by writing to: Free Software Foundation, Inc., 59 Temple Place - Suite  330, Boston, MA 02111-1307, USA. <a href="#fn__1" name="fnt__1" id="fnt__1" class="fn_top" onmouseover="fnt('1', this, event);">1)</a>.
  </p>
  
  </div>
  <!-- SECTION [1-1357] -->
  <h2><a name="introduction" id="introduction">Introduction</a></h2>
  <div class="level2">
  
  <p>
  Modern engineering is a computer-intensive discipline.  Like professionals in other engineering disciplines, electrical engineers  and electronics designers are heavy users of all kinds of CAD software,  including software for circuit design and simulation, as well as PCB and  chip production. Electrical engineers have a special name for the CAD software they use: EDA, which stands for &ldquo;Electronic Design Automation&rdquo;. Under this rubric fall many different kinds of CAD software. For example, during the front-end stages of a design, an electrical engineer will use a program called a &ldquo;schematic capture&rdquo; package to enter his design into the computer.  A schematic capture program is basically a specialized drawing program  incorporating symbols used in creating a circuit design. After drawing his schematic, the electrical engineer may choose to simulate the behavior of his circuit in order to verify that his design will work as desired. The most popular program for this purpose is SPICE (Simulation Program with Integrated Circuit Emphasis), which was developed at Berkeley starting in the 1970s, and is widely available in multiple forms today. SPICE is now considered a fundamental engineering tool, and is an essential part of the repertoire of most practicing engineers.
  </p>
  
  <p>
  The <a href="http://www.geda.seul.org/"; class="urlextern" title="http://www.geda.seul.org/";  rel="nofollow">gEDA project</a> is an open-source effort to create a <acronym title="GNU General Public License">GPL</acronym>&lsquo;ed EDA suite running on Linux. GEDA has developed to the point where the power and quality of the tools is quite high; using the gEDA suite, you can now create complex SPICE netlists (files) incorporating vendor model files. You can then use various simulators running on Linux to perform SPICE simulations of your netlists. The purpose of this document is to explain how to use the gEDA tools (typically running on GNU/Linux) to perform SPICE simulations. In particular, this HOWTO documents the usage of <strong>spice-sdb</strong>, which is an advanced backend for the gEDA netlister (<strong>gnetlist</strong>) used to create SPICE netlists. <strong>spice-sdb</strong> is bundled with the gEDA tool suite; if you have installed gEDA, you are  ready to create SPICE netlists. This HOWTO also provides advice about using ngspice/tclspice and/or LTSpice to simulate a circuit netlisted with <strong>spice-sdb</strong>.
  </p>
  
  </div>
  <!-- SECTION [1358-3623] -->
  <h3><a name="target_audience_for_this_howto" id="target_audience_for_this_howto">Target audience for this HOWTO</a></h3>
  <div class="level3">
  
  <p>
  This HOWTO is not a tutorial about circuit design or SPICE simulation. Rather, it is designed to help the practicing engineer begin using gEDA to perform SPICE simulations on the Linux platform. Therefore, I assume that you are already familiar with electronic design, the mechanics of schematic capture using EDA tools, and SPICE simulation in general. I also assume that you are reasonably familiar with the GNU/Linux operating system and its development environment. Finally, I assume that you have already installed gEDA, and know how to use it.  If you need to come up to speed on any of these subjects, further information is available at the following websites:
  </p>
  <ul>
  <li class="level1"><div class="li"> The gEDA project: <a href="http://www.geda.seul.org/"; class="urlextern" title="http://www.geda.seul.org";  rel="nofollow">http://www.geda.seul.org</a></div>
  </li>
  <li class="level1"><div class="li"> SPICE3 syntax and commands: <a href="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/"; class="urlextern" title="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/";  rel="nofollow">http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/</a></div>
  </li>
  <li class="level1"><div class="li"> Ngspice: <a href="http://ngspice.sourceforge.net/"; class="urlextern" title="http://ngspice.sourceforge.net/";  rel="nofollow">http://ngspice.sourceforge.net/</a></div>
  </li>
  <li class="level1"><div class="li"> Tclspice: <a href="http://tclspice.sourceforge.net/"; class="urlextern" title="http://tclspice.sourceforge.net/";  rel="nofollow">http://tclspice.sourceforge.net/</a></div>
  </li>
  <li class="level1"><div class="li"> LTSpice: <a href="http://www.linear.com/software/"; class="urlextern" title="http://www.linear.com/software/";  rel="nofollow">http://www.linear.com/software/</a></div>
  </li>
  <li class="level1"><div class="li"> Spice on Linux resources: <a href="http://www.brorson.com/gEDA/SPICE/"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/";  rel="nofollow">http://www.brorson.com/gEDA/SPICE/</a></div>
  </li>
  <li class="level1"><div class="li"> Free Dog &ndash; The Free EDA Users Group: <a href="http://www.freeedaug.org/"; class="urlextern" title="http://www.freeedaug.org/";  rel="nofollow">http://www.freeedaug.org/</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3624-4807] -->
  <h3><a name="acknowledgements" id="acknowledgements">Acknowledgements</a></h3>
  <div class="level3">
  
  <p>
  This document does not live in isolation. Several active members of the free EDA community were instrumental in helping me to creat this HOWTO. First and foremost, Paolo Nenzi, the author of ngspice, took my original HOWTO and turned it into a Lyx document which I could then make a DocBook. Thanks, Paolo, for helping with this HOWTO, and more importantly, thanks for all the great work on ngspice! Also at the top of the list stands Ales Hvezda, who is the driving force behind the gEDA project. Without Ales, none of this would have been possible; his contribution of <strong>gschem</strong> is invaluable. Thanks, Ales, for creating gEDA and distributing it worldwide under the <acronym title="GNU General Public License">GPL</acronym> &ndash; you&rsquo;ve started a revolution! Stefan Jones deserves a deep thank-you  for his work on tclspice, and his graceous support and integration efforts when I submitted patches to the tclspice project. I should also thank W. Kazubski and S. Gieltjes &ndash; they wrote the original SPICE netlisters upon which I based gnet-spice-sdb.scm. I also want to thank Ken Healy for contributing the netlist sorting patch, and Peter Kaiser for pushing me to include some features useful for chip simulation. Peter also deserves thanks for writing some of the device-oriented sections of this document. Finally, I should acknolwedge the contributions and suggestions I receive from readers of the geda-user e-mail list. The beauty of free software is that it encourages collaboration, which means that the end product is greater than what one individual could acheive alone.
  </p>
  
  </div>
  <!-- SECTION [4808-6362] -->
  <h3><a name="the_big_picturethe_design_flow_in_geda" id="the_big_picturethe_design_flow_in_geda">The big picture: the design flow in gEDA</a></h3>
  <div class="level3">
  
  <p>
  In EDA, the concept of &ldquo;design flow&rdquo; is important. GEDA is a suite of tools used to do electronic design &ndash; it is not a single application. &ldquo;Design flow&rdquo; refers to the order in which you use the tools to acheive your goal. Depending upon whether you are doing analog or digital design, designing boards or chips, the type of files required by the manufacturer of your boards, and a number of other factors, you will use different tools from the gEDA suite to acheive your goal.
  </p>
  
  <p>
  A flow diagram of the gEDA design flow is shown in the figure below. The diagram shows a simple flow suitable for designing, simulating, and laying out PC boards. As can be seen, the simulation activitiy (blue blocks) is a loop. That is, you create your design and simulate it repeatedly until it behaves according to your desired specifications. <a href="_detail/geda_geda_flow.html" class="media" title="geda:geda_flow.png"><img src="_media/geda_geda_flow.png" class="mediacenter" alt="" /></a> The design flow used in gEDA. Shown under &ldquo;simulation&rdquo; are several different types of simulator available. In this HOWTO, we are interested only in the SPICE variants (e.g. ngspice, tclspice).
  </p>
  
  </div>
  <!-- SECTION [6363-7459] -->
  <h3><a name="overview_of_spice_usage_with_geda" id="overview_of_spice_usage_with_geda">Overview of SPICE usage with gEDA</a></h3>
  <div class="level3">
  
  <p>
  Conceptually, SPICE simulation in gEDA proceeds via the following steps:
  </p>
  <ol>
  <li class="level1"><div class="li"> Creation and gathering of schematic symbols and SPICE model files. Often, the SPICE model files are obtained from your component vendor. You can generally find most models by checking the component vendor&rsquo;s website.</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture using symbols and SPICE models created in step 1.</div>
  </li>
  <li class="level1"><div class="li"> Netlist generation from the schematic created in step 2.</div>
  </li>
  <li class="level1"><div class="li"> SPICE simulation of the circuit described by the netlist created in step 3.</div>
  </li>
  </ol>
  
  <p>
   These steps are illustrated by the blue boxes in the flow diagram above.
  </p>
  
  <p>
  To create a SPICE netlist, the netlister (<strong>gnetlist</strong>) iterates through the entire schematic and looks at several parts of each component&rsquo;s symbol in order to create a blob of SPICE code. In general, each component can generate one or more lines of SPICE code. Component information needed by the netlister is held in two places:
  </p>
  <ol>
  <li class="level1"><div class="li"> The symbol itself, in the attribute, which is attached when the symbol is created, and is typically accessed through the symbol editor.</div>
  </li>
  <li class="level1"><div class="li"> In attributes manually attached to the component during schematic capture using <strong>gschem</strong>.</div>
  </li>
  </ol>
  
  <p>
   Since there are two places the netlister looks for information, <strong><em>you must make sure that the required information is available in both places</em></strong>.
  </p>
  
  </div>
  <!-- SECTION [7460-8803] -->
  <h3><a name="detailed_design_simulation_flow_summary" id="detailed_design_simulation_flow_summary">Detailed design/simulation flow summary</a></h3>
  <div class="level3">
  
  <p>
  The detailed steps required to design and simulate a circuit using gEDA look like this:
  </p>
  <ol>
  <li class="level1"><div class="li"> Schematic symbol creation with correct <strong><code>device</code></strong> attribute. (Usually, the symbols have already been created with the correct <strong><code>device</code></strong> attribute, but if you are having problems, it doesn&rsquo;t hurt to check them.)</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture using <strong>gschem</strong>.</div>
  </li>
  <li class="level1"><div class="li"> Assignment of SPICE attributes (<strong><code>value</code></strong>, <strong><code>model</code></strong>, <strong><code>file</code></strong>, <strong><code>type</code></strong>, , etc.) to components using <strong>gschem</strong> or <strong>gattrib</strong>.</div>
  </li>
  <li class="level1"><div class="li"> Assignment of <strong><code>refdes</code></strong>  using e.g. <strong>refdes_renum</strong>.</div>
  </li>
  <li class="level1"><div class="li"> Creation of netlist using: <strong><code>gnetlist -g spice-sdb</code></strong></div>
  </li>
  <li class="level1"><div class="li"> Check netlist for correctness (manually open and inspect netlist).</div>
  </li>
  <li class="level1"><div class="li"> Run spice using a simulator such as <strong>LTSpice</strong>, <strong>ngspice</strong>, or <strong>tclspice</strong>.</div>
  </li>
  <li class="level1"><div class="li"> Plot/analyze results (often plotting/analysis tools are incorporated in the simulator).</div>
  </li>
  <li class="level1"><div class="li"> If you are not happy with your circuit&rsquo;s performance as revealed by simulation, go back to step 2, fix it using <strong>gschem</strong>  and iterate.</div>
  </li>
  </ol>
  
  <p>
   The purpose of this HOWTO is to provide the detailed understanding necessary to successfully navigate this process.
  </p>
  
  </div>
  <!-- SECTION [8804-9983] -->
  <h2><a name="preliminary_workpreparing_your_symbols_and_spice_files" id="preliminary_workpreparing_your_symbols_and_spice_files">Preliminary work: preparing your symbols and SPICE files</a></h2>
  <div class="level2">
  
  <p>
  When you create schematic symbols for inclusion into your schematic, you must make sure that certain built-in attributes are correctly configured. The steps outlined below are done by editing the symbol itself using the symbol editor in <strong>gschem</strong>, or by editing the symbol file itself using a text editor.
  </p>
  
  </div>
  <!-- SECTION [9984-10360] -->
  <h3><a name="configuring_your_symbols" id="configuring_your_symbols">Configuring your symbols</a></h3>
  <div class="level3">
  
  </div>
  
  <h4><a name="identifying_the_component_to_the_netlister" id="identifying_the_component_to_the_netlister">Identifying the component to the netlister</a></h4>
  <div class="level4">
  
  <p>
  The SPICE netlister can recognize any particular symbol in two ways:
  </p>
  <ol>
  <li class="level1"><div class="li"> The symbol&rsquo;s <strong><code>device</code></strong> attribute, and</div>
  </li>
  <li class="level1"><div class="li"> The symbol&rsquo;s <strong><code>refdes</code></strong>.</div>
  </li>
  </ol>
  
  <p>
   Both of these attributes are attached to the symbol when the symbol is created.
  </p>
  
  <p>
  Each symbol has a <strong><code>device</code></strong>  attribute attached to it. The <strong><code>device</code></strong> attribute is the first thing the netlister examines when processing the symbol. There are a number of devices which are native to the netlister, meaning that the netlister knows exactly how to deal with these types of devices. Native device types include <strong>RESISTOR</strong>, <strong>CAPACITOR</strong>, <strong>NPN_TRANSISTOR</strong>, etc. The entire list of native devices is present in <a href="#appendix_a" title="geda:csygas &crarr;" class="wikilink1">Appendix A</a> - Native components and their attributes.
  </p>
  
  <p>
  The <strong><code>device</code></strong> attribute is hidden during normal use of <strong>gschem</strong>. Most often, the symbol&rsquo;s creator has already given the symbol the correct <strong><code>device</code></strong>  attribute. However, because the <strong><code>device</code></strong> attribute is hidden from the ordinary user, it can sometimes cause problems with SPICE netlist creation when it is set to an unexpected value. To view the <strong><code>device</code></strong> attribute, go into the symbol editor (select the symbol to edit, and do <strong><em>Hierarchy</em></strong> &rarr; <strong><em>down symbol</em></strong>, and turn on invisible attributes (<strong><em>Edit</em></strong> &rarr; <strong><em>show/hide inv text</em></strong>). If the <strong><code>device</code></strong> attribute is incorrect, you may change it by editing the symbol itself using a text editor.
  </p>
  
  <p>
  If a symbol is not native (i.e. the netlister doesn&rsquo;t recognize it as a built-in type), the netlister relies upon the first letter of the <strong><code>refdes</code></strong> to determine how to process the symbol. The <strong><code>refdes</code></strong> prefix is also built into the symbol when it is created. Example <strong><code>refdes</code></strong> prefixes are <strong>R</strong> for resistors, <strong>C</strong> for capacitors, <strong>Q</strong> for transistors, etc. <strong><code>refdes</code></strong> prefixes correct for SPICE are listed in <a href="#appendix_a" title="geda:csygas &crarr;" class="wikilink1">Appendix A</a> - Native components and their attributes. Note that relying upon the <strong><code>refdes</code></strong> to identify the component for SPICE is not foolproof &ndash; for example, the netlister cannot distinguish between NPN and PNP transistors based upon the <strong><code>refdes</code></strong>. Therefore, it is always best to use a native <strong><code>device</code></strong> in your symbols.
  </p>
  
  </div>
  
  <h4><a name="setting_the_pin_order" id="setting_the_pin_order">Setting the pin order</a></h4>
  <div class="level4">
  
  <p>
  The netlister emits a components pins in the order set by the <strong><code>pinseq</code></strong> attribute. Note that this is not the same as the physical pin location. To set the <strong><code>pinseq</code></strong> attribute, first determine the pin ordering you want. SPICE uses a specific pin order for many components, including diodes and transistors. For example, a bipolar transistor&rsquo;s pins listed in CBE order. Another example: if your symbol is meant to represent an IC modeled with a vendor&rsquo;s <strong><code>.subckt</code></strong>, the order of the connections to the subcircuit is set by the <strong><code>.subckt</code></strong> line in the file.
  </p>
  
  <p>
  Once you know the order in which to emit the pins, simply set the <strong><code>pinseq</code></strong> attribute with the correct order for the part. This will ensure that the part&rsquo;s pins are emitted in the correct order.
  </p>
  
  </div>
  <!-- SECTION [10361-13440] -->
  <h3><a name="configuring_your_spice_files" id="configuring_your_spice_files">Configuring your SPICE files</a></h3>
  <div class="level3">
  
  <p>
  Files holding complicated SPICE models or other SPICE code may be incorporated into the final SPICE netlist by including appropriate symbols into the schematic. SPICE model files are usually obtained from component vendors. Dealing with these files is straightforward. However, some issues should be kept in mind when preparing models for use during schematic capture:
  </p>
  <ul>
  <li class="level1"><div class="li"> It is usually prudent to place these files into a dedicated directory distinct from the symbol directories.</div>
  </li>
  <li class="level1"><div class="li"> <em>Make sure that the SPICE files pin assignments correctly correspond to the pins as defined in the component&rsquo;s symbol!</em> This is hard to over-emphasize. The order in which pins are listed in a .subckt file do not necessarily correspond to the physical pin ordering of the part. As described above, pins are emitted from the netlister in the order given by the <strong><code>pinseq</code></strong> attribute.</div>
  </li>
  <li class="level1"><div class="li"> <em>Make sure that the last character in a SPICE model file is a carriage return.</em> If no carriage return exists, then the next component listed in the netlist may be placed on the same line as the last line of the SPICE model file.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [13441-14587] -->
  <h2><a name="creating_your_circuitschematic_capture" id="creating_your_circuitschematic_capture">Creating your circuit: schematic capture</a></h2>
  <div class="level2">
  
  <p>
  Schematic capture is the process by which one uses a special-purpose drawing program to draw a schematic diagram of the circuit under design. In the gEDA environment, the schematic capture program is called <strong>gschem</strong>. I assume you already know how to use <strong>gschem</strong>. If not, consult the documentation available at the gEDA website: <a href="http://www.geda.seul.org/"; class="urlextern" title="http://www.geda.seul.org/";  rel="nofollow">http://www.geda.seul.org/</a>. For the purposes of creating SPICE netlists, you must use <strong>gschem</strong> to attach attributes to components, and possibly also incorporate other SPICE directives into your netlist. After you are done with schematic capture, you create the SPICE netlist by running gEDA&rsquo;s netlister <strong>gnetlist</strong> on your design.
  </p>
  
  </div>
  <!-- SECTION [14588-15311] -->
  <h3><a name="gschem_attributes_for_spice_netlisting" id="gschem_attributes_for_spice_netlisting">Gschem attributes for spice netlisting</a></h3>
  <div class="level3">
  
  <p>
  There are several ways that spice attributes may be associated with a component using <strong>gschem</strong>. The way you choose to do this depends upon many factors, including the type of component, and the size and format of the SPICE model.
  </p>
  
  </div>
  <!-- SECTION [15312-15593] -->
  <h3><a name="component_attributes_and_meanings" id="component_attributes_and_meanings">Component attributes and meanings</a></h3>
  <div class="level3">
  
  <p>
  The following attributes are meaningful for SPICE netlisting, and may be attached from within <strong>gschem</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: The reference designator of the component. Valid values depend upon the component type and are given in <a href="#appendix_a" title="geda:csygas &crarr;" class="wikilink1">Appendix A</a> - Native components and their attributes.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: For passives, this is the component value. For actives, this is the type (model no.) of the component (e.g. 2N3904, uA741). When a model for an active is instantiated separately from the component itself, the <strong><code>value</code></strong> attribute holds the name of the spice model.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong>: This holds a one line spice model for the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>file</code></strong>: This holds the name of a file. Typically, this is a file holding e.g. a SPICE .MODEL, .SUBCKT, or other SPICE code.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: This holds the name of the spice model referred to in a .MODEL or .SUBCKT statement. <strong><code>model-name</code></strong> is mainly used to identify the spice model name in the symbol <strong><code>spice-model-1.sym</code></strong>. Active components should call out this name in the <strong><code>device</code></strong> attribute to associate the component with its particular spice model or subcircuit.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>type</code></strong>: This specifies the type of component and is used by spice when interpreting the model parameters. Valid values depend upon the device being modeled.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [15594-16953] -->
  <h3><a name="refdes_conventions" id="refdes_conventions">refdes conventions</a></h3>
  <div class="level3">
  
  <p>
  As a prerequisite to handling SPICE-related attributes, the SPICE netlister requires that all components must have a <strong><code>refdes</code></strong> attached to them. The <strong><code>refdes</code></strong> may be attached either by hand (which is laborious), or using the program <strong>refdes_renum</strong> included in the gEDA distribution.
  </p>
  
  <p>
  Note that the first letter of the <strong><code>refdes</code></strong> must correspond to the appropriate letter for spice simulation. The <strong><code>refdes</code></strong> convention is given in the appendix.
  </p>
  
  </div>
  <!-- SECTION [16954-17448] -->
  <h3><a name="passives" id="passives">Passives</a></h3>
  <div class="level3">
  
  </div>
  
  <h4><a name="basic_passives" id="basic_passives">Basic passives</a></h4>
  <div class="level4">
  
  <p>
  The most basic components which one encounters in SPICE are passive components like resistors and capacitors which have numeric values, but no other modeling attributes. In this case the following attributes must be filled in:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: The correct <strong><code>refdes</code></strong> for the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: For passives, this is the numeric value of the component (e.g. 100pF). For actives, this attribute may be filled in, but if no model attribute is available elsewhere in the schematic, the value is not used (in SPICE netlisting, anyway).</div>
  </li>
  <li class="level1"><div class="li"> If only a <strong><code>refdes</code></strong> and <strong><code>value</code></strong> attribute are encountered, the netlister will write a single line into the output file.</div>
  </li>
  </ul>
  
  </div>
  
  <h4><a name="example_resistor" id="example_resistor">Example resistor:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong> = R2</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>  = 220</div>
  </li>
  </ul>
  
  <p>
   SPICE line generated: <strong><code>R2 0 4 220</code></strong>
  </p>
  
  <p>
  (note that &ldquo;0&rdquo; and &ldquo;4&rdquo; correspond to the net nodes connected to the component, and are generated automatically by <strong>gnetlist</strong>.)
  </p>
  
  </div>
  
  <h4><a name="example_capacitor" id="example_capacitor">Example capacitor:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong> = C22</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong> = 1UF</div>
  </li>
  </ul>
  
  <p>
   SPICE line generated: <strong><code>C22 4 23 1UF</code></strong>
  </p>
  
  </div>
  <!-- SECTION [17449-18544] -->
  <h3><a name="passives_with_additional_attributes" id="passives_with_additional_attributes">Passives with additional attributes</a></h3>
  <div class="level3">
  
  <p>
  Oftentimes, passive components have additional attributes attached to them for spice simulation. Examples of such attributes are temperature coefficients (for resistors) and initial conditions (for reactive components). These additional components may be incorporated into the SPICE file by simply attaching them to the component&rsquo;s <strong><code>model</code></strong> attribute. Specifically, the required attributes are:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: Correct component <strong><code>refdes</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: Numerical component <strong><code>value</code></strong>, as always.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong>: One line string holding additional parameters, formatted as a valid SPICE string.</div>
  </li>
  </ul>
  
  <p>
   This string is placed after the component value in the line generated by gnetlist. Therefore, it is important to format the string placed in the <strong><code>model</code></strong> line to be valid SPICE code. Otherwise, you will risk causing the SPICE simulator to barf.
  </p>
  
  </div>
  
  <h4><a name="example_resistor1" id="example_resistor1">Example resistor:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong> = R5</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong> = 1MEG</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong> = TC=0.001,0.015</div>
  </li>
  </ul>
  
  <p>
   SPICE line generated: <strong><code>R2 0 4 220 TC=0.001,0.015</code></strong>
  </p>
  
  </div>
  <!-- SECTION [18545-19630] -->
  <h3><a name="passives_for_semiconductor_design" id="passives_for_semiconductor_design">Passives for semiconductor design</a></h3>
  <div class="level3">
  
  <p>
  The values for resistors and capacitors are often given as dimensions in an ASIC design. SPICE takes from the technology library the typical value per square and calculates the actual value in Ohm or Farad by itself. Therefor the following attributes are required:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: The correct refdes for the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: corresponds to the model in the technology library.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>w</code></strong>, <strong><code>l</code></strong>: dimensions of the device.</div>
  </li>
  </ul>
  
  <p>
   The technology library must be included with an <strong><code>.include</code></strong> line in the SPICE input file.
  </p>
  
  </div>
  
  <h4><a name="example_semiconductor_resistor" id="example_semiconductor_resistor">Example semiconductor resistor:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong> = R6</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong> = rpoly</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>w</code></strong> = 3u</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>l</code></strong> = 100u</div>
  </li>
  </ul>
  
  <p>
   SPICE line generated: <strong><code>R6 0 5 rpoly w=3u l=100u</code></strong>
  </p>
  
  </div>
  
  <h4><a name="example_semiconductor_resistor_model" id="example_semiconductor_resistor_model">Example semiconductor resistor model:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> model rpoly R rsh=300</div>
  </li>
  </ul>
  
  <p>
   This should be part of the technology library from your ASIC vendor.
  </p>
  
  </div>
  <!-- SECTION [19631-20557] -->
  <h3><a name="transistors_and_diodes" id="transistors_and_diodes">Transistors and diodes</a></h3>
  <div class="level3">
  
  <p>
  Transistors and diodes are generally accompanied by a device-specific model. Each model attempts to capture the detailed nonlinear dynamics of its particular device; otherwise, SPICE simulation is pointless. The SPICE model may be either a short, one-line string of parameters, or a multi-line set of SPICE parameters. A typical one-line parameter string is a short list of parameters describing a small-signal diode. Typical multi-line models come from component vendors, who often provide models for their components in a text file. Since there are two broad formats of SPICE information, there are two approaches to incorporating these parameters into the schematic:
  </p>
  
  </div>
  
  <h4><a name="one_line_string_of_spice_parameters" id="one_line_string_of_spice_parameters">One line string of SPICE parameters</a></h4>
  <div class="level4">
  
  <p>
  To incorporate a one line string of SPICE parameters into the netlist, the following attributes must be attached to the component:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: Correct component <strong><code>refdes</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: The model number or part number of the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: The name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a <strong><code>value</code></strong> attribute to the component, this parameter is optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong>: One line string holding additional parameters. Do not place the model parameters in parentheses &ndash; <strong>gnetlist</strong> will do this for you.</div>
  </li>
  </ul>
  
  </div>
  
  <h4><a name="example_diode" id="example_diode">Example diode:</a></h4>
  <div class="level4">
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong> = D5</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong> = 1N1004</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong> = IS=0.5UA RS=6 BV=5.20</div>
  </li>
  </ul>
  
  <p>
   SPICE lines generated: <strong><code>D5 2 6 1N1004 MODEL 1N1004 D (IS=0.5UA RS=6 BV=5.20)</code></strong>
  </p>
  
  </div>
  
  <h4><a name="spice_model_file" id="spice_model_file">SPICE model file</a></h4>
  <div class="level4">
  
  <p>
  To incorporate a file-full of SPICE parameters into the netlist, the following attributes must be attached to the component:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: Correct component <strong><code>refdes</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: The model number or part number of the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: the name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a <strong><code>value</code></strong> attribute to the component, this parameter is optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>file</code></strong>: The file name of the SPICE model which you wish to incorporate into the netlist. This file name may specify either a relative or an absolute path, but it is probably better to use an absolute path to avoid problems if you ever move your schematic directory.</div>
  </li>
  </ul>
  
  <p>
   Note that you need to make sure that the model name held in your SPICE model file is the same as the <strong><code>value</code></strong> or <strong><code>model-name</code></strong> attributes you attached to the component. It is also a good idea to verify that the pin assignments in the model file correspond to the pin assignments made by the component symbol.
  </p>
  
  </div>
  <!-- SECTION [20558-23258] -->
  <h3><a name="actives_--_integrated_circuits" id="actives_--_integrated_circuits">Actives -- integrated circuits</a></h3>
  <div class="level3">
  
  <p>
  Integrated circuits are incorporated into the netlist similarly to transistors and diodes. As such, you may incorporate the spice information either as a one-line parameter string, or as a model file.
  </p>
  
  </div>
  
  <h4><a name="one_line_string_of_spice_parameters1" id="one_line_string_of_spice_parameters1">One line string of SPICE parameters</a></h4>
  <div class="level4">
  
  <p>
  To incorporate a one line string of SPICE parameters into the netlist, the following attributes must be attached to the component:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: Correct component <strong><code>refdes</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: The model number or part number of the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: the name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a <strong><code>value</code></strong> attribute to the component, this parameter is optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model</code></strong>: One line string holding additional parameters. Do not place the model parameters in parentheses &ndash; <strong>gnetlist</strong> will do this for you.</div>
  </li>
  </ul>
  
  </div>
  
  <h4><a name="spice_.model_or_.subckt_file" id="spice_.model_or_.subckt_file">SPICE .MODEL or .SUBCKT file</a></h4>
  <div class="level4">
  
  <p>
  To incorporate a file-full of SPICE parameters into the netlist, the following attributes must be attached to the component:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>refdes</code></strong>: Correct component <strong><code>refdes</code></strong>. <em>Note that if the file holds a .MODEL, the</em> <strong><code>refdes</code></strong> <em>should start with U; if the file holds a .SUBCKT, the refdes should start with X.</em> The netlister checks for the file type and tries to &ldquo;do the right thing&rdquo;, but problems can arise if you don&rsquo;t follow this rule.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>value</code></strong>: The model number or part number of the component.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>model-name</code></strong>: The name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a <strong><code>value</code></strong> attribute to the component, this parameter is optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>file</code></strong>: The name of the file holding the SPICE .MODEL or .SUBCKT which you wish to incorporate into the netlist. This file name may specify either a relative or an absolute path, but it is probably better to use an absolute path to avoid problems if you ever move your schematic directory.</div>
  </li>
  </ul>
  
  <p>
   Note that you need to make sure that the model name held in your SPICE model file is the same as the <strong><code>value</code></strong> or <strong><code>model-name</code></strong> attributes you attached to the component. It is also a good idea to verify that the pin assignments in the model file correspond to the pin assignments made by the component symbol.
  </p>
  
  </div>
  <!-- SECTION [23259-25602] -->
  <h3><a name="independent_sources" id="independent_sources">Independent sources</a></h3>
  <div class="level3">
  
  <p>
  There are two independent sources: voltage sources and current sources. For incorporation into a SPICE netlist, they both work the same way. To incorporate an independent source into your SPICE netlist, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Place the independent source on your schematic. (Do <strong><em>Add</em></strong> &rarr; <strong><em>Component</em></strong> &rarr; <strong><em>spice</em></strong> &rarr; <strong>&lt;independent source name&gt;.sym</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: V? or I?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>value</code></strong>: A one line string in SPICE format describing the source.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [25603-26176] -->
  <h3><a name="dependent_sources" id="dependent_sources">Dependent sources</a></h3>
  <div class="level3">
  
  <p>
  There are four dependent sources:
  </p>
  
  <p>
  This section remains TBD.
  </p>
  
  </div>
  <!-- SECTION [26177-26266] -->
  <h3><a name="spice_components" id="spice_components">SPICE components</a></h3>
  <div class="level3">
  
  </div>
  
  <h4><a name="spice_model_block" id="spice_model_block">Spice model block</a></h4>
  <div class="level4">
  
  <p>
  In certain situations, you may wish to embed a spice model block directly into your schematic.  This is done when you have several devices with a &ldquo;value&rdquo; attribute calling out for a spice model. Depending upon whether the spice block is one line or multi-line, you may embed the code in one of two ways:
  </p>
  
  </div>
  
  <h4><a name="one_line_spice_model" id="one_line_spice_model">One line SPICE model:</a></h4>
  <div class="level4">
  <ol>
  <li class="level1"><div class="li"> Place a spice model block on your schematic. (Do <strong><em>Add</em></strong> &rarr; <strong><em>Component</em></strong> &rarr; <strong><em>spice</em></strong> &rarr; <strong>spice-model-1.sym</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: A?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>model</code></strong>: model name (i.e. the model name used in the components being modeled)</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>type</code></strong>: One of the valid spice component types defined in the spice <acronym title="specification">spec</acronym>.</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>value</code></strong>: The corresponding one-line spice model</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="multi-line_spice_model" id="multi-line_spice_model">Multi-line SPICE model:</a></h4>
  <div class="level4">
  <ol>
  <li class="level1"><div class="li"> Place a spice model block on your schematic.(Do <strong><em>Add</em></strong> &rarr; <strong><em>Component</em></strong> &rarr; <strong><em>spice</em></strong> &rarr; <strong>spice-model-1.sym</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: A?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>model</code></strong>: model name</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>file</code></strong>: Name of file holding SPICE model code (i.e. .MODEL or .SUBCKT).</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="include_block" id="include_block">Include block</a></h4>
  <div class="level4">
  
  <p>
  The include block places a .INCLUDE directive into your netlist.
  </p>
  <ol>
  <li class="level1"><div class="li"> Place a spice model block on your schematic. (Do <strong><em>Add</em></strong> &rarr; <strong><em>Component</em></strong> &rarr; <strong><em>spice</em></strong> &rarr; <strong>spice-include-1.sym</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: A?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>file</code></strong>: Name of file to include.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="spice_directive_block" id="spice_directive_block">SPICE directive block</a></h4>
  <div class="level4">
  
  <p>
  Placing a SPICE directive block into your schematic creates an arbitrary block of SPICE code in the netlist. The directive may be either statements held in a file, or a one-line string held in the <strong><code>model</code></strong> attribute. The netlister will simply dump the contents of the string or the file into your netlist verbatim. Examples of situations where this is useful include:
  </p>
  <ul>
  <li class="level1"><div class="li"> .TEMP statement</div>
  </li>
  <li class="level1"><div class="li"> .IC statement</div>
  </li>
  <li class="level1"><div class="li"> Other SPICE statements for which <strong>gschem</strong> has no symbol.</div>
  </li>
  </ul>
  
  <p>
   To place a SPICE directive on your schematic, do:
  </p>
  <ol>
  <li class="level1"><div class="li"> Place a SPICE directive block on your schematic. (Do <strong><em>Add</em></strong> &rarr; <strong><em>Component</em></strong> &rarr; <strong><em>spice</em></strong> &rarr; <strong>spice-directive-1.sym</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: A?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>file</code></strong>: Name of file to include.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [26267-28676] -->
  <h3><a name="handling_hierarchical_models" id="handling_hierarchical_models">Handling hierarchical models</a></h3>
  <div class="level3">
  
  <p>
  In SPICE modeling, there are often situations where you wish to create a schematic representation of some particular component as a .SUBCKT, and then embed that component&rsquo;s model in a higher level schematic. A common example might be as follows: You are doing a microwave simulation, and want to use a capacitor model which includes parasitic inductances and resistances, as well as the capacitance. Capacitor manufacturers often supply a printed schematic showing a circuit topology incorporating parasitics, and specify values for the parasitics. You would like to draw the capacitor model using gschem, netlist it to create a .SUBCKT, and then use the .SUBCKT to model capacitors in a higher lever schematic.
  </p>
  
  <p>
  Since this kind of task is very common in SPICE simulation, <strong>gnet-spice-sdb</strong> now supports it (starting with rev 20030331). To create a lower level .SUBCKT and use it in a higher level schematic, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Draw the schematic of the lower level component (e.g. the capacitor + parasitics) using <strong>gschem</strong>.</div>
  </li>
  <li class="level1"><div class="li"> On the lower level schematic, place a <strong><code>spice-subcircuit-LL</code></strong> block (<strong>spice-subcircuit-LL-1.sym</strong>). This alerts the netlister that the schematic is a Lower Level .SUBCKT. Attach the following attributes to the symbol:<br/>
   <br/>
   * <strong><code>model-name</code></strong> = cap_with_parasitics<br/>
   <br/>
   (Of course, &ldquo;cap_with_parasitics&rdquo; is the example we use here. Use your own model name in your schematic.) Upon netlisting, this schematic symbol will cause the netlist to insert &ldquo;.SUBCKT cap_with_parasitics&rdquo; into the first line of the netlist file.</div>
  </li>
  <li class="level1"><div class="li"> On the lower level schematic, attach a <strong><code>spice-subcircuit-IO</code></strong> symbol (<strong>spice-subcircuit-IO-1.sym</strong>) to each IO net (i.e. connection to the upper level). Number the refdeses of the IO symbols in the same order as you would like the IO nets to be listed in the .SUBCKT line in the output file. (i.e. P1 = first, P2 = second, etc.)</div>
  </li>
  <li class="level1"><div class="li"> When you are done with the lower level schematic, netlist it in the usual way. For example, if your schematic is called <strong><code>cap_with_parasitics.sch</code></strong>, netlist it by saying: <br/>
   <br/>
   <strong><code>gnetlist -g spice-sdb -o cap_with_parasitics.cir cap_with_parasitics.sch</code></strong><br/>
   <br/>
   This will dump the SPICE netlist into the file called &ldquo;<strong>cap_with_parasitics.cir</strong>&ldquo;. Visually inspect the .cir file to make sure that netlisting worked correctly.</div>
  </li>
  <li class="level1"><div class="li"> Next, create a symbol for the upper level schematic which will point to the .SUBCKT. Note that the symbol must have a starting with the letter &ldquo;X&rdquo;. To ensure that this happens, do the following:</div>
  <ul>
  <li class="level2"><div class="li"> Use <strong>gschem</strong> to draw the symbol. I usually draw a box around a model symbol to distinguish it from a normal component. Make any other annotations desired.</div>
  </li>
  <li class="level2"><div class="li"> In the symbol, make sure that the pins are ordered identically to the order in which you have placed the pins in the .SUBCKT. This is done by editing the symbol with a text editor and setting the <strong><code>pinseq</code></strong> attribute. The netlister will output the pins in the order determined by the <strong><code>pinseq</code></strong> attribute.</div>
  </li>
  <li class="level2"><div class="li"> Using a text editor, give the symbol a <strong><code>device</code></strong> attribute like &ldquo;capacitor-model&rdquo;. Do <strong>not</strong> assign the symbol one of the native device types listed in the appendix! The goal is to create a symbol whose <strong><code>refdes</code></strong> starts with &ldquo;X&rdquo;, and if the <strong><code>device</code></strong> is a recognized type, this will not happen.</div>
  </li>
  <li class="level2"><div class="li"> Using a text editor, give the symbol the <strong><code>refdefs</code></strong> attribute &ldquo;X?&rdquo;</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Create the upper level schematic. Place your newly created symbol on the schematic as many times as required and wire up the schematic in the usual way.</div>
  </li>
  <li class="level1"><div class="li"> To point your symbol to the lower level .SUBCKT, double click on the symbol and set the following attributes:<br/>
   <br/>
   * <strong><code>file</code></strong> = cap_with_parasitics.cir<br/>
   * <strong><code>model-name</code></strong> = cap_with_parasitics<br/>
   <br/>
   as well as any other attributes required (e.g. <strong><code>refdes</code></strong>).</div>
  </li>
  <li class="level1"><div class="li"> Now netlist your upper level schematic the usual way. The contents of each .SUBCKT file is dumped into the main netlist. Inspect your netlist visually using a text editor to ensure that it is correct. It is a good idea to pay particular attention to the following:</div>
  <ul>
  <li class="level2"><div class="li"> Verify that the ordering of the nets connecting the upper level netlist to the lower level .SUBCKT is correct.</div>
  </li>
  <li class="level2"><div class="li"> Make sure that the upper level model-name and the lower level model name (on the .SUBCKT declaration line) are the same.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  <p>
   Once the netlist is created, you may simulate your design using any SPICE simulator desired. Some simulators running on Linux are covered below.
  </p>
  
  </div>
  <!-- SECTION [28677-33217] -->
  <h2><a name="spice_netlist_generation" id="spice_netlist_generation">SPICE netlist generation</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [33218-33254] -->
  <h3><a name="using_gnetlist" id="using_gnetlist">Using gnetlist</a></h3>
  <div class="level3">
  
  <p>
  Once the schematic is captured, a SPICE netlist can be generated running gEDA&rsquo;s command-line program <strong>gnetlist</strong> on the schematic files. <strong>gnetlist</strong> is architected in two sections: a front-end processor written in C which reads in the .sch file and creates from it an internal, generic representation of your design, and a back-end netlister written in SCHEME. Using this architecture, <strong>gnetlist</strong> is highly customizable; different SCHEME backends are used to write out different netlist formats. The beauty of this scheme (pun intended) is that gEDA users can easily write their own netlisters to suit their own applications. The back-end Scheme file which implements advanced SPICE netlisting is called <strong><code>gnet-spice-sdb.scm</code></strong>, and it lives in the <strong><code>${PREFIX}/geda/share/gEDA/scheme</code></strong> directory.
  </p>
  
  <p>
  <strong>gnetlist</strong> with <strong>spice-sdb</strong> is invoked from the command line in the following way: <strong><code>gnetlist [OPTIONS] -g spice-sdb filename1 ... filenameN</code></strong>. The following command-line options are available with spice-sdb: 
  </p>
  <pre class="code">-i          Interactive scheme mode
  -I          Put .INCLUDE &lt;filename&gt; in output file instead of model file's contents
  -q          Quiet mode
  -l filename Load scheme file before loading backend
  -m filename Load scheme file after loading backend, but still before executing procedure
  -g proc     Scheme procedure to execute (i.e. spice-sdb)
  -o filename Output netlist filename
  -c string   Execute string as a scheme script
  -v          Verbose mode on
  -s          Sort output netlist (for Gnucap)</pre>
  
  </div>
  <!-- SECTION [33255-34815] -->
  <h3><a name="creating_the_netlist_using_gnetlist_and_spice-sdb" id="creating_the_netlist_using_gnetlist_and_spice-sdb">Creating the netlist using gnetlist and spice-sdb</a></h3>
  <div class="level3">
  
  <p>
  Creating a netlist from a schematic is easy. To generate a SPICE netlist, just do the following:
  </p>
  <ul>
  <li class="level1"><div class="li"> Save your schematic to &lt;<strong><code>filename.sch</code></strong>&gt;</div>
  </li>
  <li class="level1"><div class="li"> Create the SPICE netlist by doing &ldquo;<strong><code>gnetlist -g spice-sdb &lt;filename.sch&gt;</code></strong>&ldquo;. The output is a netlist held in the file <strong><code>output.net</code></strong>. Alternatively, if you wish to give your output file a different name, set the output name using the <strong>-o</strong> switch. For example:<br/>
   <br/>
   <strong><code>gnetlist -g spice-sdb -o amplifier.cir amplifier.sch</code></strong><br/>
   <br/>
   takes the design schematic called &ldquo;<strong><code>amplifier.sch</code></strong>&rdquo; and outputs a SPICE netlist named &ldquo;<strong><code>amplifier.cir</code></strong>&ldquo;.</div>
  </li>
  <li class="level1"><div class="li"> Inspect your SPICE netlist using a text editor. Verify that there are no missing attributes or other netlist problems.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [34816-35609] -->
  <h3><a name="common_netlisting_problems" id="common_netlisting_problems">Common netlisting problems</a></h3>
  <div class="level3">
  
  <p>
  The following list attempts to catalog common problems with the netlist and the associated fixes:
  </p>
  <ul>
  <li class="level1"><div class="li"> ERROR_INVALID_<acronym title="Personal Identification Number">PIN</acronym>:<br/>
   This can happen if the symbol&rsquo;s <strong><code>pinseq</code></strong> attributes don&rsquo;t start at 1, or have gaps in the numbering. This must be fixed by editing the symbol itself in a text editor.</div>
  </li>
  <li class="level1"><div class="li"> ERROR: In procedure caddr:<br/>
   This error is quite common. It usually occurs when you forget to add a mandatory attribute. To rectify the problem, try running gnetlist in verbose mode (<strong><code>gnetlist -v -g spice-sdb &lt;filename.sch&gt;</code></strong>). The netlister will stop processing and bomb out at the part with the missing attribute. Having therefore identified the offending part, you can re-open the schematic in gnetlist and fix the attributes.</div>
  </li>
  </ul>
  
  <p>
   Finally, remember that it is important to manually inspect your SPICE netlist prior to using it in simulation. Please keep in mind that the netlister is still &ldquo;beta&rdquo; quality, and some problems may still exist in netlist generation.
  </p>
  
  </div>
  <!-- SECTION [35610-36615] -->
  <h2><a name="spice_simulation" id="spice_simulation">SPICE simulation</a></h2>
  <div class="level2">
  
  <p>
  There are several options for doing SPICE simulations under GNU/Linux; I will highlight three:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>LTSpice</strong>, which is a freeware SPICE simulator originally released by Linear Technologies as a component selection/design tool running under Windows. Because its SPICE engine is very fast and powerful, it has become a popular SPICE simulator amongst hobbyists and design engineers who prefer to use free tools. Originally written for Windows, LTSpice has been tweaked to run under GNU/Linux using wine; I recommend using it if you need a robust, professional-quality SPICE simulator.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Ngspice</strong>, which is the &ldquo;official&rdquo; SPICE simulator of the gEDA suite. Ngspice is a revival of the SPICE 3 code for Linux. It provides a simulation engine, a command-line driven front-end, and the capability to plot simulation results graphically under the X Windows System. Ngspice is Linux-native and open-source. It is the SPICE of choice for those who want to do SPICE simulations easily on Linux, or want to hack and improve SPICE&rsquo;s internals.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Tclspice</strong>, is a fork off the ngspice development path. Tclspice is a superset of ngspice which (in theory) exports the SPICE command set to a TCL <acronym title="Application Programming Interface">API</acronym>, allowing you to embed SPICE analyses into a TCL program. This is useful for automating a design optimization, amongst other things. Tclspice is the simulator to use if you are interested in advanced, scripted design.</div>
  </li>
  </ul>
  
  <p>
   There is also a <acronym title="GNU General Public License">GPL</acronym>&lsquo;ed simulator called <strong>gnucap</strong>, which is based upon (or is the descendant of) Al&rsquo;s Circuit Simulator (<strong><code>ACS</code></strong>). I haven&rsquo;t used it very much; information about gnucap is therefore TBD.
  </p>
  
  </div>
  <!-- SECTION [36616-38268] -->
  <h3><a name="ltspice" id="ltspice">LTSpice</a></h3>
  <div class="level3">
  
  <p>
  LTSpice was written by Mike Englehardt and others at Linear Technologies, and is given away by LinearTech as a design aid for engineers wishing to simulate the performance of LinearTech&rsquo;s switch mode power supply controllers. The package incorporates a schematic capture front end, fast and powerful SPICE engine, and the capability for plotting the results of many different types of SPICE analysis. Personally, I think the schematic capture front-end is hard to use and clunky; <strong>gschem</strong> knocks its socks off for ease of use and features. However, the SPICE engine and analysis stuff in LTSpice is simply great.
  </p>
  
  <p>
  LTSpice was originally developed to run under Windows, but Mike has tweaked it so that it runs fairly well on GNU/Linux under wine. (Only the help menu system is broken &ndash; the rest of the package runs well). Another good feature of LTSpice is that it is well supported &ndash; Mike reads the newsgroup <strong><code>sci.electronics.cad</code></strong> regularly and is generally happy to help people who experience problems with it. Therefore, despite its Windoze heritage, I recommend LTSpice as a powerful, professional-quality simulation and analysis back end for gEDA.
  </p>
  
  </div>
  
  <h4><a name="installation_and_configuration_of_ltspice" id="installation_and_configuration_of_ltspice">Installation and configuration of LTSpice</a></h4>
  <div class="level4">
  
  <p>
  To install and configure LTSpice, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Download and install wine. I have had success using Wine-20030219. Later versions probably also work.</div>
  </li>
  <li class="level1"><div class="li"> Download LTSpice. It is available under <a href="http://www.linear.com/software"; class="urlextern" title="http://www.linear.com/software";  rel="nofollow">http://www.linear.com/software</a> under the name SwitcherCAD-III.</div>
  </li>
  <li class="level1"><div class="li"> Run the LTSpice installer under wine.</div>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="running_ltspice_with_geda_designs" id="running_ltspice_with_geda_designs">Running LTSpice with gEDA designs</a></h4>
  <div class="level4">
  
  <p>
  LTSpice can read a file holding a gEDA SPICE netlist. I have had success doing LTSpice simulations in the following way:
  </p>
  <ol>
  <li class="level1"><div class="li"> First of all, make sure that you are logged in as a normal user &ndash; Wine doesn&rsquo;t like to run when invoked by root.</div>
  </li>
  <li class="level1"><div class="li"> Create a file in your project directory called &ldquo;Simulation.cmd&rdquo;. In this file place your spice analysis commands (e.g. .OP, .AC, .DC, etc.)</div>
  </li>
  <li class="level1"><div class="li"> Place a SPICE include block into your schematic. For the file attribute, type in &ldquo;Simulation.cmd&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> Netlist your design.</div>
  </li>
  <li class="level1"><div class="li"> Create a link from your netlist <strong><code>output.net</code></strong> and a netlist in the directory in which SwCADIII lives. Make the netlist suffix <strong><code>.cir</code></strong>. For example:<br/>
   <br/>
   ln -s ${DESIGN_HOME}/output.net ${WINE_HOME}/.wine/fake_windows/Program Files/LTC/SwCADIII/MyDesign.cir<br/>
   <br/>
  </div>
  </li>
  <li class="level1"><div class="li"> Run LTSpice: cd into the directory where SwCADIII lives and say &ldquo;<strong><code>wine scad3.exe</code></strong>&rdquo;</div>
  </li>
  <li class="level1"><div class="li"> From the SwCADIII <acronym title="Graphical User Interface">GUI</acronym>, do: <strong><em>File</em></strong> &rarr; <strong><em>Open</em></strong> &rarr; <strong><em>(files of type netlist [.cir])</em></strong>, and select your file.</div>
  </li>
  <li class="level1"><div class="li"> Run the simulator by clicking on the run button, or doing: <strong><em>Simulate</em></strong> &rarr; <strong><em>Run</em></strong>.</div>
  </li>
  <li class="level1"><div class="li"> Select the variables to graph, and then click OK. SwCADIII does the rest of the work.</div>
  </li>
  </ol>
  
  <p>
   Naturally, it is very important to play around with LTSpice to understand how to use it effectively, but the above description should suffice to get you started.
  </p>
  
  </div>
  <!-- SECTION [38269-41208] -->
  <h3><a name="ngspice" id="ngspice">Ngspice</a></h3>
  <div class="level3">
  
  <p>
  Ngspice was started at the University of Rome &ldquo;La Sapienza&rdquo; by Paolo Nenzi as an attempt to create a <acronym title="GNU General Public License">GPL</acronym>&lsquo;ed version of the standard Berkeley SPICE version 3 by re-writing the entire SPICE package. Plans were also laid to create better, more robust computational algorithms for the simulation engine. More information is available at the ngspice website: <a href="http://ngspice.sourceforge.net/"; class="urlextern" title="http://ngspice.sourceforge.net/";  rel="nofollow">http://ngspice.sourceforge.net/</a>. In light of his lofty plans, what Paolo did, however, was a little different: He took the SPICE 3 code which had been floating around the internet for many years, refactored it, and hacked the build system so that it would compile using the normal GNU make procedure. This was a major achievement for which Paolo deserves great praise. Unfortunately, from the look of the webpage, development on <strong>ngspice</strong> seems to have ceased at the end of 2001. Indeed, development did slow down considerably after 2001, but recently Paolo has been working on <strong>ngspice</strong> again. He released the latest version, <strong>ngspice-rework-15</strong>, in February 2004. This version is available only on the Sourceforge download page; Paolo hasn&rsquo;t updated the rest of the project&rsquo;s website.
  </p>
  
  </div>
  
  <h4><a name="installation_and_configuration_of_ngspice" id="installation_and_configuration_of_ngspice">Installation and configuration of ngspice</a></h4>
  <div class="level4">
  
  <p>
  I generally find it best to download, configure, and compile the source  of <strong>ngspice</strong> instead of trying to install a binary package. That&rsquo;s the approach I outline here.
  </p>
  
  </div>
  
  <h4><a name="downloading_the_source_code" id="downloading_the_source_code">Downloading the source code</a></h4>
  <div class="level4">
  
  <p>
  Get the latest distribution from: <a href="http://sourceforge.net/projetcs/ngspice"; class="urlextern" title="http://sourceforge.net/projetcs/ngspice";  rel="nofollow">http://sourceforge.net/projetcs/ngspice</a>. Make sure that you get the latest version for best performance and the most features. As of May 2004, the latest release is <strong>ngspice-rework-15</strong>. Install the source in the place you typically put your sources. I like to keep my gEDA sources in a separate directory, for example <strong><code>/usr/local/geda/sources/ngspice</code></strong>. You might adopt a similar system.
  </p>
  
  </div>
  
  <h4><a name="extracting_the_source_code" id="extracting_the_source_code">Extracting the source code</a></h4>
  <div class="level4">
  
  <p>
  The source code you downloaded is distributed in a &ldquo;tarball&rdquo;, a compressed archive. You have to extract archived files by doing: 
  </p>
  <pre class="code">user@host:~$ cd &lt;directory where you want to extract the source&gt;
  user@host:~sources$ tar -xvzf &lt;/path/to/package.tar.gz&gt;
  user@host:~sources$ cd &lt;extracted dir&gt;</pre>
  
  <p>
  At this point you are in the top level directory of ngspice. Read the usual files, like <strong><code>README</code></strong>, and <strong><code>INSTALL</code></strong>, to learn about the simulator and the installation process. Reading <strong><code>NOTES</code></strong> file is also a good idea; it holds information valuable if you want to hack or debug features present in ngspice.
  </p>
  
  </div>
  
  <h4><a name="configuration_and_compilation_of_ngspice" id="configuration_and_compilation_of_ngspice">Configuration and compilation of ngspice.</a></h4>
  <div class="level4">
  
  <p>
  Ngspice uses the typical &ldquo;<strong><code>configure &amp;&amp; make &amp;&amp; make install</code></strong>&rdquo; sequence used by other GNU software. There are numerous configure time options available for ngspice. A complete listing with attendant documentation is TBD; the best way to see them all is to look at <strong><code>configure.ac</code></strong> itself. Many of the configure time options pertain to debugging the simulator, or are to enable experimental analyses. For newbies, three configure time options are worth mentioning:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>&ndash;enable-xspice</code></strong>: This flag compiles in support for XSpice extensions. These extensions allow you to define devices whose behavior is given by arbitrary &ldquo;code models&rdquo;. Arguably, the most important code model is <strong><code>spice2poly</code></strong>, which is a model which translates SPICE2 style POLY constructs into an XSpice model usable by SPICE 3.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>&ndash;with-readline</code></strong>: This flag compiles GNU readline support into <strong>ngspice</strong>, which means that you can use emacs-style key commands, as well as the arrow keys to move around in the command line interface (CLI). Without this feature, the command line interface can be hostile, meaning that if you make a mistake in typing a long command, you have no choice but to type it all over again. Paolo discourages use of the readline feature because it mixes <acronym title="GNU General Public License">GPL</acronym> code (readline) with BSD code (<strong>ngspice</strong>), but he left the option open to other to decide for themselves how pure they wanted to be.</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>&ndash;prefix</code></strong>: This flag point to the base directory where you want your binaries to be installed.</div>
  </li>
  </ul>
  
  <p>
   Before you run configure, you should check the options you want to include, a brief description is given in appendix TBD. Once ready type: 
  </p>
  <pre class="code">user@host:~sources/&lt;tld&gt;$./configure --enable-xspice --with-readline  --prefix=/usr/local/geda &lt;other configure options&gt;</pre>
  
  <p>
  Of course, &ldquo;<strong><code>&ndash;prefix=</code></strong>&rdquo; should point to the place where you put <strong>your</strong> gEDA stuff. After issuing the command, your simulator is configured and ready to be compiled. Compilation is straightforward: 
  </p>
  <pre class="code">user@host:~sources/&lt;tld&gt;$ make &amp;&amp; make install</pre>
  
  <p>
  As always, you will probably need to be root in order to install the packages in a public directory, in such case you should do: 
  </p>
  <pre class="code">user@host:~sources/&lt;tld&gt;$ make
  user@host:~sources/&lt;tld&gt;$ su -c make install</pre>
  
  </div>
  
  <h4><a name="testing_the_installation" id="testing_the_installation">Testing the installation</a></h4>
  <div class="level4">
  
  <p>
  At this point, you should be able to use ngspice. You can test your installation by trying one of the test circuits held in the tests directory. I recommend running the TransImpedanceAmp test, since it tests the SPICE2 POLY functionality.
  </p>
  
  </div>
  
  <h4><a name="using_ngspice" id="using_ngspice">Using ngspice</a></h4>
  <div class="level4">
  
  <p>
  Running ngspice is very simple. Just issue the command: 
  </p>
  <pre class="code">user@host:~$ ngspice filename.net</pre>
  
  <p>
  at the unix command prompt, and ngspice will load the SPICE netlist called <strong><code>filename.net</code></strong> into its workspace, and leave you at an ngspice command prompt. You can run the simulator by saying &ldquo;run&rdquo;. Your results will be stored in SPICE vectors for later printing or plotting. The command set available to you is documented at: <a href="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5"; class="urlextern" title="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5";  rel="nofollow">http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5</a>
  </p>
  
  <p>
  To make use of the SPICE2 POLY codemodel, you need to load it into <strong>ngspice</strong> <strong><em class="u">before</em></strong> you load your netlist. (If you load it after loading your netlist, POLYs in your netlist are not translated, and therefore won&rsquo;t be simulated correctly.) To load the codemodel, just say: 
  </p>
  <pre class="code">codemodel /usr/local/geda/lib/spice/spice2poly.cm</pre>
  
  <p>
  (or wherever you put your codemodels) at the ngspice prompt. Note that you must provide the <strong>absolute path</strong> to the location of the codemodel; ngspice isn&rsquo;t smart enough to look for it in any default locations. (Also note that you should specify the location where <strong><code>spice2poly.cm</code></strong> lives on your machine; the path above is for mine).
  </p>
  
  <p>
  A better way to read in the <strong><code>spice2poly</code></strong> codemodel is to include it in the ngspice initialization file, <strong><code>spinit</code></strong>. The initialization file lives in the directory <strong><code>/usr/local/geda/share/ng-spice-rework/scripts</code></strong> (or where ever you placed your gEDA installation). Other ngspice customizations may also be placed into the <strong><code>spinit</code></strong> file.
  </p>
  
  </div>
  <!-- SECTION [41209-47913] -->
  <h3><a name="tclspice" id="tclspice">Tclspice</a></h3>
  <div class="level3">
  
  <p>
  While the main branch of ngspice development hibernated in 2002, some friendly people at MultiGig Ltd. (<a href="http://www.multigig.com/"; class="urlextern" title="http://www.multigig.com/";  rel="nofollow">http://www.multigig.com/</a>) were busy developing a branch of ngspice which they called <strong>tclspice</strong>. Tclspice is a superset of ngspice in which much of the SPICE command set is exported as an <acronym title="Application Programming Interface">API</acronym> to TCL. The purpose of this is to facilitate scripting of SPICE analyses. This is a very powerful tool: With tclspice you can write a TCL script which runs a loop, tweaks component values, runs an analysis, and then evaluates the circuit performance with the tweaked components before looping again. Obviously, this ability can be used to perform automated, multi-dimensional circuit optimization. When complete, tclspice might possibly become a &ldquo;killer-app&rdquo; for open-source EDA.
  </p>
  
  </div>
  
  <h4><a name="downloading_installing_and_building_tclspice" id="downloading_installing_and_building_tclspice">Downloading, installing, and building tclspice</a></h4>
  <div class="level4">
  
  <p>
  Tclspice&rsquo;s project homepage is at: <a href="http://tclspice.sourceforge.net/"; class="urlextern" title="http://tclspice.sourceforge.net/";  rel="nofollow">http://tclspice.sourceforge.net/</a>. The tclspice source lives at <a href="http://sourceforge.net/projects/tclspice"; class="urlextern" title="http://sourceforge.net/projects/tclspice";  rel="nofollow">http://sourceforge.net/projects/tclspice</a>. Download and installation of tclspice follow the same steps as those detailed for ngspice above. Since tclspice is a superset of ngspice, you can install ngspice alone from the tclspice sources if desired. To build the entire package requires a couple of extra steps. Here, I present a series of steps which will build both ngspice (the stand-alone, CLI driven program) and the TCL <acronym title="Application Programming Interface">API</acronym> from the tclspice source.
  </p>
  
  <p>
  Before building tclspice, you need to have the following packages already installed:
  </p>
  <ul>
  <li class="level1"><div class="li"> TclX (tclx8.3.5 works for me.)</div>
  </li>
  <li class="level1"><div class="li"> tclreadline (tclreadline-2.1.0 works for me.)</div>
  </li>
  <li class="level1"><div class="li"> BLT for TCL (blt2.4z works for me.)</div>
  </li>
  <li class="level1"><div class="li"> TCL/Tk (8.4.3. works for me)</div>
  </li>
  </ul>
  
  <p>
   If you don&rsquo;t have these packages already on your Linux box, you need to get and build them. Note that building TclX requires having the sources for TCL and Tk, so you will also need to get those sources if you don&rsquo;t have them installed already. I am running successfully with TCL/Tk 8.4.3, although 8.3.X versions are also supposed to work. Also, if you want to run spice in the background you need to recompile TCL and Tk to enable thread support if they haven&rsquo;t got it enabled already (redhat packages haven&rsquo;t).
  </p>
  
  <p>
  Assuming you have downloaded and installed the additional packages mentioned above, the following steps will build both ngspice and the TCL <acronym title="Application Programming Interface">API</acronym> on your machine: 
  </p>
  <pre class="code">user@host:~sources/&lt;tld&gt;$ ./configure --enable-xspice --with-readline  --prefix=/usr/local/geda 
  user@host:~sources/&lt;tld&gt;$ make &amp;&amp; make install (this makes and installs regular old ngspice)
  user@host:~sources/&lt;tld&gt;$ ./configure --enable-xspice --prefix=/usr/local/geda --enable-tcl --enable-experimental --disable-shared
  user@host:~sources/&lt;tld&gt;$ make tcl &amp;&amp; make install-tcl</pre>
  
  <p>
  As always, you will probably need to be root in order to install the packages in a public directory, in such case you should do: 
  </p>
  <pre class="code">user@host:~sources/&lt;tld&gt;$ su -c make install
  user@host:~sources/&lt;tld&gt;$ su -c make install-tcl</pre>
  
  <p>
  to install your packages. Now you will be ready to write TCL scripts which incorporate SPICE commands. Information about using tclspice is given below. Finally, if you are interested in hacking tclspice (or even if you are not), it&rsquo;s a good idea to read the <strong><code>NOTES</code></strong> file living in the top source directory for a couple of useful pointers.
  </p>
  
  </div>
  
  <h4><a name="use_of_tclspice" id="use_of_tclspice">Use of tclspice</a></h4>
  <div class="level4">
  
  <p>
  Tclspice is designed to export SPICE commands to TCL programs. To use tclspice, you just need to say &ldquo;<strong><code>package require spice</code></strong>&rdquo; at the beginning of your TCL program. Thereafter, to invoke a SPICE command, you just call it in the spice namespace. For example, the following TCL program will read in a SPICE netlist, command a transient analysis, run the simulation, and then plot the voltage observed over time on net Vout: 
  </p>
  <pre class="code">#! tclsh 
  package require spice
  spice::codemodel /usr/local/src/tclspice-0.2.12/src/xspice/icm/spice2poly.cm
  spice::source netlistname.cir
  spice::tran 0.1ns 40ns
  spice::run
  spice::plot Vout
  puts &quot;All done now!&quot;</pre>
  
  <p>
  Note that since tclspice doesn&rsquo;t read the ngspice initialization file <strong><code>spinit</code></strong>, you will need to put any initialization commands directly into the TCL program. For example, in the above example we read the spice2poly codemodel directly into the workspace. Many other commands are also available; the entire tclspice commandset is documented at: <a href="http://tclspice.sourceforge.net/docs/tclspice_com.html"; class="urlextern" title="http://tclspice.sourceforge.net/docs/tclspice_com.html";  rel="nofollow">http://tclspice.sourceforge.net/docs/tclspice_com.html</a>
  </p>
  
  </div>
  
  <h4><a name="tclspice_problems" id="tclspice_problems">Tclspice problems</a></h4>
  <div class="level4">
  
  <p>
  A major problem with tclspice (which was inherited from ngspice) is that it leaks memory. Therefore, the time over which you may run a simulation is limited. This means that if you want to do an optimization by looping through a circuit many, many times, you may run out of memory before your program has completed its optimization. This is a known issue with tclspice, and efforts are underway to plug the leaks.
  </p>
  
  <p>
  Meanwhile, there are some workarounds which can be used on moderate-sized designs to facilitate long optimization runs. One method I have employed is to have the optimizer write its current state into a file after every circuit analysis, and read its starting state from the same file. The optimizer also stores the current list of best components in another file, and reads this file at the start of every run. Then, I have a TCL program called <strong><code>TaskMgr.tcl</code></strong> which runs in a loop; at each iteration of the loop it forks a child process to run the optimizer. Meanwhile, the parent process waits for 5 minutes (a heuristically determined time), and then issues a &ldquo;KILL&rdquo; signal to the child before looping and starting the optimizer again. This way, the optimizer never runs long enough to consume all the memory in my machine. The <strong><code>TaskMgr.tcl</code></strong> program is shown here: 
  </p>
  <pre class="code">#! tclsh
  package require Tclx
  while {1} {
    set PID [fork] 
    if {$PID} {
      # Parent
      after 300000
      puts &quot;About to kill child PID = $PID . . . .&quot;
      kill $PID
      wait $PID
    } else {
      # Child
      source Optimize.tcl
      # If we ever get through this, we can print out the following:
      error &quot;We are done now!!!!!!&quot;
    }
  }</pre>
  
  <p>
  Note that <strong><code>TaskMgr.tcl</code></strong> needs the TclX package you already installed to run tclspice. Also, you may want to change the wait time to a different value depending upon the memory and speed of your machine. Finally, the parent has to wait on $PID because that causes the child process&rsquo;s corpse to be taken off the Linux kernel&rsquo;s task list when it dies. Otherwise, you will end up with a lot of zombie processes lurking around your machine as the optimizer runs &ndash; a long optimization could turn your system into &ldquo;the night of the living dead&rdquo;!
  </p>
  
  <p>
  This method of waiting a specific amount of time for the child process is preferable if a single analysis run takes a relatively short time compared to the time required to eat all memory in the machine. If the analysis time is comparable to the time taken to eat all memory in the machine, a better approach is to have the parent keep track of the analysis state, kick off a single analysis run, and then have the run terminate after every iteration. Whether this is preferable depends upon the size and complexity of your design; you may want to experiment with your analysis to see just how long it takes and how much memory it consumes. I have found that a design comprised of six op amps (with corresponding vendor models) and 50 or so passives will run in under 10 seconds on a PIII 333MHz with 128MB RAM. Therefore, your design must be very big before a single analysis will eat a significant amount of RAM.
  </p>
  
  </div>
  <!-- SECTION [47914-55445] -->
  <h1><a name="appendix_a" id="appendix_a">Appendix A</a></h1>
  <div class="level1">
  
  <p>
  <strong>Native components and their attributes</strong>
  </p>
  
  <p>
  Presented in table 1 are the devices and associated attributes used with spice-sdb. Bold faced attributes are required, normal typeface attributes are optional. Note that the <strong><code>device</code></strong> attribute is invisible, and is normally attached to the symbol when it is created. The other attributes are attached to the symbol during schematic capture using <strong>gschem</strong>.
  </p>
  
  <p>
  When dealing with simple actives (diodes, transistors) having SPICE models held in files, you only need to set the <strong><code>model-name</code></strong> and <strong><code>file</code></strong> attributes; you don&rsquo;t need to set the <strong><code>model</code></strong> attribute. However, if your simple active has a one-line SPICE model which you wish to enter directly into the schematic, then set the <strong><code>model</code></strong> and <strong><code>model-name</code></strong> attribures; you don&rsquo;t need to set the <strong><code>file</code></strong> attribute. 
  </p>
  <table class="inline">
  	<tr>
  		<th>device</th><th>refdes</th><th>value</th><th>model</th><th>file</th><th>model-name</th><th>type</th><th>comment</th>
  	</tr>
  	<tr>
  		<td>RESISTOR</td><td class="centeralign">  R?  </td><td class="centeralign">  (4)  </td><td class="centeralign">  (2)  </td><td class="centeralign">  -  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (11)  </td>
  	</tr>
  	<tr>
  		<td>CAPACITOR</td><td class="centeralign">  C?  </td><td class="centeralign">  (4)  </td><td class="centeralign">  (3)  </td><td class="centeralign">  -  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (11)  </td>
  	</tr>
  	<tr>
  		<td>POLARIZED_CAPACITOR</td><td class="centeralign">  C?  </td><td class="centeralign">  (4)  </td><td class="centeralign">  (3)  </td><td class="centeralign">  -  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (11)  </td>
  	</tr>
  	<tr>
  		<td>INDUCTOR</td><td class="centeralign">  L?  </td><td class="centeralign">  (4)  </td><td class="centeralign">  (3)  </td><td class="centeralign">  -  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (11)  </td>
  	</tr>
  	<tr>
  		<td>SPICE-ccvs</td><td class="centeralign">  H?  </td><td class="centeralign">  (5)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td>SPICE-cccs</td><td class="centeralign">  F?  </td><td class="centeralign">  (5)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td>SPICE-vscs</td><td class="centeralign">  E?  </td><td class="centeralign">  (5)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td>SPICE-vccs</td><td class="centeralign">  G?  </td><td class="centeralign">  (5)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td>SPICE-nullor</td><td class="centeralign">  E?  </td><td class="centeralign">  (5)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td>DIODE</td><td class="centeralign">  D?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>PMOS_TRANSISTOR</td><td class="centeralign">  M?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>NMOS_TRANSISTOR</td><td class="centeralign">  M?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>PNP_TRANSISTOR</td><td class="centeralign">  Q?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>NPN_TRANSISTOR</td><td class="centeralign">  Q?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>PFET_TRANSISTOR</td><td class="centeralign">  J?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>NFET_TRANSISTOR</td><td class="centeralign">  J?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>MESFET_TRANSISTOR</td><td class="centeralign">  B?  </td><td class="centeralign">  Part number  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  Model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>IC</td><td class="centeralign">  U?  </td><td class="centeralign">  Part number  </td><td class="rightalign">    </td><td class="centeralign">  .model file name  </td><td class="centeralign">  Name of model  </td><td class="centeralign">  -  </td><td class="centeralign">  For IC with .model file  </td>
  	</tr>
  	<tr>
  		<td>IC</td><td class="centeralign">  X?  </td><td class="centeralign">  Part number  </td><td class="rightalign">    </td><td class="centeralign">  .subckt file name  </td><td class="centeralign">  Name of .subckt  </td><td class="centeralign">  -  </td><td class="centeralign">  For IC with .subckt file  </td>
  	</tr>
  	<tr>
  		<td>model</td><td class="centeralign">  A?  </td><td class="centeralign">  -  </td><td class="centeralign">  One line SPICE model  </td><td class="centeralign">  .model file name  </td><td class="centeralign">  (9)  </td><td class="centeralign">  (10)  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>include</td><td class="centeralign">  A?  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  .include file name  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  (13)  </td>
  	</tr>
  	<tr>
  		<td>options</td><td class="centeralign">  A?  </td><td class="centeralign">  (8)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  (13)  </td>
  	</tr>
  	<tr>
  		<td>directive</td><td class="centeralign">  A?  </td><td class="centeralign">  (1)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  (12)  </td>
  	</tr>
  	<tr>
  		<td>VOLTAGE_SOURCE</td><td class="centeralign">  V?  </td><td class="centeralign">  (6)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  Independent voltage source  </td>
  	</tr>
  	<tr>
  		<td>CURRENT_SOURCE</td><td class="centeralign">  I?  </td><td class="centeralign">  (7)  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  -  </td><td class="centeralign">  Independent current source  </td>
  	</tr>
  </table>
  <br />
  
  <p>
   (1) One line string holding SPICE statements for inclusion in netlist<br/>
   (2) One line of SPICE model parameters (e.g. TC, etc.)<br/>
   (3) One line of SPICE model parameters (e.g. IC, POLY, etc.)<br/>
   (4) Component numeric value<br/>
   (5) String describing source behavior<br/>
   (6) One line string holding voltage source behavior<br/>
   (7) One line string holding current source behavior<br/>
   (8) line of options to include<br/>
   (9) Name of model pointed to by other components<br/>
   (10) Corresponding SPICE model type (valid types given below)<br/>
   (11) Model parameters are placed inside parentheses after component value<br/>
   (12) For modeling, one must include either model or file<br/>
   (13) Places .include directive in SPICE netlist<br/>
  
  </p>
  
  <p>
  &ldquo;Native to the netlister&rdquo; means that there is a corresponding blob of scheme code which knows exactly how to handle these components and is guaranteed (almost) to generate correct spice code. Symbols having &ldquo;device&rdquo; attributes not on the above list are handled using the scheme function &ldquo;spice-sdb:write-default-component&rdquo;, which looks at the refdes of the component to make a decision about how to treat the component. In general, this function will &ldquo;do the right thing&rdquo; when generating spice code, but it is not guaranteed. In particular, this function cannot distinguish between N and P type transistors, and will generate an &lt;unknown&gt; type for the .MODEL string in the netlist. This will probably cause your SPICE simulator to barf. Therefore, it is best to make sure that all devices used have the proper &ldquo;device&rdquo; attribute.
  </p>
  
  </div>
  <!-- SECTION [55446-60117] -->
  <h1><a name="appendix_b" id="appendix_b">Appendix B</a></h1>
  <div class="level1">
  
  <p>
  <strong>Valid &ldquo;type&rdquo; values.</strong>
  </p>
  
  <p>
  The &ldquo;type&rdquo; attribute is a flag signaling the spice engine the component type, and prepares it to accept model parameters specific to that component type. The following values are valid SPICE &ldquo;type&rdquo;s: 
  </p>
  <table class="inline">
  	<tr>
  		<th class="centeralign">  Component  </th><th class="centeralign">  &ldquo;type&rdquo;  </th><th class="centeralign">  Comment  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  RESISTOR  </td><td class="centeralign">  RES  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  CAPACITOR  </td><td class="centeralign">  CAP  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  POLARIZED_CAPACITOR   </td><td class="centeralign">  CAP  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  INDUCTOR  </td><td class="centeralign">  IND   </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  DIODE  </td><td class="centeralign">  D  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  PMOS_TRANSISTOR  </td><td class="centeralign">  PMOS  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  NMOS_TRANSISTOR  </td><td class="centeralign">  NMOS  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  PNP_TRANSISTOR  </td><td class="centeralign">  PNP  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  NPN_TRANSISTOR  </td><td class="centeralign">  NPN  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  PFET_TRANSISTOR  </td><td class="centeralign">  PJF  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  NFET_TRANSISTOR  </td><td class="centeralign">  NJF  </td><td class="rightalign">    </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  MESFET_TRANSISTOR  </td><td class="centeralign">  -  </td><td class="rightalign">    </td>
  	</tr>
  </table>
  <br />
  
  <p>
   Table 2: Valid &ldquo;type&rdquo; attributes for components. 
  </p>
  
  </div>
  <!-- SECTION [60118-] --><div class="footnotes">
  <div class="fn"><a href="#fnt__1" id="fn__1" name="fn__1" class="fn_bot">1)</a> 
  This HOWTO is released under the GNU Free Documentation License thanks to the generosity of Electroniscript, inc. The most recent copy can always be found at <a href="http://www.brorson.com/gEDA/HOWTO/"; class="urlextern" title="http://www.brorson.com/gEDA/HOWTO/";  rel="nofollow">http://www.brorson.com/gEDA/HOWTO/</a></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_cygwin.html
  
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  <h1><a name="installing_geda_gaf_on_windows_-_the_cygwin_way" id="installing_geda_gaf_on_windows_-_the_cygwin_way">Installing gEDA/gaf on Windows - the Cygwin way</a></h1>
  <div class="level1">
  
  <p>
   This guide describes one way to build gEDA/gaf (gschem and friends) on the Windows operating system. It uses Cygwin as the layer between Windows and the *nix world (ie gcc, make, bash etc...).
  </p>
  
  </div>
  <!-- SECTION [1-257] -->
  <h2><a name="instructions" id="instructions">Instructions</a></h2>
  <div class="level2">
  
  <p>
   1. Download and run setup.exe from cygwin website: <a href="http://www.cygwin.com/"; class="urlextern" title="http://www.cygwin.com";  rel="nofollow">http://www.cygwin.com</a>.
  </p>
  
  <p>
  In the package selection dialog, select the following packages:
  </p>
  
  <p>
  (Hint: press the &ldquo;view&rdquo; button once to arrange the list in alphabetical order) 
  </p>
  <pre class="code">atk-devel
  file
  gcc
  gtk2-x11-devel
  guile-devel
  make
  pango-devel
  patchutils
  pcre-devel
  pcre-doc
  pkg-config
  xorg-x11-devel
  xorg-x11-fscl
  xterm</pre>
  
  <p>
   2. Append these lines to your .bash_profile: 
  </p>
  <pre class="code">export LD_LIBRARY_PATH=$HOME/geda/lib:$LD_LIBRARY_PATH
  export PATH=$HOME/geda/bin:$PATH
  export PKG_CONFIG_PATH=$HOME/geda/lib/pkgconfig:$PKG_CONFIG_PATH</pre>
  
  <p>
   Update your environment:
  </p>
  <pre class="code">$ source .bash_profile</pre>
  
  <p>
   3. Go to the <a href="http://www.geda.seul.org/sources.html"; class="urlextern" title="http://www.geda.seul.org/sources.html";  rel="nofollow">gEDA sources download page</a>.
  </p>
  
  <p>
  From the gEDA/gaf group, download <strong>only</strong> the packages which have a date as its version (like 20060123). The necessary dependencies where already installed in step 1.
  </p>
  
  <p>
  4. Download  <a href="http://sourceforge.net/tracker/download.php?group_id=161080&atid=818428&file_id=182795&aid=1511658"; class="urlextern" title="http://sourceforge.net/tracker/download.php?group_id=161080&amp;atid=818428&amp;file_id=182795&amp;aid=1511658";  rel="nofollow">cygwin.patch</a> in the same folder as the above.
  </p>
  
  <p>
  5. Go to the download directory and type:
  </p>
  <pre class="code">$ make open
  $ patch -p1 &lt; cygwin.patch
  $ make install
  ( ...patience... )</pre>
  
  <p>
   6. Now, to properly view the documentation from the help menu of gschem:
  </p>
  
  <p>
  Locate the executables of your browser and <acronym title="Portable Document Format">PDF</acronym> reader and create links from /usr/bin. Examples:
  </p>
  <pre class="code">$ ln -s &quot;c:\Program Files\Internet Explorer\iexplore.exe&quot; /usr/bin/iexplore
  $ ln -s &quot;c:\Program Files\Adobe\Acrobat 7.0\Reader\AcroRd32.exe&quot; /usr/bin/acroread</pre>
  
  <p>
   Try:
  </p>
  <pre class="code">$ iexplore
  ( Microsoft Internet Explorer appears )
  $ acroread
  ( Adobe Acrobat Reader appears )
  $ gschemdoc -m
  ( gEDA/gaf documentation appears )</pre>
  
  <p>
   7. Finally, before running gschem:
  </p>
  <pre class="code">$ startx</pre>
  
  <p>
   Have fun!
  </p>
  
  </div>
  <!-- SECTION [258-] --></div>
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_tool_suite_on-line_documentation" class="toc">gEDA Tool Suite on-line documentation</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#for_document_authors" class="toc">For document authors</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gschem_-_schematic_capture" class="toc">gschem - Schematic Capture</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gnetlist_-_netlister" class="toc">gnetlist - Netlister</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gsymcheck_-_symbol_checker" class="toc">gsymcheck - Symbol Checker</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#utils_-_geda_utilities" class="toc">utils - gEDA Utilities</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#examples" class="toc">Examples</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#attribute_file_format_details" class="toc">Attribute/File Format Details</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#spice" class="toc">SPICE</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#ngspice" class="toc">ngspice</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gnucap" class="toc">gnucap</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gspiceui" class="toc">gSpiceUI</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#pcb" class="toc">PCB</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gerbv" class="toc">gerbv</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#icarus_verilog" class="toc">Icarus Verilog</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#gtkwave" class="toc">GTKWave</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#wcalc" class="toc">Wcalc</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#mcalc" class="toc">mcalc</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#covered" class="toc">covered</a></span></div></li></ul>
  </div>
  </div>
  
  <h1><a name="geda_tool_suite_on-line_documentation" id="geda_tool_suite_on-line_documentation">gEDA Tool Suite on-line documentation</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-53] -->
  <h2><a name="for_document_authors" id="for_document_authors">For document authors</a></h2>
  <div class="level2">
  
  <p>
  New features are available for document authors:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="geda_syntax_features.html" class="wikilink1" title="geda:syntax_features">Syntax features</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_installed_plugins.html" class="wikilink1" title="geda:installed_plugins">Installed plugins</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_style_guide.html" class="wikilink1" title="geda:style_guide">Style Guide</a> &ndash; A work in progress, please contribute</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [54-262] -->
  <h2><a name="gschem_-_schematic_capture" id="gschem_-_schematic_capture">gschem - Schematic Capture</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_gschem_ug.html" class="wikilink1" title="geda:gschem_ug">gschem User's Guide</a> &ndash; In transition, please comment</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gschem_mp.html" class="wikilink1" title="geda:gschem_mp">gschem man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_scg.html" class="wikilink1" title="geda:scg">Symbol Creation Guide</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_hse_howto.html" class="wikilink1" title="geda:hse_howto">Hooks/Scheme Extension HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_kig_howto.html" class="wikilink1" title="geda:kig_howto">Keymapping in gschem HOWTO</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [263-558] -->
  <h2><a name="gnetlist_-_netlister" id="gnetlist_-_netlister">gnetlist - Netlister</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_gnetlist_ug.html" class="wikilink1" title="geda:gnetlist_ug">gnetlist User's Guide</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gnetlist_mp.html" class="wikilink1" title="geda:gnetlist_mp">gnetlist man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_sdb_howto.html" class="wikilink1" title="geda:sdb_howto">Spice netlisting (SDB) HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_na_howto.html" class="wikilink1" title="geda:na_howto">net= attribute mini-HOWTO</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_ssan.html" class="wikilink1" title="geda:ssan">Switcap Symbols and Netlister</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_sn_readme.html" class="wikilink1" title="geda:sn_readme">Switcap netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_fbabgapp.html" class="wikilink1" title="geda:fbabgapp">Forward/Backward Annotation Between gEDA and Pads PowerPCB</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_grcsan.html" class="wikilink1" title="geda:grcsan">gEDA RF Cascade Symbols and Netlister</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_bom_readme.html" class="wikilink1" title="geda:bom_readme">Bill of Material netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gschem2pcb_readme.html" class="wikilink1" title="geda:gschem2pcb_readme">gschem2pcb README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_verilog_netlister_readme.html" class="wikilink1" title="geda:verilog_netlister_readme">Verilog netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_vhdl_netlister_readme.html" class="wikilink1" title="geda:vhdl_netlister_readme">VHDL netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_vams_netlister_readme.html" class="wikilink1" title="geda:vams_netlister_readme">VAMS netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_systemc_netlister_readme.html" class="wikilink1" title="geda:systemc_netlister_readme">SystemC netlister README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_eagle_pcb_netlister_readme.html" class="wikilink1" title="geda:eagle_pcb_netlister_readme">Eagle PCB netlister README</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [559-1431] -->
  <h2><a name="gsymcheck_-_symbol_checker" id="gsymcheck_-_symbol_checker">gsymcheck - Symbol Checker</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_gsymcheck_mp.html" class="wikilink1" title="geda:gsymcheck_mp">gsymcheck man-page</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1432-1516] -->
  <h2><a name="utils_-_geda_utilities" id="utils_-_geda_utilities">utils - gEDA Utilities</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_gsch2pcb_readme.html" class="wikilink1" title="geda:gsch2pcb_readme">gsch2pcb (gschem to PCB) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">gsch2pcb tutorial</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_tragesym_readme.html" class="wikilink1" title="geda:tragesym_readme">tragesym (symbol generator) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/tragesym/tragesym.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/tragesym/tragesym.html";  rel="nofollow">tragesym Tutorial</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_olib_readme.html" class="wikilink1" title="geda:olib_readme">olib (OrCAD (TM) converter) README</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_grenum_mp.html" class="wikilink1" title="geda:grenum_mp">grenum man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gattrib_readme.html" class="wikilink1" title="geda:gattrib_readme">gattrib README</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1517-2025] -->
  <h2><a name="examples" id="examples">Examples</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_example_hsm.html" class="wikilink1" title="geda:example_hsm">Hierarchical SPICE model</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_example_usbjtag.html" class="wikilink1" title="geda:example_usbjtag">Example USB-based JTAG interface</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2026-2175] -->
  <h2><a name="attribute_file_format_details" id="attribute_file_format_details">Attribute/File Format Details</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_master_attributes_list.html" class="wikilink1" title="geda:master_attributes_list">Master Attributes List</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_file_format_spec.html" class="wikilink1" title="geda:file_format_spec">sym/sch File Format Specification</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2176-2341] -->
  <h1><a name="spice" id="spice">SPICE</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/papers/al-davis-dissertation.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/papers/al-davis-dissertation.pdf";  rel="nofollow">Implicit Mixed-Mode Simulation of VLSI Circuits</a> by Albert Tatum Davis (1991)<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> goes dead.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/SPICE/intro.html"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/intro.html";  rel="nofollow">Circuit Simulation using gEDA and SPICE - HOWTO</a> (<acronym title="HyperText Markup Language">HTML</acronym> version)<br/>
   by Stuart Brorson (20 December 2004).<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> is not the latest version.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/HOWTO/gEDA_Spice_HOWTO-20050103.pdf"; class="urlextern" title="http://www.brorson.com/gEDA/HOWTO/gEDA_Spice_HOWTO-20050103.pdf";  rel="nofollow">Circuit Simulation using gEDA and SPICE - HOWTO</a> (<acronym title="Portable Document Format">PDF</acronym> version)<br/>
   by Stuart Brorson ( 5 January 2005).</div>
  </li>
  </ul>
  
  <p>
   Testing:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="geda_csygas.html" class="wikilink1" title="geda:csygas">Circuit Simulation using gEDA and SPICE - HOWTO</a> &ndash; Done converting. Please comment on this conversion to a wiki-format.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2342-3091] -->
  <h1><a name="ngspice" id="ngspice">ngspice</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www-ti.informatik.uni-tuebingen.de/~bernauer/lehre/ti-1-0506/spice/ngspice.pdf"; class="urlextern" title="http://www-ti.informatik.uni-tuebingen.de/~bernauer/lehre/ti-1-0506/spice/ngspice.pdf";  rel="nofollow">NGSPICE User Manual</a> &ndash; describes ngspice-rework-17, Draft Version 0.2<br/>
   Please report if this <acronym title="Uniform Resource Locator">URL</acronym> is not the appropriated version, or if it goes dead.</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_ngspice_mp.html" class="wikilink1" title="geda:ngspice_mp">ngspice man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_ngnutmeg_mp.html" class="wikilink1" title="geda:ngnutmeg_mp">ngnutmeg man-page</a> &ndash; note</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_ngsconvert_mp.html" class="wikilink1" title="geda:ngsconvert_mp">ngsconvert man-page</a> &ndash; note</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3092-3514] -->
  <h1><a name="gnucap" id="gnucap">gnucap</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/gnucap-man.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/gnucap-man.pdf";  rel="nofollow">The Gnu Circuit Analysis Package Users manual</a> &ndash; January 21,2004 version</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/tools/gnucap/papers/gnucap-model-compiler.pdf"; class="urlextern" title="http://www.geda.seul.org/tools/gnucap/papers/gnucap-model-compiler.pdf";  rel="nofollow">The Gnucap Model Compiler</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3515-3775] -->
  <h1><a name="gspiceui" id="gspiceui">gSpiceUI</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/shared/gEDA-20060124/Documents/gSpiceUI/gSpiceUI.html"; class="urlextern" title="file:///shared/gEDA-20060124/Documents/gSpiceUI/gSpiceUI.html"  rel="nofollow">GNU Spice GUI</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3776-3883] -->
  <h1><a name="pcb" id="pcb">PCB</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_pcb_ug.html" class="wikilink2" title="geda:pcb_ug">Pcb-1.99q</a> &ndash; gEDA Suite version 20060123</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_footprint_creation.html" class="wikilink2" title="geda:footprint_creation">footprint_creation</a> &ndash; Stuart Brorson&rsquo;s document, is this the latest?</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_pcb_mp.html" class="wikilink1" title="geda:pcb_mp">PCB man-page</a></div>
  </li>
  <li class="level1"><div class="li"></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://pcb.sourceforge.net/manual.html"; class="urlextern" title="http://pcb.sourceforge.net/manual.html";  rel="nofollow">Recent development shapshot manuals and the current CVS version manual</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3884-4200] -->
  <h1><a name="gerbv" id="gerbv">gerbv</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_gerbv_mp.html" class="wikilink1" title="geda:gerbv_mp">gerbv man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gerbv_pnp_readme.html" class="wikilink1" title="geda:gerbv_pnp_readme">Searching for Parts and marking them on screen (in gerbv)</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4201-4346] -->
  <h1><a name="icarus_verilog" id="icarus_verilog">Icarus Verilog</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="geda_icarus_quick_start.html" class="wikilink1" title="geda:icarus_quick_start">Getting Started with Icarus Verilog</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_mp.html" class="wikilink1" title="geda:icarus_mp">Icarus Verilog compiler man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_vpi_mp.html" class="wikilink1" title="geda:icarus_vpi_mp">Compile front end for VPI modules man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_vvp_runtime.html" class="wikilink1" title="geda:icarus_vvp_runtime">Icarus Verilog vvp runtime engine man-page</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_readme.html" class="wikilink1" title="geda:icarus_readme">The Icarus Verilog Compilation System</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_igarus_fpga_lcg.html" class="wikilink1" title="geda:igarus_fpga_lcg">FPGA Loadable Code Generator for Icarus Verilog</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_xilinx_hints.html" class="wikilink1" title="geda:icarus_xilinx_hints">Xilinx Hints</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_xnf.html" class="wikilink1" title="geda:icarus_xnf">Xilinx Netlist Format</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_ieee1364.html" class="wikilink1" title="geda:icarus_ieee1364">Icarus Verilog vs. IEEE1364</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_anc.html" class="wikilink1" title="geda:icarus_anc">Icarus Attribute Naming Conventions</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_extensions.html" class="wikilink1" title="geda:icarus_extensions">Icarus Verilog Extensions</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_glossary.html" class="wikilink1" title="geda:icarus_glossary">Icarus Verilog Glossary</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_opcodes.html" class="wikilink1" title="geda:icarus_opcodes">Executable Instruction Opcodes</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_vpi_within_vvp.html" class="wikilink1" title="geda:icarus_vpi_within_vvp">VPI_within_VVP</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_icarus_vvp_simulation.html" class="wikilink1" title="geda:icarus_vvp_simulation">VVP Simulation Engine</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4347-5272] -->
  <h1><a name="gtkwave" id="gtkwave">GTKWave</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://home.nc.rr.com/gtkwave/"; class="urlextern" title="http://home.nc.rr.com/gtkwave/";  rel="nofollow">Welcome to GTKWave</a> &ndash; Now for version 3.0 (the promoted version 1.3)</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_mp.html" class="wikilink1" title="geda:gtkwave_mp">Visualization tool for VCD, LXT, and VZT files (gtkwave)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_lxt2miner_mp.html" class="wikilink1" title="geda:gtkwave_lxt2miner_mp">Data mining of LXT2 files (lxt2miner)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_lxt2vcd_mp.html" class="wikilink1" title="geda:gtkwave_lxt2vcd_mp">Coverts LXT2 files to VCD (lxt2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_mvl2lxt_mp.html" class="wikilink1" title="geda:gtkwave_mvl2lxt_mp">Coverts MVLSIM AET files to LXT (mvl2lxt)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_mvl2vcd_mp.html" class="wikilink1" title="geda:gtkwave_mvl2vcd_mp">Coverts MVLSIM AET files to VCD (mvl2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_tex2vcd_mp.html" class="wikilink1" title="geda:gtkwave_tex2vcd_mp">Coverts TEXSIM AET files to VCD (tex2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_tla2vcd_mp.html" class="wikilink1" title="geda:gtkwave_tla2vcd_mp">Converts TLA to VCD or LST files (tla2vcd)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_vcd2lxt_mp.html" class="wikilink1" title="geda:gtkwave_vcd2lxt_mp">Converts VCD files to interlaced or linear LXT files (vcd2lxt)</a></div>
  </li>
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   (vcd2vzt)</a></div>
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  </li>
  <li class="level1"><div class="li"> <a href="geda_gtkwave_vztminer_mp.html" class="wikilink1" title="geda:gtkwave_vztminer_mp">Data mining of VZT files (vztminer)</a></div>
  </li>
  </ul>
  
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  <!-- SECTION [5273-6304] -->
  <h1><a name="wcalc" id="wcalc">Wcalc</a></h1>
  <div class="level1">
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  <!-- SECTION [6305-6451] -->
  <h1><a name="mcalc" id="mcalc">mcalc</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://mcalc.sourceforge.net/"; class="urlextern" title="http://mcalc.sourceforge.net/";  rel="nofollow">Microstrip Analysis/Synthesis Calculator</a> &ndash; latest documentation from sourceforge</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_mcalc_readme.html" class="wikilink1" title="geda:mcalc_readme">mcalc README</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6452-6631] -->
  <h1><a name="covered" id="covered">covered</a></h1>
  <div class="level1">
  <ul>
  <li class="level1"><div class="li"> <a href="http://covered.sourceforge.net/user/index.html"; class="urlextern" title="http://covered.sourceforge.net/user/index.html";  rel="nofollow">covered User Manual</a> &ndash; link to latest covered documentation on sourceforge</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_covered_rv.html" class="wikilink2" title="geda:covered_rv">covered Report Viewer</a> &ndash; available in the Help menu of the <acronym title="Graphical User Interface">GUI</acronym> report utility</div>
  </li>
  <li class="level1"><div class="li"> <a href="geda_covered_mp.html" class="wikilink1" title="geda:covered_mp">covered man-page</a></div>
  </li>
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  1.1                  eda/geda/gaf/docs/wiki/geda_eagle_pcb_netlister_readme.html
  
  Index: geda_eagle_pcb_netlister_readme.html
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  <h1><a name="eagle_pcb_netlister_readme" id="eagle_pcb_netlister_readme">Eagle PCB netlister README</a></h1>
  <div class="level1">
  <pre class="code">Basic information about the Eagle PCB backend and sch2eaglepos.sh
  
  gnet-eagle.scm  
  
  The script uses the component's package, footprint, value, and (if no
  value) device attributes, as well as the netlist, to generate an Eagle
  script that will add and connect all components.  It also introduces a
  &quot;lib&quot; attribute, which specifies the Eagle library where the footprint
  can be found...if a &quot;lib&quot; attribute is not set for a component, then
  the library defaults to &quot;smd-ipc&quot; (the default Eagle surface mount library).
  
  sch2eaglepos.sh
  
  I am also including a simple shell script that I wrote which has saved
  me hours by extracting the relative locations of the parts from a
  gschem schematic, and generating an Eagle script to place the
  components in the same relative locations on the layout.  By default
  all packages are piled on top of each other, and with a large design
  it takes a long time to sort out which cap bypasses which IC, etc.
  
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_example_hsm.html
  
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  <h1><a name="hierarchical_spice_model" id="hierarchical_spice_model">Hierarchical SPICE model</a></h1>
  <div class="level1">
  
  <p>
  If you installed the gEDA Tool Suite from the distribution CD-ROM, then you should have this example of a hierarchical analog RF SPICE model in the:<br/>
   <strong><code>{source_install_path}geda-sources/gedagaf/geda-examples-20060123/RF_Amp</code></strong> <br/>
   directory.
  </p>
  <pre class="code">This README created 3.31.2003
  
  ---------------------  Contents of directories  -----------------------
  
  This directory holds the schematics and associated materials for a
  SPICE model of Agilent's MSA-2643 bipolar amp.  The model was obtained
  from Agilent's datasheet 5980-2396E.  The directory structure is as
  follows:
  
  RF_Amp (base directory)
  
  MSA-2643.sch -- schematic of stuff inside device package (as shown in
  p. 7 of datasheet.  Note that I have not included the transmission 
  lines in this schematic because no value of Z was included in the data
  sheet.   (Yes, it's probably 50 ohms, but including them was a
  sideshow compared to my main intent: build a hierarchical model of an
  RF circuit.)
  MSA-2643.cir -- netlisted circuit ready for SPICE simulation.
  
  Q1.sch -- schematic model of Q1 MSA-26 transistor shown on p. 8 of datasheet.
  Q1.cir -- netlisted circuit holding .SUBCKT model of Q1.
  
  Q2.sch -- schematic model of Q2 MSA-26 transistor shown on p. 8 of datasheet.
  Q2.cir -- netlisted circuit holding .SUBCKT model of Q2.
  
  README -- this file.
  
  Simulation.cmd -- a file holding SPICE analysis commands which is read
  at simulation time by the SPICE simulator.  
  
  5980-2396E.pdf -- Agilent datasheet about the MSA-2643.
  
  
  ./model/
  
  BJTM1_Q1.mod -- text-based SPICE model of BJT1 used in Q1 .SUBCKT
  DiodeM1_Q1.mod -- text-based SPICE model of diode M1 used in Q1 .SUBCKT
  DiodeM2_Q1.mod -- SPICE model of diode M2 used in Q1 .SUBCKT
  DiodeM3_Q1.mod -- SPICE model of diode M3 used in Q1 .SUBCKT
  (similar files for Q2 models. . . .)
  These models were obtained from parameters give in p. 8 of the datasheet.
  
  ./sym/
  
  BJT_Model.sym
  spice-subcircuit-IO-1.sym
  spice-subcircuit-LL-1.sym
  Q_Model.sym -- symbol pointing to lower level models placed on upper
  level schematic.
  
  ------------  Usage of hierarchical spice models ---------------------
  This project exemplifies construction of a hierarchical SPICE
  simulation using gEDA.  The project is built in the following way:
  
  1.  Use a text editor to create .mod files containing SPICE models of
  the transistors and diodes on p. 8 of the datasheet.  
  
  2.  Create Q1 and Q2 transistor model schematics using gschem.  Place
  the .SUBCKT SPICE block on the schematic to alert the netlister that
  the schematic is a lower level .SUBCKT for incorporation into other
  schematics.  Place spice-IO pads on the schematic to instantiate the
  IOs.  Make sure to number the spice-IO pads in the same order as you
  wish them to appear in the .SUBCKT line in the .cir.
  
  3.  Generate the .SUBCKT netlist by saying:
  
  gnetlist -g spice-sdb -o Q1.cir Q1.sch
  gnetlist -g spice-sdb -o Q2.cir Q2.sch
  
  4.  Create a symbol for Q1.cir and Q2.cir which will be dropped onto
  the higher lever schematic.  Name the symbol Q_Model.sym.  Set the
  symbol &quot;DEVICE&quot; attribute = NPN_TRANSISTOR_subcircuit.  This causes
  the netlister to use &quot;write-default-component&quot; to write out the SPICE
  line for the component.  Make sure that the &quot;REFDES&quot; attribute is X?
  and not Q? -- this enables the .SUBCKT file to be attached to the
  device. 
  
  5.  Create the higher layer schematic MSA-2643.sch.  Place
  two copies of Q_Model.sym onto the schematic, corresponding to Q1 and
  Q2.  Make Q1 point to its model by setting the following attributes: 
  
  model-name: Q1_MSA26F
  file: Q1.cir
  
  Do the same for Q2.
  
  6.  Create the rest of the higher layer schematic the usual way.  Make
  sure to place a spice-include block on the schematic and point it to
  &quot;Simulation.cmd&quot;.  Place any analysis commands (e.g. .DC, .AC, .TRAN,
  etc.) into the file &quot;Simulation.cmd&quot;.
  
  7.  Netlist the higher layer design:
  
  gnetlist -g spice-sdb -o MSA-2643.cir MSA-2643.sch
  
  8.  The circuit may be simulated by any desired SPICE simulation
  and analysis package, e.g. LTSpice.
  
  --------------------  Contact  ----------------------------
  Documentation and other materials relevant to SPICE simulation under
  gEDA lives at http://www.brorson.com/gEDA/SPICE
  
  For inquiries or bug reports, please contact me:
  
  Stuart Brorson
  mailto:sdb@xxxxxxxxxx
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_example_usbjtag.html
  
  Index: geda_example_usbjtag.html
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  <h1><a name="example_usb-based_jtag_interface" id="example_usb-based_jtag_interface">Example USB-based JTAG interface</a></h1>
  <div class="level1">
  
  <p>
  If you installed the gEDA Tool Suite from the distribution CD-ROM, then you should have this example of a USB-based JTAG interface in the:<br/>
   <strong><code>{source-code_installation_path}geda-sources/gedagaf/geda-examples-20060123/gTAG</code></strong> <br/>
   directory.
  </p>
  <pre class="code">		gTAG - 	USB to JTAG interface
  		============================
  
  This is the README file for the schematic of gTAG.
  
  Short description
  -----------------
  gTAG is an interface to connect your USB port of computer to talk
  to your circuits which talks JTAG.
  
  Copyright
  ---------
  These schematics is (C) by Stefan Petersen (spe@xxxxxxxxxxxxxx) and 
  released under GPL (see the attached file COPYING). GPL is mainly 
  written for software, ie intellectual property in electronic form. 
  By making this schematic an intellectual property in electronic
  form gTAG schematics can be covered by GPL.
  
  How?
  ----
  These schematics are made with gschem and netlists are then generated
  with gnetlist. Both gschem and gnetlist are part of gEDA 
  (http://www.geda.seul.org/).
  
  Files
  -----
  The distribution of the schematics of gTAG should consist of:
  * README - this file.
  * COPYING - GPL copyright notice.
  * crdist.sh - shell script used to generate the tar.gz.
  * ChangeLog - tries to scribble down what has changed between versions.
  * Four component symbols:
    - 7414-1.sym - Original 7414 from gschem without power attributes.
    - max882.sym - 5-to-3.3 V converter.
    - cy7c64603-52nc.sym - USB microcontroller from Cypress.
    - sn75240pw.sym - Surge supressor for USB
    - copyleft.sym - Symbol with GPL text for all schematics.
  * Five schematics with four symbols:
    - gTAG.sch.sch - Toplevel schematic for gTAG
    - gTAG-jtagio.[sym/sch]
    - gTAG-ucont.[sym/sch]
    - gTAG-consio.[sym/sch]
    - gTAG-psu.[sym/sch]
  * gEDA rc-files for this project:
    - commonrc - contains common declarations for both gschem and gnetlist
    - gnetlistrc - gnetlist specific and and calls commonrc
    - gschemrc   - gschem specific and and calls commonrc
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_faq-attribs.html
  
  Index: geda_faq-attribs.html
  ===================================================================
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  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#bom_generation" class="toc">BOM generation</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#i_have_created_a_new_design._how_do_i_create_a_bom" class="toc">I have created a new design. How do I create a BOM?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#drcs" class="toc">DRCs</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_check_my_schematics" class="toc">How do I check my schematics?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_see_the_drc_output_in_the_screen_without_writing_to_a_file" class="toc">How do I see the DRC output in the screen, without writing to a file?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_want_to_disable_some_of_the_schematic_drc_checks._how_can_i_do_it" class="toc">I want to disable some of the schematic DRC checks. How can I do it?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#can_i_include_the_drc_checking_into_a_makefile_and_stop_when_errors_or_warnings_are_found" class="toc">Can I include the DRC checking into a Makefile and stop when errors or warnings are found?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#there_are_some_warnings_in_my_design_i_m_aware_of._can_i_ignore_the_warnings_in_the_return_value" class="toc">There are some warnings in my design I'm aware of. Can I ignore the warnings in the return value?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#attribute_management" class="toc">Attribute management</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#help_my_design_has_hundreds_of_components_and_it_s_a_pain_to_use_gschem_to_attach_all_my_attributes" class="toc">Help! My design has hundreds of components, and it's a pain to use gschem to attach all my attributes!</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_know_what_footprint_name_to_use_for_layout_using_pcb" class="toc">How do I know what footprint name to use for layout using PCB?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="bom_generation" id="bom_generation">BOM generation</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-30] -->
  <h2><a name="i_have_created_a_new_design._how_do_i_create_a_bom" id="i_have_created_a_new_design._how_do_i_create_a_bom">I have created a new design. How do I create a BOM?</a></h2>
  <div class="level2">
  
  <p>
  There are as many ways to export a BOM from your design as there are gEDA developers. Indeed, there are five or six different backends for gnetlist which enable you to export a BOM. Therefore, itâ??s easy for the newbie to be confused about which approach to use. A good, simple, and reasonably complete method is this:
  </p>
  <ul>
  <li class="level1"><div class="li"> Create a file called â??attribsâ?? in your project directory. In this file, place each attrib whose value you wish to export on a separate line. Hereâ??s an example:<pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">value
  Mfr
  Mfr_PN
  Vendor
  Vendor_PN</font></pre></div>
  </li>
  <li class="level1"><div class="li"> Netlist your design using the following command:<br/>
   <br/>
   <code>gnetlist -v -g bom2 -o MyDesign.bom MyDesign.sch</code> <br/>
   <br/>
   Note that the <strong><code>-v</code></strong> flag will provide a verbose spew telling you what is going in gnetlist while it is running. This can be useful if you need to diagnose a problem with netlisting.</div>
  </li>
  <li class="level1"><div class="li"> With this command, gnetlist will dump a BOM into the file â??MyDesign.bomâ??. The BOM items will be separated using a â??:â?? (colon) character. You may then read this file into any spreadsheet program. Make sure to import the BOM as a .csv file, and specify the â??:â?? character as the item separator.</div>
  </li>
  </ul>
  
  <p>
   Many other methods to create BOMs exist. Perhaps other geda-users will post their favorite methods here?!?!?
  </p>
  
  </div>
  <!-- SECTION [31-1355] -->
  <h1><a name="drcs" id="drcs">DRCs</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1356-1374] -->
  <h2><a name="how_do_i_check_my_schematics" id="how_do_i_check_my_schematics">How do I check my schematics?</a></h2>
  <div class="level2">
  
  <p>
  You can check your schematics using the drc2 gnetlistâ??s backend. It will check your schematics for some common errors, like duplicate references, unconnected pins, unused slots and more.
  </p>
  
  <p>
  Run the drc2 backend with the following command: 
  </p>
  <pre class="code">gnetlist -g drc2 -o MyDesign.drc MyDesign.sch</pre>
  
  <p>
  With this command, the DRC output is written into the file â??MyDesign.drcâ??. You can then view this file with a text editor and see the DRC warnings and errors.
  </p>
  
  </div>
  <!-- SECTION [1375-1879] -->
  <h2><a name="how_do_i_see_the_drc_output_in_the_screen_without_writing_to_a_file" id="how_do_i_see_the_drc_output_in_the_screen_without_writing_to_a_file">How do I see the DRC output in the screen, without writing to a file?</a></h2>
  <div class="level2">
  
  <p>
  Run the drc2 backend with the following command: 
  </p>
  <pre class="code">gnetlist -g drc2 -o - MyDesign.sch</pre>
  
  <p>
  This way, you will see the DRC output directly in your screen.
  </p>
  
  </div>
  <!-- SECTION [1880-2123] -->
  <h2><a name="i_want_to_disable_some_of_the_schematic_drc_checks._how_can_i_do_it" id="i_want_to_disable_some_of_the_schematic_drc_checks._how_can_i_do_it">I want to disable some of the schematic DRC checks. How can I do it?</a></h2>
  <div class="level2">
  
  <p>
  The drc2 backend is highly configurable. You have to put some special commands into a file and use the â??-lâ?? option of gnetlist with it.
  </p>
  
  <p>
  The most common commands are:
  </p>
  <ul>
  <li class="level1"><div class="li"> (define dont-check-non-numbered-parts 1) ;; Disable the non-numbered parts check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-duplicated-references 1) ;; Disable the duplicate references check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-one-connection-nets 1) ;; Disable the check for nets with only one connection.</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-pintypes-of-nets 1) ;; Disable the pintype check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-not-driven-nets 1) ;; Disable the driven net check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-unconnected-pins 1) ;; Disable the unconnected pins check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-duplicated-slots 1) ;; Disable the duplicated slots check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-unused-slots 1) ;; Disable the unused slots check</div>
  </li>
  <li class="level1"><div class="li"> (define dont-check-slots 1) ;; Disable slot number check</div>
  </li>
  <li class="level1"><div class="li"> (define action-unused-slots #\w) ;; Output an unused slots as a warning</div>
  </li>
  <li class="level1"><div class="li"> (define action-unused-slots #\e) ;; Output an unused slots as an error</div>
  </li>
  <li class="level1"><div class="li"> (define action-unused-slots #\c) ;; An unused slot is OK.</div>
  </li>
  <li class="level1"><div class="li"> (define case_insensitive 1) ;; Do all checks case insensitive</div>
  </li>
  </ul>
  
  <p>
   There are some other advanced commands, to modify the DRC matrix and the pintype which can drive a net. See the backend file â??gnet-drc2.scmâ?? with a text editor. At the beginning there is the available documentation.
  </p>
  
  <p>
  Copy the above lines you want into a file (for example â??drc_rules.txtâ??), one per line, and run the drc checker: 
  </p>
  <pre class="code">gnetlist -g drc2 -l drc_rules.txt -o MyDesign.drc MyDesign.sch</pre>
  
  <p>
  With this command, the DRC output is written into the file â??MyDesign.drcâ??. You can then view this file with a text editor and see the DRC warnings and errors.
  </p>
  
  </div>
  <!-- SECTION [2124-3952] -->
  <h2><a name="can_i_include_the_drc_checking_into_a_makefile_and_stop_when_errors_or_warnings_are_found" id="can_i_include_the_drc_checking_into_a_makefile_and_stop_when_errors_or_warnings_are_found">Can I include the DRC checking into a Makefile and stop when errors or warnings are found?</a></h2>
  <div class="level2">
  
  <p>
  Yes. The drc2 backend will return an error if there are errors or warnings, so you can add the following to your Makefile: 
  </p>
  <pre class="code">$(objects).drc : $(objects).sch
            gnetlist -g drc2 $(objects).sch -o $(objects).drc</pre>
  
  <p>
  If you are going to simulate your design, then you can add the following to your Makefile: 
  </p>
  <pre class="code">$(objects).cir : $(objects).sch $(objects).drc
            grep -v ERROR $(objects).drc &gt;/dev/null 2&gt;&amp;1
            gnetlist -g spice-sdb $(objects).sch  -o $(objects).cir</pre>
  
  <p>
  If not, please use the above example and adapt it to your own workflow.
  </p>
  
  </div>
  <!-- SECTION [3953-4630] -->
  <h2><a name="there_are_some_warnings_in_my_design_i_m_aware_of._can_i_ignore_the_warnings_in_the_return_value" id="there_are_some_warnings_in_my_design_i_m_aware_of._can_i_ignore_the_warnings_in_the_return_value">There are some warnings in my design I'm aware of. Can I ignore the warnings in the return value?</a></h2>
  <div class="level2">
  
  <p>
  Use the â??-O ignore-warnings-in-return-valueâ?? option: 
  </p>
  <pre class="code">gnetlist -g drc2 -o - MyDesign.sch -O ignore-warnings-in-return-value</pre>
  
  <p>
  Do this with caution! You will be missing all the warnings!
  </p>
  
  </div>
  <!-- SECTION [4631-4942] -->
  <h1><a name="attribute_management" id="attribute_management">Attribute management</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [4943-4978] -->
  <h2><a name="help_my_design_has_hundreds_of_components_and_it_s_a_pain_to_use_gschem_to_attach_all_my_attributes" id="help_my_design_has_hundreds_of_components_and_it_s_a_pain_to_use_gschem_to_attach_all_my_attributes">Help! My design has hundreds of components, and it's a pain to use gschem to attach all my attributes!</a></h2>
  <div class="level2">
  
  <p>
  The answer here is the gEDA/gaf utility â??gattribâ??. Gattrib is an attribute editor for gEDA. It reads your .sch file(s) and creates a spreadsheet showing all components, nets, and pins in rows, with the associated attributes listed in the columns. Gattrib allows you to add, modify, or delete attributes outside of gschem, and then save the .sch files back out. Hereâ??s a screenshot:
  </p>
  
  <p>
  <a href="_detail/geda_faq_attrib.html" class="media" title="geda:faq_attrib.jpg"><img src="_media/geda_faq_attrib.jpg" class="media" title="faq_attrib.jpg" alt="faq_attrib.jpg" /></a>
  </p>
  
  <p>
  Note that gattrib is the gEDA Projectâ??s current answer to the question of heavy symbols. That is, rather than putting all attributes (such as SPICE model files, footprint names, manufacturer part nos and the like), you are encouraged to put this information into your schematic using gattrib, where it is visible and easily manipulable with gattrib.
  </p>
  
  <p>
  When using gattrib, make sure you exit gschem first. Gattrib and gschem both save your work into the same file, so you should have only one program running at a time to avoid conflicts. There is no lockfile mechanism in gEDA/gaf (yet), so itâ??s your responsibility to avoid conflicts.
  </p>
  
  </div>
  <!-- SECTION [4979-6148] -->
  <h2><a name="how_do_i_know_what_footprint_name_to_use_for_layout_using_pcb" id="how_do_i_know_what_footprint_name_to_use_for_layout_using_pcb">How do I know what footprint name to use for layout using PCB?</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_pcb_tips.html" class="wikilink1" title="geda:pcb_tips">Answered here</a>. 
  </p>
  
  </div>
  <!-- SECTION [6149-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_faq-gnetlist.html
  
  Index: geda_faq-gnetlist.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#gnetlist_build_run-time_problems" class="toc">Gnetlist build/run-time problems</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#the_gnetlist_bom_backend_does_not_work._what_is_wrong" class="toc">The gnetlist bom backend does not work. What is wrong?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#some_gnetlist_backends_overflow_the_stack._how_do_i_solve_this" class="toc">Some gnetlist backends overflow the stack. How do I solve this?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gnetlist_has_created_a_netlist_with_duplicate_pins" class="toc">gnetlist has created a netlist with duplicate pins!?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="gnetlist_build_run-time_problems" id="gnetlist_build_run-time_problems">Gnetlist build/run-time problems</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-47] -->
  <h2><a name="the_gnetlist_bom_backend_does_not_work._what_is_wrong" id="the_gnetlist_bom_backend_does_not_work._what_is_wrong">The gnetlist bom backend does not work. What is wrong?</a></h2>
  <div class="level2">
  
  <p>
  If when running gnetlist like this: 
  </p>
  <pre class="code">gnetlist -g bom filename.sch</pre>
  
  <p>
  and gnetlist outputs an error message like: 
  </p>
  <pre class="code">Loading schematic [filename.sch]
  ERROR: In procedure open-file:
  ERROR: No such file or directory: â??attribsâ??</pre>
  
  <p>
  then you need to create a file called â??attribsâ?? in the current directory which contains the attributes which you want inside the bom file. An example of this file would be: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">refdes
  device
  value</font></pre>
  </p>
  
  </div>
  <!-- SECTION [48-576] -->
  <h2><a name="some_gnetlist_backends_overflow_the_stack._how_do_i_solve_this" id="some_gnetlist_backends_overflow_the_stack._how_do_i_solve_this">Some gnetlist backends overflow the stack. How do I solve this?</a></h2>
  <div class="level2">
  
  <p>
  If you get an error message like: 
  </p>
  <pre class="code">ERROR: Stack overflow</pre>
  
  <p>
  when running certain larger sized schematics through some of the backends, then add the following to a <strong><code>~/.gEDA/gnetlistrc</code></strong> or a local <strong><code>gnetlistrc</code></strong> (in the current working directory): 
  </p>
  <pre class="code">(debug-options (list 'stack 200000))
  (eval-options (list 'stack 200000))</pre>
  
  <p>
  If this does not work, then edit the appropriate backend (usually named: gnet-backend_name.scm) and put the above lines at the top of this file. The gnetlist backends can be found in <strong><code>${prefix}/share/gEDA/scheme</code></strong>. Also send an e-mail to geda-dev reminding the developers to fix this. Remember, you must subscribe to geda-dev before you post to the geda-dev e-mail list.
  </p>
  
  </div>
  <!-- SECTION [577-1382] -->
  <h2><a name="gnetlist_has_created_a_netlist_with_duplicate_pins" id="gnetlist_has_created_a_netlist_with_duplicate_pins">gnetlist has created a netlist with duplicate pins!?</a></h2>
  <div class="level2">
  
  <p>
  There has been at least one report of the following message coming from PCB after loading up a netlist created by gnetlist: 
  </p>
  <pre class="code">28: Error! Element R117 pin 2 appears multiple times in the netlist file.
  29: Error! Element C167 pin 2 appears multiple times in the netlist file.</pre>
  
  <p>
  What has happened is gnetlist (really libgeda) created two nets instead of one. This happens when you draw two nets that cross each other and a pin connecting to the intersection of the two crossing nets. Note the cross nets are not connected together. A schematic which demonstrates this looks like this:
  </p>
  
  <p>
  <a href="_detail/geda_ambiguous1.html" class="media" title="geda:ambiguous1.png"><img src="_media/geda_ambiguous1.png" class="media" alt="" /></a>
  </p>
  
  <p>
  The developers are debating whether or not this is a bug in gnetlist, but for now make sure your net connections, especially those that involve pins connecting to the middle of other nets, are explicitly drawn. Here is how the above connection should be drawn to netlist properly:
  </p>
  
  <p>
  <a href="_detail/geda_ambiguous1_fixed.html" class="media" title="geda:ambiguous1_fixed.png"><img src="_media/geda_ambiguous1_fixed.png" class="media" alt="" /></a> 
  </p>
  
  </div>
  <!-- SECTION [1383-] --></div>
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  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_faq-gsch2pcb.html
  
  Index: geda_faq-gsch2pcb.html
  ===================================================================
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  <div class="dokuwiki export">
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#gsch2pcb" class="toc">gsch2pcb</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#where_is_the_gsch2pcb_tutorial" class="toc">Where is the gsch2pcb tutorial?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#where_can_i_download_gsch2pcb" class="toc">Where can I download gsch2pcb?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gsch2pcb_can_t_find_some_of_my_footprints_or_errors_out._what_can_i_do_to_diagnose_my_problem" class="toc">gsch2pcb can't find some of my footprints, or errors out. What can I do to diagnose my problem?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="gsch2pcb" id="gsch2pcb">gsch2pcb</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-24] -->
  <h2><a name="where_is_the_gsch2pcb_tutorial" id="where_is_the_gsch2pcb_tutorial">Where is the gsch2pcb tutorial?</a></h2>
  <div class="level2">
  
  <p>
  Currently, the best information about this is contained in Bill Wilsonâ??s <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">outstanding tutorial</a>. <br/>
   <span class="hilited">This page will grow later to contain answers to FAQs posted on the geda-user list.</span>
  </p>
  
  </div>
  <!-- SECTION [25-327] -->
  <h2><a name="where_can_i_download_gsch2pcb" id="where_can_i_download_gsch2pcb">Where can I download gsch2pcb?</a></h2>
  <div class="level2">
  
  <p>
  gsch2pcb is part of gEDA/gaf, in the utils. It is normally installed by default (along with everything else) if you install the entirety of gEDA/gaf. If you donâ??t have it installed on your machine for some reason you can either download the utils tarball from:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">http://geda.seul.org/download.html</a></div>
  </li>
  </ul>
  
  <p>
   or grab it directly from <acronym title="Concurrent Versions System">CVS</acronym> at:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://cvs.seul.org/viewcvs/viewcvs.cgi/eda/geda/gaf/utils/src/"; class="urlextern" title="http://cvs.seul.org/viewcvs/viewcvs.cgi/eda/geda/gaf/utils/src/";  rel="nofollow">http://cvs.seul.org/viewcvs/viewcvs.cgi/eda/geda/gaf/utils/src/</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [328-783] -->
  <h2><a name="gsch2pcb_can_t_find_some_of_my_footprints_or_errors_out._what_can_i_do_to_diagnose_my_problem" id="gsch2pcb_can_t_find_some_of_my_footprints_or_errors_out._what_can_i_do_to_diagnose_my_problem">gsch2pcb can't find some of my footprints, or errors out. What can I do to diagnose my problem?</a></h2>
  <div class="level2">
  
  <p>
  Try running gsch2pcb in double verbose mode: â??gsch2pcb -v -vâ??. This will produce lots of spew telling you where gsch2pcb is looking while it tries to find footprints. It will also tell you where it does find the footprints it uses. 
  </p>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_faq-gschem.html
  
  Index: geda_faq-gschem.html
  ===================================================================
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  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#gschem_installation_run-time_problems" class="toc">Gschem installation/run-time problems</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#gschem_segfaults_when_i_delete_components_on_fc5_and_other_linux_distributions_is_there_a_work-around" class="toc">Gschem segfaults when I delete components on FC5 (and other Linux distributions)! Is there a work-around?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#after_installation_gschem_does_not_work_what_could_be_wrong" class="toc">After installation gschem does not work!? What could be wrong?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#add_components_offers_no_symbols_what_can_i_do_about_it" class="toc">&quot;Add Components&quot; offers no symbols! What can I do about it?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#gschem_usage" class="toc">Gschem usage</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_move_a_component" class="toc">How do I move a component?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_the_size_of_the_text_on_a_symbol" class="toc">How do I change the size of the text on a symbol?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#is_there_an_explicit_no_connect_symbol_that_i_can_should_place_in_the_schematic_to_prevent_gnetlist_from_thinking_i_ve_forgotten_a_connection" class="toc">Is there an explicit &quot;no connect&quot; symbol that I can/should place in the schematic to prevent gnetlist from thinking I've forgotten a connection?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_print_schematics_from_the_command_line" class="toc">How do I print schematics from the command line?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_get_color_postscript_png_output" class="toc">How can I get color postscript/PNG output?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_get_black_and_white_postscript_png_output" class="toc">How can I get black and white postscript/PNG output?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_insert_schematics_into_my_latex_document" class="toc">How can I insert schematics into my LaTex document?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_split_postscript_output_over_multiple_pages" class="toc">How can I split postscript output over multiple pages?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_unlock_a_locked_component" class="toc">How do I unlock a locked component</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#gschem_configuration_customization" class="toc">Gschem configuration/customization</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_change_the_default_size_of_floating_text" class="toc">How can I change the default size of floating text?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_have_a_different_background_color_other_than_black" class="toc">How can I have a different background color other than black?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_get_refdes_automatically_numbered_when_i_draw_a_schematic" class="toc">How can I get refdes automatically numbered when I draw a schematic?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_are_the_mouse_bindings_in_gschem" class="toc">What are the mouse bindings in gschem?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#information_on_gschem_symbols" class="toc">Information on gschem symbols</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#what_s_this_business_about_heavy_vs._light_symbols" class="toc">What's this business about heavy vs. light symbols?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_am_using_a_symbol_out_of_the_library._how_come_it_s_not_aligned_to_the_grid" class="toc">I am using a symbol out of the library.  How come it's not aligned to the grid?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_promote_an_invisible_symbol_attribute_into_the_schematic" class="toc">How do I promote an invisible symbol attribute into the schematic?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_should_i_do_about_power_pins_on_my_symbolsmake_them_visible_explicit_or_invisible_implicit" class="toc">What should I do about power pins on my symbols: Make them visible (explicit) or invisible (implicit)?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#is_there_a_specification_or_manual_for_creating_gschem_symbols_where_is_it" class="toc">Is there a specification or manual for creating gschem symbols? Where is it?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="gschem_installation_run-time_problems" id="gschem_installation_run-time_problems">Gschem installation/run-time problems</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-53] -->
  <h2><a name="gschem_segfaults_when_i_delete_components_on_fc5_and_other_linux_distributions_is_there_a_work-around" id="gschem_segfaults_when_i_delete_components_on_fc5_and_other_linux_distributions_is_there_a_work-around">Gschem segfaults when I delete components on FC5 (and other Linux distributions)! Is there a work-around?</a></h2>
  <div class="level2">
  
  <p>
  This bug seems to have appeared for users of Fedora Core 5 (and other linux distributions that use glib 2.10.x). The bug has been fixed by the developers and the bug fix will appear in the next version of gEDA/gaf. 
  </p>
  
  <p>
  In the mean time, you can work around this bug by setting the environment variable G_SLICE to â??always-mallocâ??.  Specifically, before you run gschem, do this:
  </p>
  
  <p>
  bash: 
  </p>
  <pre class="code">export G_SLICE=always-malloc</pre>
  
  <p>
  csh: 
  </p>
  <pre class="code">setenv G_SLICE always-malloc</pre>
  
  </div>
  <!-- SECTION [54-648] -->
  <h2><a name="after_installation_gschem_does_not_work_what_could_be_wrong" id="after_installation_gschem_does_not_work_what_could_be_wrong">After installation gschem does not work!? What could be wrong?</a></h2>
  <div class="level2">
  
  <p>
  If you run gschem and you get a window without a menu bar, no colors, and the program terminates when you press a key with the following message: 
  </p>
  <pre class="code">ERROR: Unbound variable: current-keymap</pre>
  
  <p>
  Or you get errors like this: 
  </p>
  <pre class="code">Gtk-CRITICAL : file gtkpixmap.c: line 97 (gtk_pixmap_new): assertion `val != NULLâ?? failed.
  Gtk-CRITICAL : file gtkpixmap.c: line 97 (gtk_pixmap_new): assertion `val != NULLâ?? failed.
  Tried to get an invalid color: 0
  Tried to get an invalid color: 7
  Tried to get an invalid color: 0
  Tried to get an invalid color: 7</pre>
  
  <p>
  then gschem is not finding an rc file. There are two required rc files. The first is <strong><code>system-gschemrc</code></strong> and the second is <strong><code>system-commonrc</code></strong>.
  </p>
  <ul>
  <li class="level1"><div class="li"> The system-gschemrc rc file should be installed when you install gschem and typically resides in <strong><code>${prefix}/share/gEDA/system-gschemrc</code></strong>. <strong><code>${prefix}</code></strong> is where you installed gschem (usually <strong><code>/usr</code></strong> or <strong><code>/usr/local</code></strong> or <strong><code>$HOME/geda</code></strong>). This file can also be installed in /etc/gEDA (the .debs packages do this).</div>
  </li>
  <li class="level1"><div class="li"> The system-commonrc rc file should be installed when you install the symbol library for gEDA/gaf. It resides in <strong><code>${prefix}/share/gEDA/system-commonrc</code></strong>. This file can also be installed in <strong><code>/etc/gEDA</code></strong> (the .debs packages do this). This file is not loaded directly by gschem. It is loaded by a â??(load ...)â?? in the system-gschemrc rc file.</div>
  </li>
  </ul>
  
  <p>
   Make sure these file are installed. The gschem.log file (which is created everytime you run gschem) holds valuable debugging information which should help in determining what is wrong. Check this file for where gschem is looking for the rc files.
  </p>
  
  <p>
  Also, some older releases of gEDA/gaf had some bugs when the rc files were installed in other locations (other that <strong><code>${prefix}/share/gEDA</code></strong>), so please upgrade to a more current release.
  </p>
  
  </div>
  <!-- SECTION [649-2572] -->
  <h2><a name="add_components_offers_no_symbols_what_can_i_do_about_it" id="add_components_offers_no_symbols_what_can_i_do_about_it">&quot;Add Components&quot; offers no symbols! What can I do about it?</a></h2>
  <div class="level2">
  
  <p>
  Make sure that at least one of your config files contains a valid path to a symbol library. At startup, gschem checks for the following config files (on a Debian system):
  </p>
  <ol>
  <li class="level1"><div class="li"> system gafrc file: <code>/etc/gEDA/system-gafrc</code></div>
  </li>
  <li class="level1"><div class="li"> user gafrc file: <code>~/.gEDA/gafrc</code></div>
  </li>
  <li class="level1"><div class="li"> local gafrc file: <code>$PWD/gafrc</code></div>
  </li>
  <li class="level1"><div class="li"> system gschemrc file: <code>/etc/gEDA/system-gschemrc</code></div>
  </li>
  <li class="level1"><div class="li"> user gschemrc file: <code>~/.gEDA/gschemrc</code></div>
  </li>
  <li class="level1"><div class="li"> local gschemrc file: <code>$PWD/gschemrc]</code></div>
  </li>
  </ol>
  
  <p>
  All of these config files may or may not append paths to the library search list. If a config file conatins the command 
  </p>
  <pre class="code">(reset-component-library)</pre>
  
  <p>
   the library search path will be emptied. Order is obviously important, as this command will erase any previously appended paths.  
  </p>
  
  </div>
  <!-- SECTION [2573-3377] -->
  <h1><a name="gschem_usage" id="gschem_usage">Gschem usage</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [3378-3405] -->
  <h2><a name="how_do_i_move_a_component" id="how_do_i_move_a_component">How do I move a component?</a></h2>
  <div class="level2">
  
  <p>
  Newbies with long-time Windows experience often ask this question. Here are three ways to easily move components with gschem:
  </p>
  
  <p>
  One:
  </p>
  <ol>
  <li class="level1"><div class="li"> Grab the component with the middle mouse button. The component will follow the cursor around as you move it.</div>
  </li>
  <li class="level1"><div class="li"> To place the component, release the middle mouse button. The component will stay where you placed it.</div>
  </li>
  </ol>
  
  <p>
  Two:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the component by clicking it with the left mouse button. The component will highlight.</div>
  </li>
  <li class="level1"><div class="li"> Hit the â??Mâ?? key on the keyboard. The component will now follow the cursor around as you move it.</div>
  </li>
  <li class="level1"><div class="li"> To place the component, click the left mouse button. The component will stay where you placed it.</div>
  </li>
  </ol>
  
  <p>
  Three:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the component by clicking it with the left mouse button. The component will highlight.</div>
  </li>
  <li class="level1"><div class="li"> Click the right mouse button. A pop-up menu will appear.</div>
  </li>
  <li class="level1"><div class="li"> With the left mouse button, click on the â??moveâ?? option in the pop-up menu.</div>
  </li>
  <li class="level1"><div class="li"> Click on the component with the left mouse button. The component will now follow the cursor around as you move it.</div>
  </li>
  <li class="level1"><div class="li"> To place the component, click the left mouse button. The component will stay where you placed it.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [3406-4580] -->
  <h2><a name="how_do_i_change_the_size_of_the_text_on_a_symbol" id="how_do_i_change_the_size_of_the_text_on_a_symbol">How do I change the size of the text on a symbol?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Select the symbol.</div>
  </li>
  <li class="level1"><div class="li"> Right click â?? down symbol (or do Hierarchy â?? down symbol). This takes you to the symbol editor.</div>
  </li>
  <li class="level1"><div class="li"> Select the pinnumber you want to change.</div>
  </li>
  <li class="level1"><div class="li"> Do Edit â?? Edit Text (or type keyboard shortcut &ldquo;ex&rdquo;).</div>
  </li>
  <li class="level1"><div class="li"> Change the font size in the pop-up box.</div>
  </li>
  <li class="level1"><div class="li"> Repeat for all desired text elements.</div>
  </li>
  <li class="level1"><div class="li"> File â?? save</div>
  </li>
  <li class="level1"><div class="li"> Right click â?? up (or Hierarchy â?? Up). Now you are back in the schematic editor.</div>
  </li>
  <li class="level1"><div class="li"> With the symbol still selected do Edit â?? Update component (or use the keyboard shortcut â??epâ??). If this doesnâ??t work, just delete the symbol and reload it.</div>
  </li>
  </ol>
  
  <p>
   More generally, you can use this procedure to edit anything on a symbol. (Substitute â??Edit Textâ?? for your desired edit, of course.)
  </p>
  
  </div>
  <!-- SECTION [4581-5371] -->
  <h2><a name="is_there_an_explicit_no_connect_symbol_that_i_can_should_place_in_the_schematic_to_prevent_gnetlist_from_thinking_i_ve_forgotten_a_connection" id="is_there_an_explicit_no_connect_symbol_that_i_can_should_place_in_the_schematic_to_prevent_gnetlist_from_thinking_i_ve_forgotten_a_connection">Is there an explicit &quot;no connect&quot; symbol that I can/should place in the schematic to prevent gnetlist from thinking I've forgotten a connection?</a></h2>
  <div class="level2">
  
  <p>
  Answer: misc â?? nc-left, nc-right, nc-top, nc-bottom.
  </p>
  
  <p>
  Caution: occassionally this may create a net called â??no_connectâ?? (or â??NC??&rdquo;) which may lead to no-connect pins being connected together in gnetlist â?? which you probably _donâ??t_ want to happen.
  </p>
  
  </div>
  <!-- SECTION [5372-5788] -->
  <h2><a name="how_do_i_print_schematics_from_the_command_line" id="how_do_i_print_schematics_from_the_command_line">How do I print schematics from the command line?</a></h2>
  <div class="level2">
  
  <p>
  Running the script <strong><code>gschem-print.scm</code></strong> will create the Postscript file that is specified on the command line.
  </p>
  
  <p>
  The command line below creates a Postscript file from a schematic file (replace MY_SCH with the name of your schematic and GEDA_SCHEME_DIR with the name of the directory where your gEDA scheme files are installed): 
  </p>
  <pre class="code">gschem -p -oMY_SCH.ps -sGEDA_SCHEME_DIR/gschem-print.scm MY_SCH.sch</pre>
  
  <p>
  The BASH script below, which I name <strong><code>gschem-print</code></strong>, creates a Postscript file for each schematic file that is specified on the command line and then outputs each Postscript file to the default printer: 
  </p>
  <pre class="code">#!/bin/bash
  
  # gschem options
  # -oPS_FILENAME output to Postscript file PS_FILENAME
  # -sSCRIPT_FILENAME run script SCRIPT_FILENAME
  # -p autoplace windows
  
  for name in $*
  do
  base=â??${name%.*}â??
  gschem -p -o$base.ps -sGEDA_SCHEME_DIR/gschem-print.scm $base.sch
  lpr -P$PRINTER $base.ps
  done</pre>
  
  </div>
  <!-- SECTION [5789-6774] -->
  <h2><a name="how_can_i_get_color_postscript_png_output" id="how_can_i_get_color_postscript_png_output">How can I get color postscript/PNG output?</a></h2>
  <div class="level2">
  
  <p>
  Edit the <strong><code>system-gschemrc</code></strong> file or place the following into a <strong><code>gschemrc</code></strong> file (either <strong><code>~/.gEDA/gschemrc</code></strong> or a <strong><code>gschemrc</code></strong> file in the local directory where you invoke gschem): 
  </p>
  <pre class="code">(output-color &quot;enabled&quot;)      ; for color postscript output
  (image-color &quot;enabled&quot;)       ; for color PNG output (enabled by default)</pre>
  
  <p>
  To control the background of the PS output, change the following line in either gschem-darkbg (for the default black colored background) or gschem-lightbg (for the alternative light colored background): 
  </p>
  <pre class="code">(output-color-background 16 &quot;black&quot; &quot;null&quot; &quot;0 0 0&quot; 0 0 0)</pre>
  
  <p>
  The â??0 0 0â?? is the RGB components (between 0..1) for the background color of the PS output.
  </p>
  
  <p>
  To control the background of the <acronym title="Portable Network Graphics">PNG</acronym> output, change the following line in either gschem-darkbg (for the default black colored background) or gschem-lightbg (for the alternative light colored background): 
  </p>
  <pre class="code">(background-color 0 &quot;grey94&quot; &quot;null&quot; &quot;1 1 1&quot; 255 255 255)</pre>
  
  <p>
  The 255 255 255 are the RGB components for the background color of the <acronym title="Portable Network Graphics">PNG</acronym> image.
  </p>
  
  </div>
  <!-- SECTION [6775-7906] -->
  <h2><a name="how_can_i_get_black_and_white_postscript_png_output" id="how_can_i_get_black_and_white_postscript_png_output">How can I get black and white postscript/PNG output?</a></h2>
  <div class="level2">
  
  <p>
  For black and white PS output, place the following into a gschemrc file: 
  </p>
  <pre class="code">(output-color &quot;disabled&quot;)      ; for monochrome postscript output</pre>
  
  <p>
  For black and white <acronym title="Portable Network Graphics">PNG</acronym> images, place the following into a gschemrc file: 
  </p>
  <pre class="code">(image-color &quot;disabled&quot;)       ; for monochromoe PNG output</pre>
  
  </div>
  <!-- SECTION [7907-8272] -->
  <h2><a name="how_can_i_insert_schematics_into_my_latex_document" id="how_can_i_insert_schematics_into_my_latex_document">How can I insert schematics into my LaTex document?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Print the schematic to a file. This will be generic postscript (*.ps).</div>
  </li>
  <li class="level1"><div class="li"> Convert the postscript file to epsi with the tool ps2epsi. This is a script from the ghostscript suite.</div>
  </li>
  <li class="level1"><div class="li"> Include usepackage{graphicx} to the preamble of your latex document. Use the comand includegraphics to place your schematic.</div>
  </li>
  </ol>
  
  <p>
   A simple example: 
  </p>
  <pre class="code">\documentclass{article}
  \usepackage{graphicx}
  \begin{document}
    \begin{image}
    \includegraphics[width=100mm]{ModulPID.epsi}
    \end{image}
  \end{document}</pre>
  
  </div>
  <!-- SECTION [8273-8836] -->
  <h2><a name="how_can_i_split_postscript_output_over_multiple_pages" id="how_can_i_split_postscript_output_over_multiple_pages">How can I split postscript output over multiple pages?</a></h2>
  <div class="level2">
  
  <p>
  gschem does not provide this functionality internally, however there is a program called â??posterâ?? which does exactly this. It can be downloaded from either <a href="http://www.gnu.org/directory/poster.html"; class="urlextern" title="http://www.gnu.org/directory/poster.html";  rel="nofollow">here</a> (GNU) or <a href="http://printing.kde.org/downloads/"; class="urlextern" title="http://printing.kde.org/downloads/";  rel="nofollow">here</a> (KDE Print).
  </p>
  
  </div>
  <!-- SECTION [8837-9181] -->
  <h2><a name="how_do_i_unlock_a_locked_component" id="how_do_i_unlock_a_locked_component">How do I unlock a locked component</a></h2>
  <div class="level2">
  
  <p>
  When a component is locked it is unselectable using the middle mouse button however it is selectable using a window select. To window select a component click and hold the left mouse button and drag the mouse to create a rectangular region containing the component to be unlocked. Execute the command <strong><em>Edit</em></strong> <strong>â??</strong> <strong><em>unLock</em></strong> to unlock the component.
  </p>
  
  </div>
  <!-- SECTION [9182-9591] -->
  <h1><a name="gschem_configuration_customization" id="gschem_configuration_customization">Gschem configuration/customization</a></h1>
  <div class="level1">
  
  <p>
  Gschem is configurable in more ways than can be describe here. Look at &ldquo;system-gschemrc&rdquo; for suggestions what else can be done.
  </p>
  
  </div>
  <!-- SECTION [9592-9769] -->
  <h2><a name="how_can_i_change_the_default_size_of_floating_text" id="how_can_i_change_the_default_size_of_floating_text">How can I change the default size of floating text?</a></h2>
  <div class="level2">
  
  <p>
  Put  
  </p>
  <pre class="code">(text-size 10)</pre>
  
  <p>
   into your gschemrc and replace &ldquo;10&rdquo; with your favorite size.
  </p>
  
  </div>
  <!-- SECTION [9770-9928] -->
  <h2><a name="how_can_i_have_a_different_background_color_other_than_black" id="how_can_i_have_a_different_background_color_other_than_black">How can I have a different background color other than black?</a></h2>
  <div class="level2">
  
  <p>
  Edit the system-gschemrc file and near the top you will find lines like: 
  </p>
  <pre class="code">; 
  ; Start of color section
  ; 
  ; Load up a color scheme has a light (almost white) background
  ; Comment out the first line and comment in the second line for a
  ; dark (black) background.  The dark background is the original look.
  ; 
  (load (string-append gedadatarc &quot;/gschem-darkbg&quot;)) ; dark background
  ;(load (string-append gedadatarc &quot;/gschem-lightbg&quot;)) ; light background</pre>
  
  <p>
  Comment out the <strong><code>darkbg</code></strong> line (with a ;) and comment in the <strong><code>lightbg</code></strong> line. This will give you a light background instead of a black background. It also adjust all the other colors to be compatible with a light background.
  </p>
  
  <p>
  If you want more control over the colors, please edit <strong><code>${prefix}/share/gEDA/gschem-darkbg</code></strong> or <strong><code>${prefix}/share/gEDA/gschem-lightbg</code></strong> or create your own file and load it in the <strong><code>system-gschemrc</code></strong> file.
  </p>
  
  <p>
  <acronym title="In my humble opinion">IMHO</acronym>, a black background is easier on the eyes for long periods of time.
  </p>
  
  </div>
  <!-- SECTION [9929-10992] -->
  <h2><a name="how_can_i_get_refdes_automatically_numbered_when_i_draw_a_schematic" id="how_can_i_get_refdes_automatically_numbered_when_i_draw_a_schematic">How can I get refdes automatically numbered when I draw a schematic?</a></h2>
  <div class="level2">
  
  <p>
  Edit the system-gschemrc file or place the following into a gschemrc file (either <strong><code>~/.gEDA/gschemrc</code></strong> or a <strong><code>gschemrc</code></strong> file in the local directory where you invoke gschem): 
  </p>
  <pre class="code">(load &quot;$YOUR_INSTALL_PATH/share/gEDA/scheme/auto-uref.scm&quot;)  ; load the autonumbering script
  (add-hook! add-component-hook auto-uref)                     ; autonumber when adding a component
  (add-hook! copy-component-hook auto-uref)                    ; autonumber when copying a component</pre>
  
  <p>
  Please substitute $YOUR_INSTALL_PATH by the path where geda is installed.
  </p>
  
  </div>
  <!-- SECTION [10993-11636] -->
  <h2><a name="what_are_the_mouse_bindings_in_gschem" id="what_are_the_mouse_bindings_in_gschem">What are the mouse bindings in gschem?</a></h2>
  <div class="level2">
  
  <p>
  By default you get:
  </p>
  <ul>
  <li class="level1"><div class="li"> Left mouse button is used for picking and drawing</div>
  </li>
  <li class="level1"><div class="li"> Middle mouse button is either move object (just hold down the middle button over an object and move the mouse) or copy object (ALT key held down while holding down the middle button over object and move the mouse).</div>
  </li>
  <li class="level1"><div class="li"> Right mouse button is a popup menu.</div>
  </li>
  </ul>
  
  <p>
   You can change the middle button by adding the following to a gschemrc file: 
  </p>
  <pre class="code">(middle-button &quot;action&quot;)   ;default binding, move or copy an object</pre>
  
  <p>
  or: 
  </p>
  <pre class="code">(middle-button &quot;stroke&quot;)   ;draw mouse gestures/strokes (must install libstroke to enable</pre>
  
  <p>
  or: 
  </p>
  <pre class="code">(middle-button &quot;repeat&quot;)   ;repeat the last command executed</pre>
  
  <p>
  You can change the right button by adding the following to a gschemrc file: 
  </p>
  <pre class="code">(third-button &quot;popup&quot;)     ;default binding, show a popup menu</pre>
  
  <p>
  or: 
  </p>
  <pre class="code">(third-button &quot;mousepan&quot;)  ;use the mouse to pan around the schematic</pre>
  
  <p>
  For more information on these options, please see the <strong><code>${install_prefix}/share/gEDA/system-gschemrc</code></strong> file.
  </p>
  
  </div>
  <!-- SECTION [11637-12722] -->
  <h1><a name="information_on_gschem_symbols" id="information_on_gschem_symbols">Information on gschem symbols</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [12723-12767] -->
  <h2><a name="what_s_this_business_about_heavy_vs._light_symbols" id="what_s_this_business_about_heavy_vs._light_symbols">What's this business about heavy vs. light symbols?</a></h2>
  <div class="level2">
  
  <p>
  This nomenclature arose from a discussion which frequently appears on the geda-user and geda-dev mailing lists. A light symbol is one which contains very few built-in attributes in the symbol itself. It requires that the user attach almost all attributes at the schematic level (e.g. using either gschem or gattrib). A heavy symbol is one which contains many attributes (such as package footprints, SPICE model names, etc.) built into the symbol file itself. A heavy symbol therefore requires very little attribute attachment at the schematic level â?? you just place it and youâ??re done.
  </p>
  
  <p>
  The debate between proponents of heavy and light symbols is very detailed and involved. In caricature, proponents of heavy symbols belive that they provide better integration between gschem and PCB since the important layout attributes (such as <a href="geda_pcb_tips.html" class="wikilink1" title="geda:pcb_tips">footprint name</a>) are already built into the symbol. This is considered a good thing for new users (noobs) who just want to design a simple board and donâ??t appreciate or donâ??t care about the zillions of variations that even a simple resistor might have (e.g. different footprint, TCR, precision, material composition, etc). Proponents of light symbols prefer to deal with attributes at the schematic level because they believe it to be more flexible. They are quick to point out that a library of heavy symbols will quickly grow into the thousands of parts with grotesquely long names trying to distinguish between the different variations of the part. They also point out that the utility ï¿½ï¿½ï¿½ï¿½ï¿½gattribâ?? is the preferred tool for dealing with attributes at the schematic level (i.e. in the .sch file).
  </p>
  
  <p>
  GEDA/gaf, as default configured, uses light symbols, although it can be configured to use heavy symbols. For further information, you may read these dicussions from the geda-user mailing list:
  </p>
  
  <p>
  <a href="http://archives.seul.org/geda/user/Jun-2005/msg00001.html"; class="urlextern" title="http://archives.seul.org/geda/user/Jun-2005/msg00001.html";  rel="nofollow">http://archives.seul.org/geda/user/Jun-2005/msg00001.html</a> <a href="http://archives.seul.org/geda/dev/Oct-2005/msg00043.html"; class="urlextern" title="http://archives.seul.org/geda/dev/Oct-2005/msg00043.html";  rel="nofollow">http://archives.seul.org/geda/dev/Oct-2005/msg00043.html</a>
  </p>
  
  </div>
  <!-- SECTION [12768-14912] -->
  <h2><a name="i_am_using_a_symbol_out_of_the_library._how_come_it_s_not_aligned_to_the_grid" id="i_am_using_a_symbol_out_of_the_library._how_come_it_s_not_aligned_to_the_grid">I am using a symbol out of the library.  How come it's not aligned to the grid?</a></h2>
  <div class="level2">
  
  <p>
  The symbols in the symbol library, like those available at the  <a href="http://www.gedasymbols.org/"; class="urlextern" title="http://www.gedasymbols.org";  rel="nofollow"> gedasymbols </a> website are contributed by users just like you.  Some people use different grid settings than other people (e.g. 50mil vs. 100mil).   If you discover a symbol which seems to be off the grid, try reducing your grid spacing, move the symbol so that it sits on <strong>your</strong> grid, then revert to your preferred grid settings.
  </p>
  
  <p>
  Yes, the gEDA docs suggest that you use a 100mil grid spacing.  But everybody likes to do things their own way, and there is no overall symbol dictator to enforce the rules on contributed symbols.  Therefore, you just need to be aware of this possibility.
  </p>
  
  </div>
  <!-- SECTION [14913-15690] -->
  <h2><a name="how_do_i_promote_an_invisible_symbol_attribute_into_the_schematic" id="how_do_i_promote_an_invisible_symbol_attribute_into_the_schematic">How do I promote an invisible symbol attribute into the schematic?</a></h2>
  <div class="level2">
  
  <p>
  Most attributes living in the symbol do not get promoted to the schematic unless they are visible. To promote invisible symbol attributes, look for the following keywords in the system-gschemrc file: 
  </p>
  <pre class="code">(attribute-promotion â??enabledâ??);
  (promote-invisible â??disabledâ??) ; â?? This one
  (keep-invisible â??enabledâ??)</pre>
  
  <p>
  Add to your gschemrc file: 
  </p>
  <pre class="code">(promote-invisible â??enabledâ??)</pre>
  
  <p>
  and you will get all the attributes promoted. The â??keep-invisibleâ?? keyword will keep hidden those attributes that are hidden in the symbol file.
  </p>
  
  </div>
  <!-- SECTION [15691-16326] -->
  <h2><a name="what_should_i_do_about_power_pins_on_my_symbolsmake_them_visible_explicit_or_invisible_implicit" id="what_should_i_do_about_power_pins_on_my_symbolsmake_them_visible_explicit_or_invisible_implicit">What should I do about power pins on my symbols: Make them visible (explicit) or invisible (implicit)?</a></h2>
  <div class="level2">
  
  <p>
  In the past, digital logic circuits often hid the power pin, and attached power nets using an attribute inside the symbol. Modern thought is that this is a bad practice (although religious wars still occasionally rage about this topic).
  </p>
  
  <p>
  Itâ??s marginally OK for an old logic circuit which is all 5V TTL to have hidden power and GND pins. If you only have +5V on your board, then hiding the power pin can simplify your schematic somewhat. However, few designers design such circuits nowadays; 5V TTL (and 5V CMOS) are rapidly becoming antique technologies.
  </p>
  
  <p>
  Itâ??s always been unacceptable to hide the power pins on analog chips. First, analog often has multiple power connections (VCC, VEE) which need to be explicitly drawn out. Second, good design practice is to place decoupling caps on each and every power pin. Sometimes one places an inductor in series with power also. Since these should be drawn into the schematic, it is best done by attaching them to an explicit power pin. Therefore, one should never use hidden power pins for analog symbols.
  </p>
  
  <p>
  New logic circuits often use multiple supplies for different chip sections (OVDD, DVDD, etc). It is also typical to have several logic families on a single board (5V, 3.3V etc.). Therefore, itâ??s best to explicitly place and wire the power pins on the symbol. Hidden power pins are a recipe for disaster since you can all too easily misconnect a 5V part to a 3.3V power net, for example.
  </p>
  
  <p>
  To paraphrase Nancy Reagan: Just say â??noâ?? to hidden power pins.
  </p>
  
  <p>
  That said, it may still be usefull to detach the power pins from the functional part of the symbol. To do so, define a seperate power symbol and give it the same <a href="http://geda.seul.org/wiki/geda:glossary"; class="wikilink1" title="geda:glossary">refdes</a> as the functional part. A run of gsch2pcb will treat the siblings properly as one single component. As neither gschem nor gsch2pcb explicitely know that the component is only complete with both symbols defined, you have to check yourself. With this workaround, you can draw all power related circuitry in one corner of the schematic where it does not interfere with the signal nets. In many cases this is advantageous with analog circuits.
  </p>
  
  </div>
  <!-- SECTION [16327-18584] -->
  <h2><a name="is_there_a_specification_or_manual_for_creating_gschem_symbols_where_is_it" id="is_there_a_specification_or_manual_for_creating_gschem_symbols_where_is_it">Is there a specification or manual for creating gschem symbols? Where is it?</a></h2>
  <div class="level2">
  
  <p>
  Yes. It is the <a href="geda_scg.html" class="wikilink1" title="geda:scg">Symbol Creation Guide</a>. 
  </p>
  
  </div>
  <!-- SECTION [18585-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_faq-simulation.html
  
  Index: geda_faq-simulation.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#simulation" class="toc">Simulation</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#i_want_to_simulate_my_analog_circuit_design._what_are_my_options" class="toc">I want to simulate my analog circuit design. What are my options?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_about_tclspice_what_is_it_should_i_use_it" class="toc">What about tclspice? What is it? Should I use it?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#isn_t_there_a_nice_graphical_schematic_capture_front_end_so_i_can_just_place_components_and_press_a_simulate_button" class="toc">Isn't there a nice graphical (schematic capture) front end so I can just place components and press a &quot;simulate&quot; button?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_create_my_schematic_to_facilitate_analog_simulation" class="toc">How do I create my schematic to facilitate analog simulation?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#which_spice_netlister_backend_to_gnetlist_should_i_use_there_are_several_of_them" class="toc">Which spice netlister backend to gnetlist should I use? There are several of them. . . .</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_about_if_i_want_to_use_gnucap_can_i_use_spice-sdb_to_create_my_gnucap_netlists" class="toc">How about if I want to use gnucap, can I use spice-sdb to create my gnucap netlists?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_not_reuse_my_simulation_schematic_for_layout" class="toc">Why not reuse my simulation schematic for layout?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="simulation" id="simulation">Simulation</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-25] -->
  <h2><a name="i_want_to_simulate_my_analog_circuit_design._what_are_my_options" id="i_want_to_simulate_my_analog_circuit_design._what_are_my_options">I want to simulate my analog circuit design. What are my options?</a></h2>
  <div class="level2">
  
  <p>
  Within the cannonical gEDA Suite apps there are two analog circuit simulators: ngspice and gnucap. In (slightly) more detail:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://ngspice.sourceforge.net/"; class="urlextern" title="http://ngspice.sourceforge.net/";  rel="nofollow">Ngspice</a> is a port/clean-up of classical SPICE 3f5 to the GNU/Linux platform. It is fully functional, includes the XSpice extensions (such as SPICE 2 POLY constructs), and the CIDER framework.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.gnucap.org/"; class="urlextern" title="http://www.gnucap.org/";  rel="nofollow">Gnucap</a> is a new circuit simulator written from the ground up. It offers the ability to perform event-driven â?? as well as continuous time â?? simulations. It is the work of Al Davis, Professor of Electrical Engineering at Kettering University. If you wish to download it, make sure you grab the latest version, available through the â??developement releasesâ?? link on the gnucap website.</div>
  </li>
  </ul>
  
  <p>
   Both are CLI (command line interface) programs, meaning that you intereact with the simulator by typing commands at a command line. It also means that you need to learn the simulator-specific command set.
  </p>
  
  <p>
  If you prefer a graphical interface, the new gEDA app GSpiceUI provides a nice <acronym title="Graphical User Interface">GUI</acronym> front-end to drive the simulation programs. However, GSpiceUI is not a complete schematic-to-simulation-output simulator like LTSpice or PSpice. Rather, it just provides a <acronym title="Graphical User Interface">GUI</acronym> menu which helps you navigate the commands you need to perform your ngspice/gnucap simulation.
  </p>
  
  </div>
  <!-- SECTION [26-1444] -->
  <h2><a name="what_about_tclspice_what_is_it_should_i_use_it" id="what_about_tclspice_what_is_it_should_i_use_it">What about tclspice? What is it? Should I use it?</a></h2>
  <div class="level2">
  
  <p>
  <a href="http://tclspice.sourceforge.net/"; class="urlextern" title="http://tclspice.sourceforge.net/";  rel="nofollow">Tclspice</a> was a fork off the ngspice development path. It was begun in the 2002 timeframe. In principle, tclspice would export the SPICE command set to a TCL <acronym title="Application Programming Interface">API</acronym>, allowing you to embed SPICE analyses into a TCL program. This vision is certainly very attractive since TCL is a powerful scripting language â?? much more powerful than the scripting constructs available from within SPICE itself. Using TCL, one could imagine writing complex circuit optimizers, adding behavioral elements to a simulation, and finally gaining control over SPICEâ??s graphical output.
  </p>
  
  <p>
  As it turns out, this goal was partially met â?? with tclspice you can indeed do something like this: 
  </p>
  <pre class="code">#! tclsh 
  package require spice 
  spice::codemodel /usr/local/src/tclspice-0.2.12/src/xspice/icm/spice2poly.cm 
  
  spice::source netlistname.cir
  spice::tran 0.1ns 40ns
  spice::run
  spice::plot Vout
  puts &quot;All done now!&quot;</pre>
  
  <p>
  Unfortunately, tclspice lacks certain important features, like providing you a return code which tells you whether your simulation actually worked or errored out instead. Also, the graphics functionality never seemed to work (at least for me ... and the developers admit that the graphics stink). Converting TCL variables to and from SPICE vectors never seemed to work â?? again at least for me. Finally, ngspice (at least) has a lot of memory leaks, making long simulation runs difficult. Therefore, tclspice doesnâ??t meet the promise it originally held out: a convenient, scriptable way to drive SPICE simulations.
  </p>
  
  <p>
  Developement on tclspice effectively stopped in 2004. Perhaps some day somebody will pick it up again. In the meantime, the main <a href="http://ngspice.sourceforge.net/"; class="urlextern" title="http://ngspice.sourceforge.net/";  rel="nofollow">ngspice</a> development branch has picked up the tclspice features if you want them (they require separate configuration options), and the code is fresher.
  </p>
  
  </div>
  <!-- SECTION [1445-3373] -->
  <h2><a name="isn_t_there_a_nice_graphical_schematic_capture_front_end_so_i_can_just_place_components_and_press_a_simulate_button" id="isn_t_there_a_nice_graphical_schematic_capture_front_end_so_i_can_just_place_components_and_press_a_simulate_button">Isn't there a nice graphical (schematic capture) front end so I can just place components and press a &quot;simulate&quot; button?</a></h2>
  <div class="level2">
  
  <p>
  No. The best you can do is use GSpiceUI.
  </p>
  
  </div>
  <!-- SECTION [3374-3548] -->
  <h2><a name="how_do_i_create_my_schematic_to_facilitate_analog_simulation" id="how_do_i_create_my_schematic_to_facilitate_analog_simulation">How do I create my schematic to facilitate analog simulation?</a></h2>
  <div class="level2">
  
  <p>
  The usual design path is â??gschemâ?? â?? â??gnetlist -g spice-sdbâ?? â?? [â??ngspiceâ?? | â??gnucapâ??]. You need to attach attributes to the components in your schematic to provide attributes needed by SPICE/Gnucap. You can also attach attributes using gattrib.
  </p>
  
  <p>
  The <a href="geda_csygas.html" class="wikilink1" title="geda:csygas">Circuit Simulation using gEDA and SPICE - HOWTO</a> describes all this in great detail.
  </p>
  
  <p>
   Some <a href="http://www.brorson.com/gEDA/SPICE/"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/";  rel="nofollow">SPICE resources</a> will help you understand how to use spice-sdb.
  </p>
  
  </div>
  <!-- SECTION [3549-4101] -->
  <h2><a name="which_spice_netlister_backend_to_gnetlist_should_i_use_there_are_several_of_them" id="which_spice_netlister_backend_to_gnetlist_should_i_use_there_are_several_of_them">Which spice netlister backend to gnetlist should I use? There are several of them. . . .</a></h2>
  <div class="level2">
  
  <p>
  Use spice-sdb. It is by far the most advanced and feature rich. The others are there only for reasons of history. Note that spice-sdb is an extension of one of the other SPICE backends, so you arenâ??t missing anything by using spice-sdb.
  </p>
  
  </div>
  <!-- SECTION [4102-4442] -->
  <h2><a name="how_about_if_i_want_to_use_gnucap_can_i_use_spice-sdb_to_create_my_gnucap_netlists" id="how_about_if_i_want_to_use_gnucap_can_i_use_spice-sdb_to_create_my_gnucap_netlists">How about if I want to use gnucap, can I use spice-sdb to create my gnucap netlists?</a></h2>
  <div class="level2">
  
  <p>
  Yes. Also, you can draw your schematic using gnucap directives available in the â??spiceâ?? symbol directory.
  </p>
  
  </div>
  <!-- SECTION [4443-4650] -->
  <h2><a name="why_not_reuse_my_simulation_schematic_for_layout" id="why_not_reuse_my_simulation_schematic_for_layout">Why not reuse my simulation schematic for layout?</a></h2>
  <div class="level2">
  
  <p>
  Newbies commonly want to create a single schematic for both design simulation/validation as well as layout. This vision seems very attractive at first, since your layout will have been tested &amp; validated before committing it to FR-4. However, the devil is in the details; using a single schematic for simulation and layout usually doesnâ??t work for the following reasons:
  </p>
  <ul>
  <li class="level1"><div class="li"> Components required for simulation and layout are normally very different. For example, simulation often requires a schematic holding a bunch of SPICE-related devices such as voltage sources, dependent sources, SPICE directives, and so on. On the other hand, layout requires non-SPICEable components such as connectors, logic devices, and even things like voltage regulators which might have no SPICE models available, but will pollute your SPICE netlist, possibly making the netlister and the simulator unhappy.</div>
  </li>
  <li class="level1"><div class="li"> Some real electronic components donâ??t have built-in SPICE models. There are plenty of components which donâ??t have native SPICE models like potentiometers, transformers, thermistors, EMI filters, logic gates, crystals, vacuum tubes, and on and on. Therefore, if your design uses any of these components, you must mock up the device using an equivalent circuit for simulation. This makes it very difficult to reuse the simulation schematic for layout.</div>
  </li>
  <li class="level1"><div class="li"> Usually, you only really need to simulate a subset of your design. For example, you might want to simulate the behavior of a filter or oscillator circuit, but donâ??t care about (or canâ??t simulate) your power supply, glue logic, or other part of your design. If you insist upon creating a SPICE model for these circuit subsections, you might need to jump through a lot of hoops â?? and do a lot of unnecessary hard work â?? in order to find or create SPICE models for parts of your design which arenâ??t important.</div>
  </li>
  </ul>
  
  <p>
   Therefore, I (SDB) normally recommend that you shouldnâ??t try too hard to use the same schematic for simulation and for layout. If you can do it, great! But usually you canâ??t.
  </p>
  
  <p>
  Personally, I tend to create SPICE models of only the critical analog sections of my design. A larger project might therefore have a couple of simulation schematics validating a couple of analog subcircuits. Besides the simulation scheamtics, Iâ??ll have a main schematic which is used for layout. 
  </p>
  
  </div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_faq.html
  
  Index: geda_faq.html
  ===================================================================
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_faq" class="toc">gEDA FAQ</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_geda_project" class="toc">What is the gEDA project?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_geda_gaf_and_how_does_it_relate_to_geda" class="toc">What is gEDA/gaf and how does it relate to gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_geda_suite" class="toc">What is the gEDA suite?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_what_makes_geda_so_different_from_other_eda_tools" class="toc">Why? What makes gEDA so different from other EDA tools?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application" class="toc">Why does the gEDA Suite seem like a collection of random programs, and not a single integrated application?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application" class="toc">So which is better, a suite (i.e. confederacy) of programs or an integrated application?</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#suite_confederacy_pros" class="toc">Suite (confederacy) pros:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#suite_confederacy_cons" class="toc">Suite (confederacy) cons:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#monolithic_application_pros" class="toc">Monolithic application pros:</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#monolithic_application_cons" class="toc">Monolithic application cons:</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_license_does_geda_use" class="toc">What license does gEDA use?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#where_can_i_get_more_information_about_and_download_geda" class="toc">Where can I get more information about and download gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#okay_how_do_i_start_using_geda" class="toc">Okay, how do I start using gEDA?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_faq" id="geda_faq">gEDA FAQ</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-24] -->
  <h2><a name="what_is_the_geda_project" id="what_is_the_geda_project">What is the gEDA project?</a></h2>
  <div class="level2">
  
  <p>
  The gEDA project is working on producing a full <acronym title="GNU General Public License">GPL</acronym>&lsquo;d suite of EDA (<em class="u">E</em>lectronic <em class="u">D</em>esign <em class="u">A</em>utomation) tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout.
  </p>
  
  <p>
  The originator of gEDA project is Ales Hvezda. The gEDA project has grown quite a bit, since the Spring of 1998. It is no longer one person producing tools. Instead, there are many people involved. A few people are contributing to the original tools, while others are doing their own development on their own tools. So, gEDA does not refer to the original tools anymore (those tools now stand on their own now), but instead it refers to all the projects which are free and are somehow associated with this webpage or the geda-dev/geda-user mailing lists. By associating with gEDA, free software authors do not give up any control over their tools, but they gain a community which cares about quality and free (as in freedom) EDA tools.
  </p>
  
  <p>
  gEDA can be pronounced â??gee-daahhhâ?? (rhymes with cheetah) or â??g-dahhh (short g).
  </p>
  
  </div>
  <!-- SECTION [25-1420] -->
  <h2><a name="what_is_geda_gaf_and_how_does_it_relate_to_geda" id="what_is_geda_gaf_and_how_does_it_relate_to_geda">What is gEDA/gaf and how does it relate to gEDA?</a></h2>
  <div class="level2">
  
  <p>
  gaf stands for â??<em class="u">g</em>schem <em class="u">a</em>nd <em class="u">f</em>riendsâ??. It is a subset of the entire tool suite grouped together under the gEDA name. gEDA/gaf is a collection of tools which currently includes:
  </p>
  <ul>
  <li class="level1"><div class="li"> gschem: A schematic capture program</div>
  </li>
  <li class="level1"><div class="li"> gnetlist: A netlist generation program</div>
  </li>
  <li class="level1"><div class="li"> gsymcheck: A syntax checker for schematic symbols</div>
  </li>
  <li class="level1"><div class="li"> gattrib: A spreadsheet programm that manipulates the properties of symbols of a schematic</div>
  </li>
  <li class="level1"><div class="li"> libgeda: Libraries for gschem gnetlist and gsymcheck</div>
  </li>
  <li class="level1"><div class="li"> gsch2pcb: Forward annotation from your schematic to layout using <a href="geda_pcb.html" class="wikilink2" title="geda:pcb">PCB</a>.</div>
  </li>
  <li class="level1"><div class="li"> some minor utils</div>
  </li>
  </ul>
  
  <p>
   The gEDA/gaf tools share a common file format (.sch) and also share a common link library (libgeda.so). The gEDA/gaf source distribution can be found on this website (geda.seul.org).
  </p>
  
  <p>
  Even though gaf is very much a part of gEDA, the gEDA name does not necessarily only apply to gaf â?? tools gathered under the â??gEDAâ?? moniker include many other programs. Indeed, gEDA refers to <strong>any</strong> <acronym title="GNU General Public License">GPL</acronym>&lsquo;d EDA tool which decides to associate itself with the gEDA website/mailing list. Important examples of gEDA tools include the layout program <a href="geda_pcb.html" class="wikilink2" title="geda:pcb">PCB</a>, the Verilog complier <a href="http://www.icarus.com/eda/verilog/"; class="urlextern" title="http://www.icarus.com/eda/verilog/";  rel="nofollow">Icarus Verilog</a>, the analog circuit simulator <a href="http://www.gnucap.org/"; class="urlextern" title="http://www.gnucap.org/";  rel="nofollow">gnucap</a>, and the open-source SPICE simulator <a href="http://www.ngspice.org/"; class="urlextern" title="http://www.ngspice.org/";  rel="nofollow">ngspice</a>. Many other gEDA programs also exist.
  </p>
  
  <p>
  For historical reasons, on <a href="http://freshmeat.net/"; class="urlextern" title="http://freshmeat.net/";  rel="nofollow">freshmeat</a> gaf is known as the package â??gEDAâ??.
  </p>
  
  </div>
  <!-- SECTION [1421-2969] -->
  <h2><a name="what_is_the_geda_suite" id="what_is_the_geda_suite">What is the gEDA suite?</a></h2>
  <div class="level2">
  
  <p>
  The gEDA suite is a CDROM image (.iso) created by Stuart Brorson to make it easier to install all the various tools that are part of, associated with, or just plain work with the gEDA projectâ??s software. The vision is that the tools collected on the gEDA suite CDROM constitute a coherent, complete, open-source design environment gathered into one convenient download. Currently the gEDA suite CDROM includes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/"; class="urlextern" title="http://geda.seul.org/tools/";  rel="nofollow">gEDA/gaf</a> â?? schematic capture and netlisting</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/ngspice"; class="urlextern" title="http://geda.seul.org/tools/ngspice";  rel="nofollow">ngspice</a> â?? SPICE simulation</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gnucap"; class="urlextern" title="http://geda.seul.org/tools/gnucap";  rel="nofollow">gnucap</a> â?? Analog simulation</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gspiceui"; class="urlextern" title="http://geda.seul.org/tools/gspiceui";  rel="nofollow">gspiceui</a> â?? <acronym title="Graphical User Interface">GUI</acronym> front end for ngspice/gnucap</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/pcb"; class="urlextern" title="http://geda.seul.org/tools/pcb";  rel="nofollow">pcb</a> â?? PCB layout</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gerbv"; class="urlextern" title="http://geda.seul.org/tools/gerbv";  rel="nofollow">gerbv</a> â?? Gerber viewer</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/icarus"; class="urlextern" title="http://geda.seul.org/tools/icarus";  rel="nofollow">Icarus Verilog</a> â?? Verilog simulator</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/tools/gtkwave"; class="urlextern" title="http://geda.seul.org/tools/gtkwave";  rel="nofollow">GTKWave</a> â?? Digitial waveform viewer</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://wcalc.sourceforge.net/"; class="urlextern" title="http://wcalc.sourceforge.net/";  rel="nofollow">wcalc</a> â?? Transmission line and electromagnetic structure analysis</div>
  </li>
  </ul>
  
  <p>
   At the center of the gEDA suite CDROM is an easy to use installer that automates the building and installing of all the various packages from source â?? making it easy to install the whole suite for the first time user. The gEDA suite CDROM image is available from the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">download</a> page. <strong>Note: The installer works only with Linux!</strong>
  </p>
  
  </div>
  <!-- SECTION [2970-4492] -->
  <h2><a name="why_what_makes_geda_so_different_from_other_eda_tools" id="why_what_makes_geda_so_different_from_other_eda_tools">Why? What makes gEDA so different from other EDA tools?</a></h2>
  <div class="level2">
  
  <p>
  Tools in the gEDA suite and associated tools have the following characteristics:
  </p>
  <ul>
  <li class="level1"><div class="li"> Free in the monetary sense (no cost).</div>
  </li>
  <li class="level1"><div class="li"> All the file formats and all the source codes are available via the <acronym title="GNU General Public License">GPL</acronym> license. This license grants specific rights to the authors and users of <acronym title="GNU General Public License">GPL</acronym>&lsquo;d software.</div>
  </li>
  <li class="level1"><div class="li"> Independence from any one vendor. All gEDA tools come with full source. You can change, improve, port, and even distribute (if you follow the terms of the <acronym title="GNU General Public License">GPL</acronym>) the tools.</div>
  </li>
  <li class="level1"><div class="li"> No mechanism is used to restrict the use of the tools (like making use of hard disk serial numbers or ethernet addresses to force the software to only run on one machine).</div>
  </li>
  <li class="level1"><div class="li"> No arbitrary, marketeering-driven limitations. Free versions of commercial tools usually include capricious limitations (i.e. limited design size, inability to print, inability to export netlists, etc.) which cripple the program, and force the serious user to buy the real tool. In contrast, the gEDA tools are fully-featured, and do not arbitrarily impose limits on design as a way of extracting money from you.</div>
  </li>
  <li class="level1"><div class="li"> Legacy design protection. Since the software will always run forever (because of above), gEDA tool design files will always be viewable/editable (with the right versions of the software).</div>
  </li>
  <li class="level1"><div class="li"> Open design flow. This means that the tools talk to each other via known and documented means (files / APIs). It is easy to replace a tool or augment the tools with something else if you so desire.</div>
  </li>
  <li class="level1"><div class="li"> Stability - Bugs which cause crashes are investigated immediately and fixed as soon as possible.</div>
  </li>
  <li class="level1"><div class="li"> Minimize bloat and unnecessary features.</div>
  </li>
  <li class="level1"><div class="li"> Run on as many platforms as possible. For gEDA/gaf: GNU/Linux, various other Unix systems.</div>
  </li>
  <li class="level1"><div class="li"> Developed in an open (no secrets) fashion.</div>
  </li>
  <li class="level1"><div class="li"> Strive to be documented.</div>
  </li>
  </ul>
  
  <p>
   gEDA may not have all the latest cutting edge features found in other packages and may be viewed sometimes as being on the trailing edge of EDA technology, but the tools are becoming useful to a lot of people because the above mentioned reasons.
  </p>
  
  </div>
  <!-- SECTION [4493-6575] -->
  <h2><a name="why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application" id="why_does_the_geda_suite_seem_like_a_collection_of_random_programs_and_not_a_single_integrated_application">Why does the gEDA Suite seem like a collection of random programs, and not a single integrated application?</a></h2>
  <div class="level2">
  
  <p>
  The gEDA suite is indeed a confederacy of somewhat independent programs. This happened for reasons of history: Ales Hvezda started the gEDA project more or less on his own. The original vision was to produce an end-to-end software suite for creating PC boards so that robotics hobbiests could design their own boards. However, as the gEDA project progressed the large magnitude of this task became clear â?? and coding many of the proposed apps had not even begun!
  </p>
  
  <p>
  Meanwhile, other software developers â?? with their own independently written applications â?? found the gEDA project vision compelling. The authors of those applications joined Ales and contributed their programs to the gEDA project. Amongst the contributed projects was â??pcbâ??, a ten year old (at that time) PCB layout program. With the contribution of â??pcbâ??, gEDAâ??s originally planned layout tool â??gpcbâ?? was scuttled. At the same time, other developers contributed analog and digital simulators, waveform viewers, and so on.
  </p>
  
  <p>
  In this way the gEDA suite came together. It is not shared code, or a common user interface which distinguishes the gEDA suite. Rather, the shared vision of an open-source EDA environment is the thread which holds the project together. Today, the gEDA Suite is a collection of many different programs contributed by many different authors. The apps strive to work together, and usually succeed. But the separate beginnings of each program in the suite are still observable. Nonetheless, with a little work the various components of the suite are interoperable, and many people have completed quite complex board designs using the gEDA suite.
  </p>
  
  </div>
  <!-- SECTION [6576-8346] -->
  <h2><a name="so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application" id="so_which_is_better_a_suite_i.e._confederacy_of_programs_or_an_integrated_application">So which is better, a suite (i.e. confederacy) of programs or an integrated application?</a></h2>
  <div class="level2">
  
  <p>
  This is ultimately a matter of religion. Iâ??ll summarize some of the pros and cons (as I see them) of each approach here. 
  </p>
  
  </div>
  <!-- SECTION [8347-8570] -->
  <h3><a name="suite_confederacy_pros" id="suite_confederacy_pros">Suite (confederacy) pros:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> You can use â??best of breedâ?? applications for each part of the design flow. That is, you can use the standard gEDA flow gschem â?? gsch2pcb â?? pcb to create a PC Board. However, if you think that the open-source application â??pcbâ?? stinks, you can use the flow gschem â?? gnetlist â?? Protel (for example). Recall that gnetlist can output more than twenty different netlist formats! Moreover, if you donâ??t like one component of the flow, you can write another tool to replace it. Now at this time it is true that only a single application generally exists to perform a particular task. However, this situation will likely change with time â?? witness the forking of the â??pcbâ?? project, the contributed netlister <a href="http://www.viasic.com/opensource/"; class="urlextern" title="http://www.viasic.com/opensource/";  rel="nofollow">gnetman</a>, as well as the <a href="http://web.comhem.se/~u31829222/"; class="urlextern" title="http://web.comhem.se/~u31829222/";  rel="nofollow">HEC</a> project. As a general rule, the suite approach offers the greatest freedom to the user.</div>
  </li>
  <li class="level1"><div class="li"> The design flow has a lot of natural breakpoints. These occur where one design tool completes its job and writes out a file (i.e. gschem writes out a .sch file, or gnetlist writes out a SPICE netlist). At this point, you can easily break into the flow and write scripts which process and/or munge the design data. For big, advanced designs, this is a real advantage to the â??design suiteâ?? approach. This advantage may appeal only to the â??power userâ??, but note itâ??s importance: professional-grade EDA suites (Synopsys, Xilinx) also work the same way.</div>
  </li>
  <li class="level1"><div class="li"> Usage of an applications suite can be automated using a Makefile, or even a <acronym title="Practical Extraction and Report Language">Perl</acronym> script. ASIC designers do this all the time with their design and synthesis tools. Some gEDA users have publically disclosed (on the e-mail list) that they do this too, and point to it as an important feature of the gEDA suite.</div>
  </li>
  <li class="level1"><div class="li"> Scalability: A monolithic application is almost always developed by a lone developer who has a single-minded vision for his program. This developer can enforce stylistic and UI standards throughout all his tools. The problem with this is that a single developer â?? even one who is uniquely gifted â?? can only write one (or a couple of) parts of an EDA application. Therefore, any open-source, monolithic EDA app will likely always be limited in scope &amp; features by the abilities of a single developer. (I would love to be proven wrong on this point. I welcome counter-examples, but none have come to my attention as of this writing.) On the other hand, a confederacy of developers working independently on their own apps â?? but meanwhile contributing to a greater whole â?? can create a very large and capable EDA enviornment indeed.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [8571-11242] -->
  <h3><a name="suite_confederacy_cons" id="suite_confederacy_cons">Suite (confederacy) cons:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> More confusing to newbies, since they donâ??t know the flow right off the bat. That is, they actually need to <acronym title="Read The Fine Manual">RTFM</acronym> to know what tool to run next. Good documentation helps (thatâ??s why youâ??re reading this), but documentation is always second choice behind developing an intuitive application interface.</div>
  </li>
  <li class="level1"><div class="li"> Different programs have different UI conventions (i.e. menu organization is different, keyboard or mouse bindings are different). This can be uncomfortable to those who arenâ??t familiar with the programs.</div>
  </li>
  <li class="level1"><div class="li"> Since no assumptions are made about the design flow, schematic symbols are necessarily <a href="http://geda.seul.org/wiki/geda:faq-gschem#what_s_this_business_about_heavy_vs._light_symbols"; class="wikilink1" title="geda:faq-gschem">light</a>. This forces the user to spend more time attaching e.g. footprint attributes to his design. Moreover, the user must spend more time actually researching which footprints to use. However, a good suite (like the gEDA suite) will offer multiple methods to perform this task (e.g. gattrib, <acronym title="Practical Extraction and Report Language">Perl</acronym> scripts to populate footprints, etc.).</div>
  </li>
  <li class="level1"><div class="li"> Some developers are more energetic than others, or have more free time. Therefore, some programs in a suite will be more developed (and less buggy) than others. Unfortunately, a single buggy program in a suite can unfairly taint a new userâ??s perception of the entire suite.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [11243-12576] -->
  <h3><a name="monolithic_application_pros" id="monolithic_application_pros">Monolithic application pros:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> A single, unified design environment is easier for newbies to grasp. UI conventions may be harmonized. The tool might be intuitive enough that it can be driven without needing to <acronym title="Read The Fine Manual">RTFM</acronym>.</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture symbols can be heavy, so less work is required in attaching attributes to each symbol in a schematic.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [12577-12929] -->
  <h3><a name="monolithic_application_cons" id="monolithic_application_cons">Monolithic application cons:</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Not infinitely scalable. One developer canâ??t do everything, no matter how smart. Therefore, a monolithic app will never approach the size or power of a suite developed by a confederacy of programmers.</div>
  </li>
  <li class="level1"><div class="li"> Lack of choice. If the developer doesnâ??t like your way of doing things, you have no choice. Even if you submit patches to enable your way of performing a task, there is a chance the main developer will ignore or reject your patches. This is probably not an issue for newbies, but for â??power usersâ?? it represents a problem.</div>
  </li>
  <li class="level1"><div class="li"> Risk. If the apps developer quits, the code becomes abandoned, and the users suffer. This effectively happened to the program <a href="http://sourceforge.net/projects/xtrkcad"; class="urlextern" title="http://sourceforge.net/projects/xtrkcad";  rel="nofollow">XTrkCAD</a>, a CAD program for designing model railroads. The author of this program quit developing it, but thankfully placed his stuff on Sourceforge so that the program wouldnâ??t simply disappear. Unfortunately, without the original developerâ??s involvement, the code languished. Patches contributed to the project went to /dev/null. Eventually, a coalition of concerned user/developers created a <a href="http://xtrkcad-fork.sourceforge.net/"; class="urlextern" title="http://xtrkcad-fork.sourceforge.net/";  rel="nofollow">fork</a> of the code to enable further development. However, work on the forked code has been piecemeal and sporadic. (Hopefully, this will change someday.) Meanwhile, for the ordinary user, the fact that the original developer quit represents a catastrophe.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [12930-14377] -->
  <h2><a name="what_license_does_geda_use" id="what_license_does_geda_use">What license does gEDA use?</a></h2>
  <div class="level2">
  
  <p>
  All of the tools and associated files in gEDA will be released under the GNU General Public License version 2 (<acronym title="GNU General Public License">GPL</acronym>), from Free Software Foundation
  </p>
  
  <p>
  From the license:
  </p>
  
  <p>
  When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.
  </p>
  
  <p>
  This cannot be stressed enough: <strong>gEDA is GPLed software</strong>. Therefore nothing proprietary can be distributed with gEDA like part libraries from proprietary EDA products. Conversion program for proprietary libraries will be available, but any converted files which are part of a proprietary product must never find their way into gEDA. Contributed files must be GPLable (or be placed under another free license). Please keep this in mind if you wish to contribute something.
  </p>
  
  <p>
  Even though the focus of gEDA is GPLed software, other software licenses are more than welcome to be mixed with the existing software, just as long as they are compatible with the <acronym title="GNU General Public License">GPL</acronym>.
  </p>
  
  </div>
  <!-- SECTION [14378-15656] -->
  <h2><a name="where_can_i_get_more_information_about_and_download_geda" id="where_can_i_get_more_information_about_and_download_geda">Where can I get more information about and download gEDA?</a></h2>
  <div class="level2">
  
  <p>
  The official website is <a href="http://geda.seul.org/"; class="urlextern" title="http://geda.seul.org/";  rel="nofollow">gEDA Project</a> hosted by the <a href="http://www.seul.org/"; class="urlextern" title="http://www.seul.org/";  rel="nofollow">SEUL Project</a>. The European mirror is at <a href="http://ftp.sunet.se/geda/"; class="urlextern" title="http://ftp.sunet.se/geda/";  rel="nofollow">European gEDA Project mirror</a> hosted by Swedish University Network - Sweden, Nothern Europe.
  </p>
  
  <p>
  There are several mailing lists. Please look at the mailing listâ??s <a href="http://geda.seul.org/mailinglist"; class="urlextern" title="http://geda.seul.org/mailinglist";  rel="nofollow">info page</a> for how to subscribe and post.
  </p>
  
  <p>
  You can download all the software, including the gEDA suite CDROM from the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">download</a> page.
  </p>
  
  <p>
  You can find the latest set of documentation on the toplevel <a href="http://geda.seul.org/docs/"; class="urlextern" title="http://geda.seul.org/docs/";  rel="nofollow">documentation</a> page.
  </p>
  
  <p>
  Come to the Free EDA Users Group (Freedog) meeeting in Cambridge, MA. The meeting is at 7PM on the first Wednesday of each month at the <a href="http://www.starbucks.com/retail/locator/MapResults.aspx?a=1&StoreKey=93728&IC_O=42.3599350625432%3a-71.1021394862385%3a32%3a02139+(postal+code)%2c+Massachusetts%2c+United+States&GAD1_O=&GAD2_O=&GAD3_O=02139+(postal+code)%2c+Massachusetts%2c+United+States&GAD4_O=&radius=5&countryID=244&dataSource=MapPoint.NA" class="urlextern" title="http://www.starbucks.com/retail/locator/MapResults.aspx?a=1&amp;StoreKey=93728&amp;IC_O=42.3599350625432%3a-71.1021394862385%3a32%3a02139+(postal+code)%2c+Massachusetts%2c+United+States&amp;GAD1_O=&amp;GAD2_O=&amp;GAD3_O=02139+(postal+code)%2c+Massachusetts%2c+United+States&amp;GAD4_O=&amp;radius=5&amp;countryID=244&amp;dataSource=MapPoint.NA"  rel="nofollow">Kendal Square Starbucks</a>.
  </p>
  
  </div>
  <!-- SECTION [15657-16857] -->
  <h2><a name="okay_how_do_i_start_using_geda" id="okay_how_do_i_start_using_geda">Okay, how do I start using gEDA?</a></h2>
  <div class="level2">
  
  <p>
  The most important thing to do is to read and understand Bill Wilsonâ??s excellent <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">gschem -&gt; gsch2pcb -&gt; PCB</a> tutorial. This should get you started.
  </p>
  
  <p>
  Also be sure to check out the other <a href="http://geda.seul.org/docs"; class="urlextern" title="http://geda.seul.org/docs";  rel="nofollow">gEDA documentation</a>. An installation guide is contained in this Wiki, as is some general information about how to use the tools. Spend some time browsing, download the gEDA Suite, and try it out for yourself! 
  </p>
  
  </div>
  <!-- SECTION [16858-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_fbabgapp.html
  
  Index: geda_fbabgapp.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#forward_backward_annotation_between_geda_gaf_and_pads_powerpcb" class="toc">Forward/Backward Annotation Between gEDA/gaf and PADS PowerPCB</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#forward_annotation_of_geda_schematic_changes_to_pads_powerpcb_layout" class="toc">Forward Annotation of gEDA Schematic Changes to PADS PowerPCB Layout</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#detailed_forward_annotation_procedure" class="toc">Detailed Forward Annotation Procedure</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#back_annotation_of_pads_powerpcb_layout_changes_to_geda_schematic" class="toc">Back Annotation of PADS PowerPCB Layout Changes to gEDA Schematic</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#detailed_backannotation_procedure" class="toc">Detailed Backannotation Procedure</a></span></div></li></ul>
  </li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="forward_backward_annotation_between_geda_gaf_and_pads_powerpcb" id="forward_backward_annotation_between_geda_gaf_and_pads_powerpcb">Forward/Backward Annotation Between gEDA/gaf and PADS PowerPCB</a></h1>
  <div class="level1">
  
  <p>
  by: Dan McMahill
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  March 6th, 2003
  </p>
  
  </div>
  <!-- SECTION [1-191] -->
  <h2><a name="forward_annotation_of_geda_schematic_changes_to_pads_powerpcb_layout" id="forward_annotation_of_geda_schematic_changes_to_pads_powerpcb_layout">Forward Annotation of gEDA Schematic Changes to PADS PowerPCB Layout</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [192-272] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  Forward annotation is the process of updating a layout to reflect changes made in the schematic. This process is used when, for example, a new component is added to a schematic and needs to be included in the layout. This section describes how to forward annotate changes in a gEDA schematic to a PADS PowerPCB layout.<br/>
   PADS implements forward annotation through the use of an ECO (Engineering Change Order) file. The ECO file describes the differences between a current design and the desired design. PADS generates the ECO file by performing a netlist comparison between a new netlist file and the netlist contained in the current layout.
  </p>
  
  </div>
  <!-- SECTION [273-936] -->
  <h2><a name="detailed_forward_annotation_procedure" id="detailed_forward_annotation_procedure">Detailed Forward Annotation Procedure</a></h2>
  <div class="level2">
  
  <p>
  This procedure assumes you have a board layout open in PADS and that you have made your schematic changes in gschem. For the purposes of illustration, assume your schematic is split into two pages in the files pg1.sch and pg2.sch.
  </p>
  <ul>
  <li class="level1"><div class="li"> Create an updated PADS netlist by running:<br/>
   <strong><code>gnetlist -g pads -o mynet.asc pg1.sch pg2.sch</code></strong><br/>
   This will create the netlist file <strong><code>mynet.asc</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> Make a backup copy of your PADS layout in case things fail in a destructive way.</div>
  </li>
  <li class="level1"><div class="li"> From within PADS, choose the &ldquo;Tools &rarr; Compare Netlist&rdquo; menu item and choose the following options in the form:</div>
  </li>
  </ul>
  <table class="inline">
  	<tr>
  		<td>original design to compare</td><td>use current PCB design</td>
  	</tr>
  	<tr>
  		<td>new design with changes</td><td>mynet.asc</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>generate differences report</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>generate eco file</td>
  	</tr>
  	<tr>
  		
  	</tr>
  	<tr>
  		<td colspan="2">comparison options</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>compare only ECO registered parts</td>
  	</tr>
  	<tr>
  		<td colspan="2"> </td>
  	</tr>
  	<tr>
  		<td colspan="2">attribute comparison level</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>ignore all attributes</td>
  	</tr>
  </table>
  <br />
  
  <p>
   Click the OK button to create the ECO file.
  </p>
  <ul>
  <li class="level1"><div class="li"> Examine the ECO file to make sure it looks ok (the ECO file is a text file which can be viewed with any text editor).</div>
  </li>
  <li class="level1"><div class="li"> From within PADS, choose the &ldquo;File &rarr; Import...&rdquo; menu item. Locate and choose the ECO file created previously.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [937-2135] -->
  <h2><a name="back_annotation_of_pads_powerpcb_layout_changes_to_geda_schematic" id="back_annotation_of_pads_powerpcb_layout_changes_to_geda_schematic">Back Annotation of PADS PowerPCB Layout Changes to gEDA Schematic</a></h2>
  <div class="level2">
  
  <p>
  Backannotation is the process of updating schematics to reflect changes made in the layout. This process is used, for example, when the reference designators have been renumbered on the layout, when pins have been swapped (e.g., on an AND gate), or slots have been swapped (e.g., on a multi-gate package). This section describes how to backannotate changes in a PADS PowerPCB layout to a gEDA schematic. The PADS PowerPCB tool supports three types of schematic backannotation:
  </p>
  <ol>
  <li class="level1"><div class="li"> Reference designator changes. This is often times used at the end of a layout to give components which are geographically close a set of reference designators which are numerically close.</div>
  </li>
  <li class="level1"><div class="li"> Slot swapping. This is commonly found in digital designs where there may be multiple identical gates in a single package. For example, you may wish to swap which slot is used in a hex inverter.</div>
  </li>
  <li class="level1"><div class="li"> Pin swapping. During layout, the designer may wish to swap equivalent pins on a chip. For example, the two inputs on a NAND gate.</div>
  </li>
  </ol>
  
  <p>
   Currently only reference designator changes are automatically processed by the PADS to gschem backannotation tool. The slot and pin swapping changes are provided in a report which the schematic designer must use to manually correct the schematic.
  </p>
  
  </div>
  <!-- SECTION [2136-3463] -->
  <h3><a name="detailed_backannotation_procedure" id="detailed_backannotation_procedure">Detailed Backannotation Procedure</a></h3>
  <div class="level3">
  
  <p>
  This procedure assumes you have a board layout open in PADS. For the purposes of illustration, assume your schematic is split into two pages in the files pg1.sch and pg2.sch.
  </p>
  <ul>
  <li class="level1"><div class="li"> Create an up to date PADS netlist by running:<br/>
   <strong><code>gnetlist -g pads -o mynet.asc pg1.sch pg2.sch</code></strong><br/>
   This will create the netlist file <strong><code>mynet.asc</code></strong>.</div>
  </li>
  <li class="level1"><div class="li"> From within PADS, choose the &ldquo;Tools &rarr; Compare Netlist&rdquo; menu item and choose the following options in the form:</div>
  </li>
  </ul>
  <table class="inline">
  	<tr>
  		<td>original design to compare</td><td>mynet.asc</td>
  	</tr>
  	<tr>
  		<td>new design with changes</td><td>use current PCB design</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>generate differences report</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>generate eco file</td>
  	</tr>
  	<tr>
  		<td colspan="2"> </td>
  	</tr>
  	<tr>
  		<td colspan="2">comparison options</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>compare only ECO registered parts</td>
  	</tr>
  	<tr>
  		<td colspan="2"> </td>
  	</tr>
  	<tr>
  		<td colspan="2">attribute comparison level</td>
  	</tr>
  	<tr>
  		<td>â??</td><td>ignore all attributes</td>
  	</tr>
  </table>
  <br />
  
  <p>
   Click the OK button to create the ECO file. 
  </p>
  <ul>
  <li class="level1"><div class="li"> Examine the ECO file to make sure it looks ok (the ECO file is a text file which can be viewed with any text editor).</div>
  </li>
  <li class="level1"><div class="li"> Make a backup copy of your gEDA schematic files in case things fail in a destructive way.</div>
  </li>
  <li class="level1"><div class="li"> Run:<br/>
   <strong><code>pads_backannotate file.eco pg1.sch pg2.sch | tee backanno.log</code></strong><br/>
   where <strong><code>file.eco</code></strong> is the name of the ECO file created previously and <strong><code>pg1.sch</code></strong> and <strong><code>pg2.sch</code></strong> are all of your schematic pages. This will apply the reference designator change portion of the ECO file and also generate a list of pin and slot swapping which must be performed by hand. The file <strong><code>backanno.log</code></strong> will contain a log of the session that can be refered to when performing the pin and slot swapping.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3464-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_fc1.html
  
  Index: geda_fc1.html
  ===================================================================
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
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  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#installer_2005080x_on_fedora_core_1_install_notes" class="toc">Installer 2005080X on Fedora Core 1 install notes</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#prerequisites" class="toc">Prerequisites:</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#problems" class="toc">Problems:</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installer_2005080x_on_fedora_core_1_install_notes" id="installer_2005080x_on_fedora_core_1_install_notes">Installer 2005080X on Fedora Core 1 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-64] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  When you install FC1, make sure you install the â??workstationâ?? version, and not the â??desktopâ?? version. (You are presented with this choice when you first install the distribution off of the distribution media.) The â??workstationâ?? version includes important header files and other tools which are necessary to build many components of the gEDA Suite using the installer.
  </p>
  
  </div>
  <!-- SECTION [65-472] -->
  <h2><a name="problems" id="problems">Problems:</a></h2>
  <div class="level2">
  
  <p>
  The installer has been thoroughly tested on this platform. No problems are known, and none have been reported.
  </p>
  
  </div>
  <!-- SECTION [473-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_fc2.html
  
  Index: geda_fc2.html
  ===================================================================
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#installer_2005080x_on_fedora_core_2_install_notes" class="toc">Installer 2005080X on Fedora Core 2 install notes</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#prerequisites" class="toc">Prerequisites:</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#problems" class="toc">Problems:</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installer_2005080x_on_fedora_core_2_install_notes" id="installer_2005080x_on_fedora_core_2_install_notes">Installer 2005080X on Fedora Core 2 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-64] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  When you install FC2, make sure you install the â??workstationâ?? version, and not the â??desktopâ?? version. (You are presented with this choice when you first install the distribution off of the distribution media.) The â??workstationâ?? version includes important header files and other tools which are necessary to build many components of the gEDA Suite using the installer.
  </p>
  
  </div>
  <!-- SECTION [65-472] -->
  <h2><a name="problems" id="problems">Problems:</a></h2>
  <div class="level2">
  
  <p>
  The installer has been thoroughly tested on this platform. No problems are known, and none have been reported.
  </p>
  
  </div>
  <!-- SECTION [473-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_fc3.html
  
  Index: geda_fc3.html
  ===================================================================
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  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#installer_2005080x_on_fedora_core_3_install_notes" class="toc">Installer 2005080X on Fedora Core 3 install notes</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#prerequisites" class="toc">Prerequisites:</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#problems" class="toc">Problems:</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installer_2005080x_on_fedora_core_3_install_notes" id="installer_2005080x_on_fedora_core_3_install_notes">Installer 2005080X on Fedora Core 3 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-64] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  When you install FC3, make sure you install the â??workstationâ?? version, and not the â??desktopâ?? version. (You are presented with this choice when you first install the distribution off of the distribution media.) The â??workstationâ?? version includes important header files and other tools which are necessary to build many components of the gEDA Suite using the installer.
  </p>
  
  </div>
  <!-- SECTION [65-472] -->
  <h2><a name="problems" id="problems">Problems:</a></h2>
  <div class="level2">
  
  <p>
  No problems are known, and none have been reported.
  </p>
  
  </div>
  <!-- SECTION [473-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_fc4.html
  
  Index: geda_fc4.html
  ===================================================================
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  <li class="level1"><div class="li"><span class="li"><a href="#installer_2005080x_on_fedora_core_4_install_notes" class="toc">Installer 2005080X on Fedora Core 4 install notes</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#prerequisites" class="toc">Prerequisites:</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#problems" class="toc">Problems:</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installer_2005080x_on_fedora_core_4_install_notes" id="installer_2005080x_on_fedora_core_4_install_notes">Installer 2005080X on Fedora Core 4 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-64] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  When you install FC4, make sure you install the â??workstationâ?? version, and not the â??desktopâ?? version. (You are presented with this choice when you first install the distribution off of the distribution media.) The â??workstationâ?? version includes important header files and other tools which are necessary to build many components of the gEDA Suite using the installer.
  </p>
  
  <p>
  Also, the following additional RPMs are required:
  </p>
  <ul>
  <li class="level1"><div class="li"> guile-1.6.7-devel</div>
  </li>
  <li class="level1"><div class="li"> gettext-XX-devel.</div>
  </li>
  <li class="level1"><div class="li"> compat-gcc-3.2.3-47.fc4.i386.rpm</div>
  </li>
  <li class="level1"><div class="li"> compat-gcc-32-c++-3.2.3-47.fc4.i386.rpm</div>
  </li>
  <li class="level1"><div class="li"> compat-libstdc++-33-0:3.2.3-47.fc4.i386.rpm (installed automatically when g++ is installed by rpm)</div>
  </li>
  </ul>
  
  <p>
   These RPMs are not automatically installed by RedHatâ??s installer; you need to install them manually. The devel packages live on the 4th FC4 disk. The gcc compatability compiler lives on the 3rd FC4 disk. Install all these packages before trying to build the gEDA Suite.
  </p>
  
  <p>
  Before installing the gEDA Suite on an FC4 system, you should set the CC environment variable to point to gcc32. This is explained further in the â??Problemsâ?? section below.
  </p>
  
  </div>
  <!-- SECTION [65-1201] -->
  <h2><a name="problems" id="problems">Problems:</a></h2>
  <div class="level2">
  
  <p>
  The 200508XX installer will fail on FC4 systems. There seem to be several independent problems:
  </p>
  <ol>
  <li class="level1"><div class="li"> The installer doesnâ??t find guile, even though it comes pre-installed on the platform.<br/>
   The problem here is that the installer tries to find guile by issuing the â??guile-configâ?? command. This command lives in the guile-devel RPM which is not installed by default (see above). To fix the problem, install the guile-devel RPM which lives on the FC4 install CD no. 4.</div>
  </li>
  <li class="level1"><div class="li"> The installer doesnâ??t find gettext, even though it comes pre-installed on the platform. Gettext is used by gschem, so this error is raised during the configure stage for gschem.<br/>
   Again, the gettext header files live in the gettext-devel RPM which is not installed by default (see above). To fix this problem, install the gettext-devel RPM which lives on the FC4 install CD no. 4.</div>
  </li>
  <li class="level1"><div class="li"> Many different applications (e.g. GTKWave, GSpiceUI, Icarus Verilog) fail during compilation. The error message typically says something about a problem involving a â??typeâ??.</div>
  </li>
  </ol>
  
  <p>
   This problem obtains because FC4 incorporates the new gcc-4.0 compiler. Gcc-4.0 incorporates much stricter type checking than the older gcc versions. This has caused many open-source applications to fail to compile.
  </p>
  
  <p>
  Fortunately, RedHat still provides the older version of gcc on the FC4 disks. This version of gcc is called â??gcc32â??. It is not installed as part of the normal installation, so you must install it yourself. The RPM lives on the FC4 install media, disk 3, and is called â??compat-gcc-32-3.2.3-47.fc4.i386.rpmâ??. Allow rpm to install any dependencies it finds.
  </p>
  
  <p>
  A similar situation holds for the C++ compiler g++. You need to install the older version too; get it on the FC4 disk 4. It is called â??compat-gcc-32-c++-3.2.3-47.fc4.i386.rpmâ??. Also install any dependencies found by rpm when you install these pacakges.
  </p>
  
  <p>
  Once they are installed, set the gcc environment variables as follows:
  </p>
  
  <p>
  for bash: 
  </p>
  <pre class="code">export CC=gcc32
  export CXX=g++32</pre>
  
  <p>
  for csh: 
  </p>
  <pre class="code">setenv CC gcc32
  setenv CXX g++32</pre>
  
  <p>
  and then run the installer. Make sure you run the installer from the same window as where you set the CC environment variable!
  </p>
  
  </div>
  <!-- SECTION [1202-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_file_format_spec.html
  
  Index: geda_file_format_spec.html
  ===================================================================
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  <li class="level1"><div class="li"><span class="li"><a href="#geda_gaf_file_format_document" class="toc">gEDA/gaf File Format Document</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#coordinate_space" class="toc">Coordinate Space</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#filenames" class="toc">Filenames</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#object_types" class="toc">Object types</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#version" class="toc">version</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#line" class="toc">line</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#picture" class="toc">picture</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#box" class="toc">box</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#circle" class="toc">circle</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#arc" class="toc">arc</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#text" class="toc">text</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#net" class="toc">net</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#bus" class="toc">bus</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pin" class="toc">pin</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#component" class="toc">component</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#font" class="toc">font</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#colors" class="toc">Colors</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#attributes" class="toc">Attributes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#embedded_components" class="toc">Embedded Components</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_revision_history" class="toc">Document Revision History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gaf_file_format_document" id="geda_gaf_file_format_document">gEDA/gaf File Format Document</a></h1>
  <div class="level1">
  
  <p>
  by: Ales V. Hvezda, ahvezda@xxxxxxxxxxxxx
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  December 31st, 2003
  </p>
  
  </div>
  <!-- SECTION [1-187] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  This file is the official documentation for the file formats in gEDA/gaf (gschem And Friends). The primary file format used in gEDA/gaf is the schematic/symbol format. Files which end with .sch or .sym are schematics or symbol files. Until there is another file type in gEDA/gaf, then this document will only cover the symbol/schematic file format.<br/>
   This file format document is current as of gEDA/gaf version 20040111. This document covers file format version 1.<br/>
   Note, this file format and any other file formats associated with gEDA are placed under the General Public License (<acronym title="GNU General Public License">GPL</acronym>) version 2.0. The gEDA/gaf symbol and schematic file format is Copyright (C) 1998-2004 Ales Hvezda.
  </p>
  
  </div>
  <!-- SECTION [188-896] -->
  <h2><a name="coordinate_space" id="coordinate_space">Coordinate Space</a></h2>
  <div class="level2">
  
  <p>
  All coordinates are in mils (1/1000 or an inch). This is an arbitrary decision. Remember in there is no concept of physical lengths/dimensions in schematics and symbols (for schematic capture only).<br/>
  
  </p>
  <ul>
  <li class="level1"><div class="li"> Origin is in lower left hand corner.</div>
  </li>
  <li class="level1"><div class="li"> The size of the coordinate space is unlimited, but it is recommended that all objects stay within (120.0, 90.0) (x, y inches).</div>
  </li>
  <li class="level1"><div class="li"> It is generally advisable to have positive x and y coordinates, however, negative coordinates work too, but not recommended.</div>
  </li>
  </ul>
  
  <p>
   The following figure shows how the coordinate space is setup: 
  </p>
  <table class="inline">
  	<tr>
  		<td><a href="_detail/geda_coordinatespace.html" class="media" title="geda:coordinatespace.jpg"><img src="_media/geda_coordinatespace.jpg" class="mediaright" title=":geda:coordinatespace.jpg " alt=":geda:coordinatespace.jpg " /></a></td>
  	</tr>
  </table>
  <br />
  
  <p>
   X axis increases going to the right. Y axis increase going up. Coordinate system is landscape and corresponds to a sheet of paper turned on its side.
  </p>
  
  </div>
  <!-- SECTION [897-1703] -->
  <h2><a name="filenames" id="filenames">Filenames</a></h2>
  <div class="level2">
  
  <p>
  Symbols end in .sym. The only symbol filename convention that is used in gEDA/gaf is that if there are multiple instances of a symbol with the same name (like a 7400), then a -1, -2, -3, ... -N suffix is added to the end of the filename. Example: 7400-1.sym, 7400-2.sym, 7400-3.sym...<br/>
   Schematics end in .sch. There used to be a schematic filename convention (adding a -1 .. -N to the end of the basename), but this convention is now obsolete. Schematic filenames can be anything that makes sense to the creator.
  </p>
  
  </div>
  <!-- SECTION [1704-2240] -->
  <h2><a name="object_types" id="object_types">Object types</a></h2>
  <div class="level2">
  
  <p>
  A schematic/symbol file for gEDA/gaf consists of:
  </p>
  <ul>
  <li class="level1"><div class="li"> A version (v) as the first item in the file. This is required.</div>
  </li>
  <li class="level1"><div class="li"> Any number of objects and the correct data. Objects are specified by an &ldquo;object type&rdquo;</div>
  </li>
  <li class="level1"><div class="li"> Most objects are a single line, however text objects are two lines long.</div>
  </li>
  <li class="level1"><div class="li"> No blank lines at the end of the file (these are ignored by the tools)</div>
  </li>
  <li class="level1"><div class="li"> For all enumerated types in the gEDA/gaf file formats, the field takes on the numeric value.</div>
  </li>
  </ul>
  
  <p>
   The &ldquo;object type&rdquo; id is a single letter and this id must start in the first column. The object type id is case sensitive.<br/>
   The schematic and symbol files share the same file layout. A symbol is nothing more than a collection of primitive objects (lines, boxes, circles, arcs, text, and pins). A schematic is a collection of symbols (components), nets, and buses.<br/>
   The following sections describe the specifics of each recognized object type. Each section has the name of the object, which file type (sch/sym) the object can appear in, the format of the data, a description of each individual field, details and caveats of the fields, and finally an example with description.<br/>
   For information on the color index (which is used in practically all objects), see the Color section.
  </p>
  
  </div>
  <!-- SECTION [2241-3504] -->
  <h3><a name="version" id="version">version</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type version</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>v</td>
  	</tr>
  	<tr>
  		<td>version</td><td>int</td><td>version of gEDA/gaf that wrote this file</td>
  	</tr>
  	<tr>
  		<td>fileformat_version</td><td>int</td><td>gEDA/gaf file format version number</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The type is a lower case &ldquo;v&rdquo; (as in Victor).</div>
  </li>
  <li class="level1"><div class="li"> This object must be in every file used or created by the gEDA/gaf tools.</div>
  </li>
  <li class="level1"><div class="li"> The format of the first version field is YYYYMMDD.</div>
  </li>
  <li class="level1"><div class="li"> The version number is not an arbitrary timestamp. Do not make up a version number and expect the tools to behave properly.</div>
  </li>
  <li class="level1"><div class="li"> The &ldquo;version of gEDA/gaf that wrote this file&rdquo; was used in all versions of gEDA/gaf up to 20030921 as the file formats version. This field should no longer be used to determine the file format. It is used for information purposes only now.</div>
  </li>
  <li class="level1"><div class="li"> Starting at and after gEDA/gaf version 20031004, the fileformat version field is used to determine the file format version. All file format code should key off of this field.</div>
  </li>
  <li class="level1"><div class="li"> fileformat version increases when the file format changes.</div>
  </li>
  <li class="level1"><div class="li"> The starting point for fileformat version is 1.</div>
  </li>
  <li class="level1"><div class="li"> fileformat version is just an integer with no minor number.</div>
  </li>
  <li class="level1"><div class="li"> Valid versions include: 19990601, 19990610, 19990705, 19990829, 19990919, 19991011, 20000220, 20000704, 20001006, 20001217, 20010304, 20010708, 20010722, 20020209, 20020414, 20020527, 20020825, 20021103, 20030223, 20030525, 20030901, 20040111, 20040710, 20041228, 20050313, 20050820, 20060123, 20060821</div>
  </li>
  <li class="level1"><div class="li"> <acronym title="Concurrent Versions System">CVS</acronym> or test versions (should not be used): 20030921, 20031004, 20031019, 20031231, 20050814</div>
  </li>
  <li class="level1"><div class="li"> Keep in mind that each of the above listed versions might have had file format variations. This document only covers the last version&rsquo;s file format.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">v 20040111 1</pre>
  
  </div>
  <!-- SECTION [3505-5249] -->
  <h3><a name="line" id="line">line</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x1 y1 x2 y2 color width capstyle dashstyle dashlength dashspace</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>L</td>
  	</tr>
  	<tr>
  		<td>x1</td><td>int/mils</td><td>First X coordinate</td>
  	</tr>
  	<tr>
  		<td>y1</td><td>int/mils</td><td>First Y coordinate</td>
  	</tr>
  	<tr>
  		<td>x2</td><td>int/mils</td><td>Second X coordinate</td>
  	</tr>
  	<tr>
  		<td>y2</td><td>int/mils</td><td>Second Y coordinate</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of line</td>
  	</tr>
  	<tr>
  		<td>capstyle</td><td>int</td><td>Line cap style</td>
  	</tr>
  	<tr>
  		<td>dashstyle</td><td>int</td><td>Type of dash style</td>
  	</tr>
  	<tr>
  		<td>dashlength</td><td>int</td><td>Length of dash</td>
  	</tr>
  	<tr>
  		<td>dashspace</td><td>int</td><td>Space inbetween dashes</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The capstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> END NONE = 0</div>
  </li>
  <li class="level2"><div class="li"> END SQUARE = 1</div>
  </li>
  <li class="level2"><div class="li"> END ROUND = 2</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> TYPE SOLID = 0</div>
  </li>
  <li class="level2"><div class="li"> TYPE DOTTED = 1</div>
  </li>
  <li class="level2"><div class="li"> TYPE DASHED = 2</div>
  </li>
  <li class="level2"><div class="li"> TYPE CENTER = 3</div>
  </li>
  <li class="level2"><div class="li"> TYPE PHANTOM = 4</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashlength parameter is not used for TYPE SOLID and TYPE DOTTED. This parameter should take on a value of -1 in these cases.</div>
  </li>
  <li class="level1"><div class="li"> The dashspace paramater is not used for TYPE SOLID. This parameter should take on a value of -1 in these case.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">L 23000 69000 28000 69000 3 40 0 1 -1 75</pre>
  
  <p>
  A line segment from (23000, 69000) to (28000, 69000) with color index 3, 40 mils thick, no cap, dotted line style, and with a spacing of 75 mils in between each dot.
  </p>
  
  </div>
  <!-- SECTION [5250-6484] -->
  <h3><a name="picture" id="picture">picture</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x1 y1 width height angle ratio mirrored embedded
  filename
  encoded picture data
  encoded picture end</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>G</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>Lower left X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>Lower left Y coordinate</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of the picture</td>
  	</tr>
  	<tr>
  		<td>height</td><td>int/mils</td><td>Height of the picture</td>
  	</tr>
  	<tr>
  		<td>angle</td><td>int/degrees</td><td>Angle of the picture</td>
  	</tr>
  	<tr>
  		<td>mirrored</td><td>char</td><td>Mirrored or normal picture</td>
  	</tr>
  	<tr>
  		<td>embedded</td><td>char</td><td>Embedded or link to the picture file</td>
  	</tr>
  	<tr>
  		<td>filename</td><td>string</td><td>path and filename of a not embedded picture</td>
  	</tr>
  	<tr>
  		<td>encoded picture data</td><td>string</td><td>Serialized picture encoded using base64</td>
  	</tr>
  	<tr>
  		<td>encoded picture end</td><td>string</td><td>A line containing only a dot character</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> This object is a picture object. The first line contains all the picture parameters, and the second line is the path and filename of the picture. The filename is not used if the picture is embedded.</div>
  </li>
  <li class="level1"><div class="li"> The angle of the picture can only take on one of the following values: 0, 90, 180, 270.</div>
  </li>
  <li class="level1"><div class="li"> The mirrored field is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> NOT MIRRORED = 0</div>
  </li>
  <li class="level2"><div class="li"> MIRRORED = 1</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The embedded field is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> NOT EMBEDDED = 0</div>
  </li>
  <li class="level2"><div class="li"> EMBEDDED = 1 (not yet supported)</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The encoded picture and encoded picture end fields are only in the file if the picture is embedded in the schematic:</div>
  <ul>
  <li class="level2"><div class="li"> encoded picture data: This is a multiple line field. The picture is serialized and then encoded using base64. This way the encoded data uses only printable characters. This field is the result of these two operations.</div>
  </li>
  <li class="level2"><div class="li"> encoded picture end : A line containing only a single dot &lsquo;.&rsquo; character marks the end of the encoded picture data.</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">G 16900 35800 1400 2175 0 6.435331e-01 0 0
  ../bitmaps/logo.jpg</pre>
  
  <p>
  A picture object with the lower left corner at (16900, 35800). The width of the image is 1400 mils, and its height is 2175 mils (i.e.: the ratio is 0.6353). The picture rotation is 0 degrees and the picture is not mirrored, neither embedded.<br/>
   The picture path and filename is showed in the second line.<br/>
   Example:<br/>
   
  </p>
  <pre class="code">G 16900 35800 1400 2175 0 6.435331e-01 0 1
  ../bitmaps/logo.jpg
  AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
  BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
  .</pre>
  
  <p>
  A picture object with the lower left corner at (16900, 35800). The width of the image is 1400 mils, and its height is 2175 mils (i.e.: the ratio is 0.6353).<br/>
   The picture rotation is 0 degrees, it is not mirrored, and it is embedded.<br/>
   The picture path and filename is showed in the second line. Since this is an embedded picture, the filename and path are not used.<br/>
   The encoded picture data is only an example (it is not real data). The last line containing a single dot &lsquo;.&rsquo; character marks the end of the encoded picture data.
  </p>
  
  </div>
  <!-- SECTION [6485-9270] -->
  <h3><a name="box" id="box">box</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x y width height color width capstyle dashtype dashlength dashspace
  filltype fillwidth angle1 pitch1 angle2 pitch2</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>B</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>Lower left hand X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>Lower left hand Y coordinate</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of the box (x direction)</td>
  	</tr>
  	<tr>
  		<td>height</td><td>int/mils</td><td>Height of the box (y direction)</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of lines</td>
  	</tr>
  	<tr>
  		<td>capstyle</td><td>int/mils</td><td>Line cap style</td>
  	</tr>
  	<tr>
  		<td>dashstyle</td><td>int</td><td>Type of dash style</td>
  	</tr>
  	<tr>
  		<td>dashlength</td><td>int/mils</td><td>Length of dash</td>
  	</tr>
  	<tr>
  		<td>dashspace</td><td>int/mils</td><td>Space inbetween dashes</td>
  	</tr>
  	<tr>
  		<td>filltype</td><td>int</td><td>Type of fill</td>
  	</tr>
  	<tr>
  		<td>fillwidth</td><td>int/mils</td><td>Width of the fill lines</td>
  	</tr>
  	<tr>
  		<td>angle1</td><td>int/degrees</td><td>First angle of fill</td>
  	</tr>
  	<tr>
  		<td>pitch1</td><td>int/mils</td><td>First pitch/spacing of fill</td>
  	</tr>
  	<tr>
  		<td>angle2</td><td>int/degrees</td><td>Second angle of fill</td>
  	</tr>
  	<tr>
  		<td>pitch2</td><td>int/mils</td><td>Second pitch/spacing of fill</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The capstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> END NONE = 0</div>
  </li>
  <li class="level2"><div class="li"> END SQUARE = 1</div>
  </li>
  <li class="level2"><div class="li"> END ROUND = 2</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> TYPE SOLID = 0</div>
  </li>
  <li class="level2"><div class="li"> TYPE DOTTED = 1</div>
  </li>
  <li class="level2"><div class="li"> TYPE DASHED = 2</div>
  </li>
  <li class="level2"><div class="li"> TYPE CENTER = 3</div>
  </li>
  <li class="level2"><div class="li"> TYPE PHANTOM = 4</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashlength parameter is not used for TYPE SOLID and TYPE DOTTED. This parameter should take on a value of -1 in these cases.</div>
  </li>
  <li class="level1"><div class="li"> The dashspace paramater is not used for TYPE SOLID. This parameter should take on a value of -1 in these case.</div>
  </li>
  <li class="level1"><div class="li"> The filltype parameter is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> FILLING HOLLOW = 0</div>
  </li>
  <li class="level2"><div class="li"> FILLING FILL = 1</div>
  </li>
  <li class="level2"><div class="li"> FILLING MESH = 2</div>
  </li>
  <li class="level2"><div class="li"> FILLING HATCH = 3</div>
  </li>
  <li class="level2"><div class="li"> FILLING VOID = 4 unused</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> If the filltype is 0 (FILLING HOLLOW), then all the fill parameters should take on a value of -1.</div>
  </li>
  <li class="level1"><div class="li"> The fill type FILLING FILL is a solid color fill.</div>
  </li>
  <li class="level1"><div class="li"> The two pairs of pitch and spacing control the fill or hatch if the fill type is FILLING MESH.</div>
  </li>
  <li class="level1"><div class="li"> Only the first pair of pitch and spacing are used if the fill type is FILLING HATCH.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">B 33000 67300 2000 2000 3 60 0 2 75 50 0 -1 -1 -1 -1 -1</pre>
  
  <p>
  A box with the lower left hand corner at (33000, 67300) and a width and height of (2000, 2000), color index 3, line width of 60 mils, no cap, dashed line type, dash length of 75 mils, dash spacing of 50 mils, no fill, rest parameters unset.
  </p>
  
  </div>
  <!-- SECTION [9271-11477] -->
  <h3><a name="circle" id="circle">circle</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x y radius color width capstyle dashtype dashlength dashspace
  filltype fillwidth angle1 pitch1 angle2 pitch2</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>V</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>Center X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>Center Y coordinate</td>
  	</tr>
  	<tr>
  		<td>radius</td><td>int/mils</td><td>Radius of the circle</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of circle line</td>
  	</tr>
  	<tr>
  		<td>capstyle</td><td>int/mils</td><td>0 unused</td>
  	</tr>
  	<tr>
  		<td>dashstyle</td><td>int</td><td>Type of dash style</td>
  	</tr>
  	<tr>
  		<td>dashlength</td><td>int/mils</td><td>Length of dash</td>
  	</tr>
  	<tr>
  		<td>dashspace</td><td>int/mils</td><td>Space inbetween dashes</td>
  	</tr>
  	<tr>
  		<td>filltype</td><td>int</td><td>Type of fill</td>
  	</tr>
  	<tr>
  		<td>fillwidth</td><td>int/mils</td><td>Width of the fill lines</td>
  	</tr>
  	<tr>
  		<td>angle1</td><td>int/degrees</td><td>First angle of fill</td>
  	</tr>
  	<tr>
  		<td>pitch1</td><td>int/mils</td><td>First pitch/spacing of fill</td>
  	</tr>
  	<tr>
  		<td>angle2</td><td>int/degrees</td><td>Second angle of fill</td>
  	</tr>
  	<tr>
  		<td>pitch2</td><td>int/mils</td><td>Second pitch/spacing of fill</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The dashstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> TYPE SOLID = 0</div>
  </li>
  <li class="level2"><div class="li"> TYPE DOTTED = 1</div>
  </li>
  <li class="level2"><div class="li"> TYPE DASHED = 2</div>
  </li>
  <li class="level2"><div class="li"> TYPE CENTER = 3</div>
  </li>
  <li class="level2"><div class="li"> TYPE PHANTOM = 4</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashlength parameter is not used for TYPE SOLID and TYPE DOTTED. This parameter should take on a value of -1 in these cases.</div>
  </li>
  <li class="level1"><div class="li"> The dashspace paramater is not used for TYPE SOLID. This parameter should take on a value of -1 in these case.</div>
  </li>
  <li class="level1"><div class="li"> The filltype parameter is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> FILLING HOLLOW = 0</div>
  </li>
  <li class="level2"><div class="li"> FILLING FILL = 1</div>
  </li>
  <li class="level2"><div class="li"> FILLING MESH = 2</div>
  </li>
  <li class="level2"><div class="li"> FILLING HATCH = 3</div>
  </li>
  <li class="level2"><div class="li"> FILLING VOID = 4 unused</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> If the filltype is 0 (FILLING HOLLOW), then all the fill parameters should take on a value of -1.</div>
  </li>
  <li class="level1"><div class="li"> The fill type FILLING FILL is a solid color fill.</div>
  </li>
  <li class="level1"><div class="li"> The two pairs of pitch and spacing control the fill or hatch if the fill type is FILLING MESH.</div>
  </li>
  <li class="level1"><div class="li"> Only the first pair of pitch and spacing are used if the fill type is FILLING HATCH.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">V 38000 67000 900 3 0 0 2 75 50 2 10 20 30 90 50</pre>
  
  <p>
  A circle with the center at (38000, 67000) and a radius of 900 mils, color index 3, line width of 0 mils (smallest size), no cap, dashed line type, dash length of 75 mils, dash spacing of 50 mils, mesh fill, 10 mils thick mesh lines, first mesh line: 20 degrees, with a spacing of 30 mils, second mesh line: 90 degrees, with a spacing of 50 mils.
  </p>
  
  </div>
  <!-- SECTION [11478-13603] -->
  <h2><a name="arc" id="arc">arc</a></h2>
  <div class="level2">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x y radius startangle sweepangle color width capstyle dashtype
  dashlength dashspace</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>A</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>Center X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>Center Y coordinate</td>
  	</tr>
  	<tr>
  		<td>radius</td><td>int/mils</td><td>Radius of the arc</td>
  	</tr>
  	<tr>
  		<td>startangle</td><td>int/degrees</td><td>Starting angle of the arc</td>
  	</tr>
  	<tr>
  		<td>sweepangle</td><td>int/degrees</td><td>Amount the arc sweeps</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of circle line</td>
  	</tr>
  	<tr>
  		<td>capstyle</td><td>int</td><td>Cap style</td>
  	</tr>
  	<tr>
  		<td>dashstyle</td><td>int</td><td>Type of dash style</td>
  	</tr>
  	<tr>
  		<td>dashlength</td><td>int/mils</td><td>Length of dash</td>
  	</tr>
  	<tr>
  		<td>dashspace</td><td>int/mils</td><td>Space inbetween dashes</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The startangle can be negative, but not recommended.</div>
  </li>
  <li class="level1"><div class="li"> The sweepangle can be negative, but not recommended.</div>
  </li>
  <li class="level1"><div class="li"> The capstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> END NONE = 0</div>
  </li>
  <li class="level2"><div class="li"> END SQUARE = 1</div>
  </li>
  <li class="level2"><div class="li"> END ROUND = 2</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashstyle is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> TYPE SOLID = 0</div>
  </li>
  <li class="level2"><div class="li"> TYPE DOTTED = 1</div>
  </li>
  <li class="level2"><div class="li"> TYPE DASHED = 2</div>
  </li>
  <li class="level2"><div class="li"> TYPE CENTER = 3</div>
  </li>
  <li class="level2"><div class="li"> TYPE PHANTOM = 4</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The dashlength parameter is not used for TYPE SOLID and TYPE DOTTED. This parameter should take on a value of -1 in these cases.</div>
  </li>
  <li class="level1"><div class="li"> The dashspace paramater is not used for TYPE SOLID. This parameter should take on a value of -1 in these case.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">A 30600 75000 2000 0 45 3 0 0 3 75 50</pre>
  
  <p>
   An arc with the center at (30600, 75000) and a radius of 2000 mils, a starting angle of 0, sweeping 45 degrees, color index 3, line width of 0 mils (smallest size), no cap, center line type, dash length of 75 mils, dash spacing of 50 mils.
  </p>
  
  </div>
  <!-- SECTION [13604-15121] -->
  <h3><a name="text" id="text">text</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic and Symbol files<br/>
   <strong><code>type x y color size visibility show name value angle alignment num lines
  string line 1
  string line 2
  string line 3
  ...
  string line N</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>T</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>First X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>First Y coordinate</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>size</td><td>int/points</td><td>Size of text</td>
  	</tr>
  	<tr>
  		<td>visibility</td><td>int</td><td>Visibility of text</td>
  	</tr>
  	<tr>
  		<td>show_name_value</td><td>int</td><td>Attribute visibility control</td>
  	</tr>
  	<tr>
  		<td>angle</td><td>int/degrees</td><td>Angle of the text</td>
  	</tr>
  	<tr>
  		<td>alignment</td><td>int</td><td>Alignment/origin of the text</td>
  	</tr>
  	<tr>
  		<td>num_lines</td><td>int</td><td>Number of lines of text (1 based)</td>
  	</tr>
  	<tr>
  		<td>string line 1 ... N</td><td>string</td><td>The text strings, on a seperate line</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> This object is a multi line object. The first line contains all the text parameters and the subsequent lines are the text strings.</div>
  </li>
  <li class="level1"><div class="li"> There must be exactly num lines of text following the T ... string.</div>
  </li>
  <li class="level1"><div class="li"> The maximum length of any single text string is 1024, however there is no limit to the number of text string lines.</div>
  </li>
  <li class="level1"><div class="li"> The minimum size is 2 points (1/72 of an inch).</div>
  </li>
  <li class="level1"><div class="li"> There is no maximum size.</div>
  </li>
  <li class="level1"><div class="li"> The coordinate pair is the origin of the text item.</div>
  </li>
  <li class="level1"><div class="li"> The visibility field is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> INVISIBLE = 0</div>
  </li>
  <li class="level2"><div class="li"> VISIBLE = 1</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The show name value is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> SHOW NAME VALUE = 0 (show both name and value of an attribute)</div>
  </li>
  <li class="level2"><div class="li"> SHOW VALUE = 1 (show only the value of an attribute)</div>
  </li>
  <li class="level2"><div class="li"> SHOW NAME = 2 (show only the name of an attribute)</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The show name value field is only valid if the string is an attribute (string has to be in the form: name=value to be considered an attribute).</div>
  </li>
  <li class="level1"><div class="li"> The angle of the text can only take on one of the following values: 0, 90, 180, 270. A value of 270 will always generate upright text.</div>
  </li>
  <li class="level1"><div class="li"> The alignment/origin field controls the relative location of the origin.</div>
  </li>
  <li class="level1"><div class="li"> The alignment field can take a value from 0 to 8.</div>
  </li>
  <li class="level1"><div class="li"> The num_lines field always starts at 1.</div>
  </li>
  <li class="level1"><div class="li"> The num_lines field was added starting with file format version 1. Past versions (0 or earlier) only supported single line text objects.<br/>
   The following diagram shows what the values for the alignment field mean:</div>
  </li>
  </ul>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_fileformat_textgraphic.html" class="media" title="geda:fileformat_textgraphic.jpg"><img src="_media/geda_fileformat_textgraphic.jpg" class="media" title="fileformat_textgraphic.jpg" alt="fileformat_textgraphic.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">T 16900 35800 3 10 1 0 0 0 1
  Text string!</pre>
  
  <p>
  A text object with the origin at (16900, 35800), color index 3, 10 points in size, visible, attribute  ags not valid (not an attribute), origin at lower left, string: Text string!
  </p>
  
  <p>
  Example:<br/>
   
  </p>
  <pre class="code">T 16900 35800 3 10 1 0 0 0 5
  Text string line 1
  Text string line 2
  Text string line 3
  Text string line 4
  Text string line 5</pre>
  
  <p>
  This is a similar text object as the above example, however here there are five lines of text.
  </p>
  
  </div>
  <!-- SECTION [15122-17765] -->
  <h3><a name="net" id="net">net</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic files ONLY<br/>
   <strong><code>type x1 y1 x2 y2 color</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type char N</td>
  	</tr>
  	<tr>
  		<td>x1</td><td>int/mils</td><td>First X coordinate</td>
  	</tr>
  	<tr>
  		<td>y1</td><td>int/mils</td><td>First Y coordinate</td>
  	</tr>
  	<tr>
  		<td>x2</td><td>int/mils</td><td>Second X coordinate</td>
  	</tr>
  	<tr>
  		<td>y2</td><td>int/mils</td><td>Second Y coordinate</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> Nets can only appear in schematic files.</div>
  </li>
  <li class="level1"><div class="li"> You cannot have a zero length net (the tools will throw them away).</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">N 12700 29400 32900 29400 4</pre>
  
  <p>
  A net segment from (12700, 29400) to (32900, 29400) with color index 4.
  </p>
  
  </div>
  <!-- SECTION [17766-18291] -->
  <h3><a name="bus" id="bus">bus</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic files ONLY<br/>
   <strong><code>type x1 y1 x2 y2 color ripperdir</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type char U</td>
  	</tr>
  	<tr>
  		<td>x1</td><td>int/mils</td><td>First X coordinate</td>
  	</tr>
  	<tr>
  		<td>y1</td><td>int/mils</td><td>First Y coordinate</td>
  	</tr>
  	<tr>
  		<td>x2</td><td>int/mils</td><td>Second X coordinate</td>
  	</tr>
  	<tr>
  		<td>y2</td><td>int/mils</td><td>Second Y coordinate</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>ripperdir</td><td>int</td><td>Direction of bus rippers</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The ripperdir field for an brand new bus is 0.</div>
  </li>
  <li class="level1"><div class="li"> The ripperdir field takes on a value of 1 or -1 when a net is connected to the bus for the first time. This value indicates the direction of the ripper symbol. The ripper direction is set to the same value for the entire life of the bus object.</div>
  </li>
  <li class="level1"><div class="li"> Buses can only appear in schematic files.</div>
  </li>
  <li class="level1"><div class="li"> You cannot have a zero length bus (the tools will throw them away).</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">U 27300 37400 27300 35300 3 0</pre>
  
  <p>
  A bus segment from (27300, 37400) to (27300, 35300) with color index 3 and no nets have been connected to this bus segment.
  </p>
  
  </div>
  <!-- SECTION [18292-19223] -->
  <h3><a name="pin" id="pin">pin</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Symbol files ONLY<br/>
   <strong><code>type x1 y1 x2 y2 color pintype whichend</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>P</td>
  	</tr>
  	<tr>
  		<td>x1</td><td>int/mils</td><td>First X coordinate</td>
  	</tr>
  	<tr>
  		<td>y1</td><td>int/mils</td><td>First Y coordinate</td>
  	</tr>
  	<tr>
  		<td>x2</td><td>int/mils</td><td>Second X coordinate</td>
  	</tr>
  	<tr>
  		<td>y2</td><td>int/mils</td><td>Second Y coordinate</td>
  	</tr>
  	<tr>
  		<td>color</td><td>int</td><td>Color index</td>
  	</tr>
  	<tr>
  		<td>pintype</td><td>int</td><td>Type of pin</td>
  	</tr>
  	<tr>
  		<td>whichend</td><td>int</td><td>Specifies the active end</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> The pintype is an enumerated type:</div>
  <ul>
  <li class="level2"><div class="li"> NORMAL <acronym title="Personal Identification Number">PIN</acronym> = 0</div>
  </li>
  <li class="level2"><div class="li"> BUS <acronym title="Personal Identification Number">PIN</acronym> = 1 unused</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> The whichend specifies which end point of the pin is the active connection port. Only this end point can have other pins or nets connected to it.</div>
  </li>
  <li class="level1"><div class="li"> To make the first end point active, whichend should be 0, else to specify the other end, whichend should be 1.</div>
  </li>
  <li class="level1"><div class="li"> Pins can only appear in symbol files.</div>
  </li>
  <li class="level1"><div class="li"> You cannot have a zero length pen (the tools will throw them away).</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">P 0 200 200 200 1 0 0</pre>
  
  <p>
  A pin from (0, 200) to (200, 200) with color index 1, a regular pin, and the first point being the active connection end.
  </p>
  
  </div>
  <!-- SECTION [19224-20220] -->
  <h3><a name="component" id="component">component</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Schematic files ONLY<br/>
   <strong><code>type x y selectable angle mirror basename</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type char C</td>
  	</tr>
  	<tr>
  		<td>x</td><td>int/mils</td><td>Origin X coordinate</td>
  	</tr>
  	<tr>
  		<td>y</td><td>int/mils</td><td>Origin Y coordinate</td>
  	</tr>
  	<tr>
  		<td>selectable</td><td>int</td><td>Selectable flag</td>
  	</tr>
  	<tr>
  		<td>angle</td><td>int/degrees</td><td>Angle of the component</td>
  	</tr>
  	<tr>
  		<td>mirror</td><td>int</td><td>Mirror around Y axis</td>
  	</tr>
  	<tr>
  		<td>basename</td><td>string</td><td>The filename of the component</td>
  	</tr>
  </table>
  <br />
  
  <p>
   The selectable field is either 1 for selectable or 0 if not selectable.
  </p>
  <ul>
  <li class="level1"><div class="li"> The angle field can only take on the following values: 0, 90, 180, 270.</div>
  </li>
  <li class="level1"><div class="li"> The angle field can only be positive.</div>
  </li>
  <li class="level1"><div class="li"> The mirror flag is 0 if the component is not mirrored (around the Y axis).</div>
  </li>
  <li class="level1"><div class="li"> The mirror flag is 1 if the component is mirrored (around the Y axis).</div>
  </li>
  <li class="level1"><div class="li"> The just basename is the filename of the component. This filename is not the full path.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">C 18600 19900 1 0 0 7400-1.sym</pre>
  
  <p>
  A component whos origin is at (18600,19900), is selectable, not rotated, not mirrored, and the basename of the component is 7400-1.sym.
  </p>
  
  </div>
  <!-- SECTION [20221-21223] -->
  <h3><a name="font" id="font">font</a></h3>
  <div class="level3">
  
  <p>
  Valid in: Special font files ONLY<br/>
   <strong><code>type character width flag</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th>Field</th><th>Type/unit</th><th>Description</th>
  	</tr>
  	<tr>
  		<td>type</td><td>char</td><td>F</td>
  	</tr>
  	<tr>
  		<td>character</td><td>char</td><td>The character being defined</td>
  	</tr>
  	<tr>
  		<td>width</td><td>int/mils</td><td>Width of the character (mils)</td>
  	</tr>
  	<tr>
  		<td>flag</td><td>int</td><td>Special space flag</td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> This is a special tag and should ONLY show up in font definition files.</div>
  </li>
  <li class="level1"><div class="li"> If the font character being defined is the space character (32) then flag should be 1, otherwise 0.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   
  </p>
  <pre class="code">F 11 1</pre>
  
  <p>
  The above font definition is for the space character.
  </p>
  
  </div>
  <!-- SECTION [21224-21744] -->
  <h2><a name="colors" id="colors">Colors</a></h2>
  <div class="level2">
  
  <p>
  In the gEDA/gaf schematic and symbol file format colors are specified via an integer index. The relationship between integer and color is based on object type. Each object type typically has one or more colors. Here is a table of color index to object type: 
  </p>
  <table class="inline">
  	<tr>
  		<th>Color</th><th>Index</th><th>Object type</th>
  	</tr>
  	<tr>
  		<td>0</td><td>BACKGROUND_COLOR</td>
  	</tr>
  	<tr>
  		<td>1</td><td><acronym title="Personal Identification Number">PIN</acronym>_COLOR</td>
  	</tr>
  	<tr>
  		<td>2</td><td>NET_ENDPOINT_COLOR</td>
  	</tr>
  	<tr>
  		<td>3</td><td>GRAPHIC_COLOR</td>
  	</tr>
  	<tr>
  		<td>4</td><td>NET_COLOR</td>
  	</tr>
  	<tr>
  		<td>5</td><td>ATTRIBUTE_COLOR</td>
  	</tr>
  	<tr>
  		<td>6</td><td>LOGIC_BUBBLE_COLOR</td>
  	</tr>
  	<tr>
  		<td>7</td><td>GRID_COLOR</td>
  	</tr>
  	<tr>
  		<td>8</td><td>DETACHED_ATTRIBUTE_COLOR</td>
  	</tr>
  	<tr>
  		<td>9</td><td>TEXT_COLOR</td>
  	</tr>
  	<tr>
  		<td>10</td><td>BUS_COLOR</td>
  	</tr>
  	<tr>
  		<td>11</td><td>SELECT_COLOR</td>
  	</tr>
  	<tr>
  		<td>12</td><td>BOUNDINGBOX_COLOR</td>
  	</tr>
  	<tr>
  		<td>13</td><td>ZOOM_BOX_COLOR</td>
  	</tr>
  	<tr>
  		<td>14</td><td>STROKE_COLOR</td>
  	</tr>
  	<tr>
  		<td>15</td><td>LOCK_COLOR</td>
  	</tr>
  	<tr>
  		<td>16</td><td>OUTPUT_BACKGROUND_COLOR</td>
  	</tr>
  </table>
  <br />
  
  <p>
   The actual color associated with the color index is defined on a per tool bases. Objects are typically assigned their corresponding color index, but it is permissible (sometimes) to assign other color index values to different object types.
  </p>
  
  </div>
  <!-- SECTION [21745-22622] -->
  <h2><a name="attributes" id="attributes">Attributes</a></h2>
  <div class="level2">
  
  <p>
  Attributes are enclosed in f g and can only be text. Attributes are text items which take on the form name=value. If it doesn&rsquo;t have name=value, it&rsquo;s not an attribute. Attributes are attached to the previous object. Here&rsquo;s an example: 
  </p>
  <pre class="code">P 988 500 1300 500 1
  f
  T 1000 570 5 8 1 1 0
  pinseq=3
  T 1000 550 5 8 1 1 0
  pinnumber=3
  g</pre>
  
  <p>
  The object is a pin which has an attribute pinnumber=3 and pinseq=3 (name=value). You can have multiple text objects (both the T ... and text string are required) in between the f g. As of 20021103, you can only attached text items as attributes. Attaching other object types as attributes is unsupported.<br/>
   You can also have &ldquo;toplevel&rdquo; attributes. These attributes are not attached to any object, but instead are just text objects that take on the form name=value.<br/>
   These attributes are useful when you need to convey some info about a schematic page or symbol and need the netlister to have access to this info.
  </p>
  
  </div>
  <!-- SECTION [22623-23598] -->
  <h2><a name="embedded_components" id="embedded_components">Embedded Components</a></h2>
  <div class="level2">
  
  <p>
  Embedded components are components which have all of their definition stored within the schematic file. When a users place a component onto a schematic page, they have the option of making the component embedded. Other than storing all the symbol information inside of the schematic, an embedded component is just any other component. Embedded components are defined as: 
  </p>
  <pre class="code">C 18600 21500 1 0 0 EMBEDDED555-1.sym
  [
  ...
  ... Embedded primitive objects
  ...
  ]</pre>
  
  <p>
  In the example above, <strong>555-1.sym</strong> is the component. The EMBEDDED tag and the [ ] are the distinguishing characteristics of embedded components. <strong>componentname.sym</strong> must exist in one of the specified component-libraries if you want to unembed the component.
  </p>
  
  </div>
  <!-- SECTION [23599-24358] -->
  <h2><a name="document_revision_history" id="document_revision_history">Document Revision History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td>November 30th, 2002</td><td>Created fleformats.tex from fleformats.html.</td>
  	</tr>
  	<tr>
  		<td>December 1st, 2002</td><td>Continued work on this document.</td>
  	</tr>
  	<tr>
  		<td>October 4th, 2003</td><td>Added new file format version flag info.</td>
  	</tr>
  	<tr>
  		<td>October 19th, 2003</td><td>Added num lines text field.</td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [24359-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_footprint_creation.html
  
  Index: geda_footprint_creation.html
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  <h1><a name="gattrib_readme" id="gattrib_readme">gattrib README</a></h1>
  <div class="level1">
  <pre class="code">******************************************************************
  *************  DANGER!!  Read the entirety of this  **************
  ************  README before you try runing gattrib!  *************
  ******************************************************************
  
  
  INTRODUCTION
  
  Gattrib is gEDA's attribute editor.  It reads a set of gschem .sch
  files (schematic files), and creates a spreadsheet showing all
  components in rows, with the associated component attributes listed in
  the columns.  It allows the user to add, modify, or delete component
  attributes outside of gschem, and then save the .sch files back
  out.  When it is completed, it will allow the user to edit attributes
  attached to components, nets, and pins.  (Currently, only component
  attribute editing is implemented; pin attributes are displayed only,
  and net attributes are TBD.) 
  
  Gattrib is useful in situations where you need to view, add, modify,
  or delete a number of attributes all at once.  It saves you the pain
  of clicking on each component and repeatedly using gschem's attribute 
  editor to modify component attributes.  For example, if you create a
  large design with generic components, and then later want to attach
  &quot;footprint&quot; attributes to your components, it is a real hassle to do
  so using gschem.  In this situation, you can run gattrib on your
  design files to attach the &quot;footprint&quot; attributes all at once using an
  easy-to-use spreadsheet. 
  
  WARNING NOTE:  Gattrib is currently PRE-ALPHA SOFTWARE!
  It has been tested on several designs, but is not garuanteed to work.
  It may even trash your design!  Therefore, if you wish to try gattrib
  out, please create a backup copy of your design before you run it!
  
  ------------------------------------------------------------------
  USAGE
  
  You can invoke gattrib on your design from the command line in the
  following way:
  
  gattrib my_design_*.sch
  
  (This assumes you have a multi-page design with file names
  &quot;my_design_1.sch&quot;, &quot;my_design_2.sch&quot;, etc.)  Gattrib will then read in
  your design, and present you with a spreadsheet showing all components
  and associated attributes. 
  
  You can also just run gattrib, and specify the input files using the
  file-&gt;open dialog box.
  
  To edit your attributes, just edit the cells in the spreadsheet.  
  
  To save your design, just select &quot;save&quot; from the command menu.  Note
  that no checks are currently done when you select save.  Be careful!
  
  To quit, just select &quot;quit&quot; from the command menu.  Note that
  currently no checks thet you have saved your design are done when you
  quit.  
  
  If you want to add an entirely new attribute to your design (i.e. one
  which doesn't exist on any component), you must first attach at least
  one instance of that attribute to a component using gschem.  Then you
  can use gattrib to attach the attribute to the remaining components.
  (The reason for this is that gattrib creates its spreadsheet columns
  based upon all attributes it finds when reading in the design.
  Therefore, to create a column for a new attribute, you need to make
  sure that that new attribute pre-exists in the design.)  In the future,
  you will be able to add new attribute columns directly from gattrib,
  but this feature is currently unimplemented.
  
  ------------------------------------------------------------------
  FEATURES
  
  The following features are currently implemented:
  
  *  .sch file read in from command line.
  *  .sch file read in from menu.
  *  .sch file save out from menu.
  *  Component attribute editing (of course).
  *  Pin attribute viewing.
  *  Quit from menu.
  
  The following features are currently unimplemented, but will be
  incorporated at some future date:
  
  *  Throw up &quot;Are you sure&quot; dialog boxes upon selecting &quot;save&quot; and
     &quot;quit&quot; from menu.
  *  Alphabetic sort of rows.  (Should happen automatically upon read-in
     of design.)
  *  Editing of net attributes (important for setting routing
     attributes). 
  *  Adding/deleting attribute columns (to add/delete entire sets of
     attributes from a design.)
  *  Search/replace of individual attributes.
  *  Search for component refdeses &amp; netnames.
  *  Set/view component &amp; net visibility (through options pull-down
     menu).  Currently, visibility is &quot;invisible&quot;, and both name &amp; value
     are displayed (if you turn on the visibility).
  
  Note that if you select unimplemented features from the menu, nothing
  will happen.
  
  ------------------------------------------------------------------
  INSTALLATION
  
  To install gattrib, place the tarball in the directory where your gEDA
  sources live.  Then do:
  
  tar -zxvf geda-gattrib-20040806.tar.gz
  cd geda-gattrib-20040806
  ./configure --prefix=/path/to/your/geda/stuff
  make
  make install
  
  Note that you may need to set some environment variables first.  If
  your compilation barfs, try setting these (for csh):
  
  setenv LD_LIBRARY_PATH /usr/local/geda/lib:$LD_LIBRARY_PATH
  setenv PATH /usr/local/geda/bin:$PATH
  setenv PKG_CONFIG_PATH /usr/local/geda/lib/pkgconfig:$PKG_CONFIG_PATH
  
  ------------------------------------------------------------------
  CREDITS/CONTACT:
  
  Gattrib was cobbled together by Stuart Brorson starting in December
  2003 from parts culled from GtkSheet (GTK+Extra) and gEDA.  Please
  mail bug reports to: sdb@xxxxxxxxxx
  
  
  
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_gerbv_mp.html
  
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  <h1><a name="gerbv_man-page" id="gerbv_man-page">gerbv man-page</a></h1>
  <div class="level1">
  <pre class="code">gerbv(1)			 cvs-20051023			      gerbv(1)
  
  
  
  NAME
         gerbv - Gerber Viewer
  
  SYNOPSIS
         gerbv [OPTIONS] [gerberfile[s]]
  
  DESCRIPTION
         gerbv is a viewer for Gerber files. Gerber files is generated from dif-
         ferent PCB CAD programs and are sent to subcontractors to actually make
         the PCB. gerbv also supports Excellon/NC drill files.
  
  
  OPTIONS
         Warning!	  On  some platforms, which hasnÃ¢â?¬â?¢t long option available, only
         short options are available.
  
  
     gerbv Options
         -V|--version Prints the version number of gerbv and exits.
  
         -h|--help
  	      Prints a brief usage guide.
  
         -l &lt;filename&gt;|--log=&lt;filename&gt;
  	      All error messages etc are stored in a file with filename &lt;file-
  	      name&gt;.
  
         -t &lt;filename&gt;|--tools=&lt;filename&gt;
  	      Read Excellon tools from the file &lt;filename&gt;.
  
         --geometry=&lt;width&gt;x&lt;height&gt;[&lt;+-&gt;x-position[&lt;+-&gt;y-position]]
  	      Sets  the	 the size of the window. X-position and y-position are
  	      currently ignored by gerbv.
  
         -p &lt;project filename&gt;|--project=&lt;project filename&gt;
  	      Load a stored project. Please note that the project file must be
  	      stored in the same directory as the gerber files.
  
  
     GTK Options
         --gtk-module=MODULE Load an additional GTK module
  
         --g-fatal-warnings
  	      Make all warnings fatal
  
         --gtk-debug=FLAGS
  	      GTK debugging flags to set
  
         --gtk-no-debug=FLAGS
  	      GTK debugging flags to unset
  
         --gdk-debug=FLAGS
  	      GDK debugging flags to set
  
         --gdk-no-debug=FLAGS
  	      GDK debugging flags to unset
  
         --display=DISPLAY
  	      X display to use
  
         --sync Make X call synchronous
  
         --no-xshm
  	      DonÃ¢â?¬â?¢t use X shared memory extension
  
         --name=NAME
  	      Program name as used by the window manager
  
         --class=CLASS
  	      Program class as used by the window manager
  
  
  GENERAL
         When you start gerbv you can give the files to be loaded on the command
         line, either as each file separated with a space or by using wildcards.
  
         The user interface is graphical. Simply press left mouse button and the
         image will pan as you move the mouse. To	 manipulate  a	layer,	right-
         click on one of the rightmost buttons. That will bring up a pop-up menu
         where you can select what you want to do with that  layer  (load	 file,
         change color, etc).
  
         If  you	hold the mouse button over one the rightmost button a tooltips
         will show you the name of the file loaded on that layer.
  
         Default of concurrently loaded files are 20 layers. You can change this
         during configure with:
  
  	./configure with-maxfiles=&lt;number&gt;
  
  
  ACTIVATION AND DEACTIVATION OF LAYERS
         You can load several files at one time. You can then turn displaying of
         the layers on and off by clicking on one of the rightmost buttons.
  
         You can also control this from the keyboard. Press Alt, enter the  num-
         ber  on	the layer you want activate/deactivate on the numerical keypad
         and then release the Alt key.
  
  
  ZOOMING
         Zooming can be handled by  either  menu	choices,  keypressing,	middle
         mouse  button  or scroll wheel. If you press Alt+I you will zoom in and
         if you press Alt+O you will zoom out.If you press middle	 mouse	button
         you  will  zoom out, and if you press Shift and middle mouse button you
         will zoom in.  Scroll wheel works if you enabled that in your X	server
         and mapped it to button 4 and 5. You can also zoom in by pressing z and
         zoom out by pressing shift+z (ie Z). You can  make  the	image  fit  by
         pressing f (there is also a menu alternativ for this).
  
         You  can	 also  do  zooming by outline. Press right mouse button, draw,
         release.	 The dashed line shows how the zooming will  be	 dependent  on
         the resolution of the window. The non-dashed outline will show what you
         actually selected. If you change your mind when started	to  mark  out-
         line,  you  can	always	abort  by pressing escape. By holding down the
         shift key when you press the right mouse button,	 you  will  select  an
         area  where  the point you started at will be the center of your selec-
         tion.
  
  
  MEASUREMENTS
         You can do measurement on the image displayed. By pressing  shift,  the
         cursor  changes	to a plus. By using left mouse button you can draw the
         lines that you want to measure.	The result of the last measurement  is
         also  displayed	on the statusbar.  All measurements are in the drawing
         until you either zoom, pan or press the escape key.
  
         The statusbar shows the current mouse position on the layer in the same
         coordinates  as	in the file. Ie if you have (0,0) in the middle of the
         image in the gerber files, the statusbar will show (0,0)	 at  the  same
         place.
  
  
  SUPERIMPOSING
         When  you  load	several	 Gerber files, you can display them &quot;on top of
         each other&quot;, ie superimposing. The general way to display them are that
         upper  layers  cover  the  layers  beneath,  which is called copy (GTK+
         terms).
  
         The other ways selectable  are  and,  or,  xor  and  invert.  They  map
         directly	 to  corresponding functions in GTK. In GTK they are described
         as: &quot;For colored images, only GDK_COPY, GDK_XOR and GDK_INVERT are gen-
         erally useful. For bitmaps, GDK_AND and GDK_OR are also useful.&quot;
  
  
  PROJECTS
         gerbv  can  also	 handle projects. A project consist of bunch of loaded
         layers with their resp. color and the background color. The easiest way
         to  create  a  project is to load all files you want into the layer you
         want, set all the colors etc and do a &quot;Save Project As...&quot;.
  
         You load a project either from the menu bar or by using the commandline
         switches -p or --project.
  
         Currently there is a limit in that the project file must be in the same
         directory as the gerber files to be loaded.
  
  
  SCHEME
         The project files are simple Scheme programs that is interpreted	 by  a
         built  in  Scheme interpreter. The Scheme interpreter is TinyScheme and
         needs a Scheme program called init.scm to initialize itself. The search
         path	for	init.scm     is	    (in	    the	   following	order)
         /usr/local/gEDA-20060124/share/gerbv/scheme/share/gerbv/scheme/,	   the
         directory  with	the  executable gerbv, the directory gerbv was invoked
         from   and   finally   according	  to	the    environment    variable
         GERBV_SCHEMEINIT.
  
  
  TOOLS FILE
         Not  every  Excellon  drill  file is self-sufficient. Some CADs produce
         .drd files where tools are only referenced, but never defined (such  as
         what diameter of the tool is.) Eagle CAD is one of such CADs, and there
         are more since many board houses require Tools files.
  
         A Tools file is a plain text file which you create in an	 editor.  Each
         line  of	 the  file  describes  one tool (the name and the diameter, in
         inches):
  
  	    T01 0.024
  	    T02 0.040
  	    ...
  
         These are the same tools (T01 etc.) that are used in the Drill file.  A
         standard	 practice with Eagle is to create an empty Tools file, run the
         CAM processor, and the error report tells you which tools you &quot;forgot&quot;.
         Then you put these tools into the file and rerun the CAM processor.
  
         You  load  a tool file by using the commandline switches -t or --tools.
         The file can have any name you wish, but Eagle expects the file type to
         be &quot;.drl&quot;, so it makes sense to keep it this way. Some board houses are
         still using CAM software from DOS era, so you  may  want	 to  excercise
         caution before going beyond the 8.3 naming convention.
  
         When gerbv reads the Tools file it also checks that there are no dupli-
         cate definitions of tools. This does happen from time to	 time  as  you
         edit  the file by hand, especially if you, during design, add or remove
         parts from the board and then have to add  new  tools  into  the	 Tools
         file.  The  duplicate  tools  are  a very serious error which will stop
         (HOLD) your board until you fix the Tools file and maybe	 the  Excellon
         file.  gerbv  will detect duplicate tools if they are present, and will
         exit immediately to indicate such a fatal error in a very obvious  way.
         A message will also be printed to standard error.
  
         If your Excellon file does not contain tool definitions then gerbv will
         preconfigure the tools by deriving the diameter of the drill  bit  from
         the  tool  number. This is probably not what you want, and you will see
         warnings printed on the console.
  
  
  ENVIRONMENT
         GERBV_SCHEMEINIT
  	      Defines where the init.scm file is stored. Used by scheme inter-
  	      preter, which is used by the project reader.
  
  
  AUTHOR
         Stefan Petersen (spetm at users.sourceforge.net): Overall hacker and project leader
         Andreas Andersson (e92_aan at e.kth.se): Drill file support and general hacking
         Anders Eriksson (aenfaldor at users.sourceforge.net) : X and GTK+ ideas and hacking
  
  
  COPYRIGHT
         Copyright Ã?Â©  2001-2004 Stefan Petersen
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  Version				 Feb 8th, 2004			      gerbv(1)
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_gerbv_pnp_readme.html
  
  Index: geda_gerbv_pnp_readme.html
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  <h1><a name="searching_for_parts_and_marking_them_on_screen_in_gerbv" id="searching_for_parts_and_marking_them_on_screen_in_gerbv">Searching for Parts and marking them on screen (in gerbv)</a></h1>
  <div class="level1">
  <pre class="code">Searching for Parts and marking them on screen (in gerbv)
  
  THIS FUNCTIONALITY IS ONLY AVAILABLE WHEN COMPILING GERBV AGAINST GTK2!
  
  Please direct any comments, suggestions etc. to Juergen &lt;juergenhaas@xxxxxxx&gt;
  =============================================================================
  ***  Support for Pick and Place files:                                   ***
  ***  csv-style files with/without quotes                                 ***    
  ***  the following delimiters are supported ';' ':' '|' ','              ***
  ----------------------------------------------------------------------------
  
  
  ----------------------------------------------------------------------------
  A pick and place file has 11 columns (the first two lines a file in gerbv/examplei
  are shown here) and looks like this:
  
  Designator:Footprint:Mid X:Mid Y:Ref X:Ref Y:Pad X:Pad Y:Layer:Rotation:Comment
  
  R29:0805_REFL:25.4mm:72.644mm:25.4mm:72.644mm:25.4mm:71.6788mm:T:90.00:1K/1%
  ----------------------------------------------------------------------------
  
  Some instructions for the first time user:
  
  after loading a PNP file a new dialog will come up offering various option of
  selecting and graphically marking electronic parts.
  
  Three modes of selecting items do exist:
  1)enter any search phrase and hit enter 
       (See also paragraph &quot;SCROLLING&quot; further down)
          -Generally under linux regexp expressions are used such as &quot;.*&quot; i.e. '*'
          -All matches will be marked in the list AND on the screen
          -if you press ESC or press &lt;ENTER&gt; on an empty line it will deselect all
           items
          -if you had a selection already and you would like to add single items
           one by one, just hold down CTRL key while you left-click on the desired
           fields
  
  2)just simply use left click combined with Shift and/or CTRL for manual
    mouse driven selections
    Pressing right button of mouse will not only select but also draw item on 
    selected layer
  
  3)if you have pressed &lt;ENTER&gt; on an empty phrase you first of all will deselect 
    anything which was selected  and you can then enter the so-called &quot;assembly 
    mode&quot; by left clicking on an item and afterwards pressing space as often as 
    desired, while the select parts dialog is active. The selection will move 
    down the list one by one displaying the selected part in the window 
    automatically (with the corresponding layer being active).
    
   Alternatively 1: 
   If you had more than one item selected and you did not clear the selections list
   by &lt;ENTER&gt; on an empty phrase, only the first item will be taken into account
   and all others will be deselected.
  
   Alternatively 2:
   You can of course also select an item by clicking on it, pressing space will 
   then proceed as described
  
   This mode also features arrows Up/Down selection, where arrow Up will reverse 
   the action of arrow Down/Spacebar. Furthermore, holding SHIFT while pressing 
   arrow Up/Down will increase the selection in either direction 
  -------------------------
  More Features:  
  
  4)Inversion of selection:
    pressing this button at any given time inverts the selection concerning the 
    whole list and upon clicking Mark button this new selection will be drawn 
    onto screen.
   
    
  5)Top/bottom selection
    General:  press mark to mark selections on screen, after choosing to select 
                     top or bottom parts.
  
      a)in existing selection will only remove non wanted items 
            (e.g. all bottom parts if you press &quot;top  parts&quot;) from selection
     
      b)if there is no selection, all top or all bottoms parts are selected
  
  
  6)Choose available layers for marking selected parts from drop-down list
    HINT: if pick and place file is loaded last, already occupied layers 
          will not be in the drop-down list
  
  -------------------------------------------------------------------
  Hint 1:
  right click functionality to know Part description.
  After you have graphically marked a number of parts (say all resistors) you can
  right click onto a part which is selected in the scroll-down list of available
  parts in the search dialog.
  Its designator, comment and footprint are then shown in the statusbar and in the log window.
  This comes in handy if there are many parts you want to look at, but e.g. you already
  know a fault has occurred only on one side of the board.
  
  -------------------------------------------------------------------
  Hint 2:
  SCROLLING (in the dialog window)
   Scrolling generally only occurs, if search for comments is not activated AND 
   also whenever enter is hit the list will bescrolled to the first hit, 
   regardless of the search mode.
   The use of BackSpace is supported.
   If you decide to select an entry from the list of completions offered, then the
   scrolling will only occur once you press enter.
  
  Example:
   imagine you are looking for an element labelled EU3:
   If you hit the first key (E) to enter a search phrase in the entry field, the 
   list will be scrolled to the first element matching this key (E), also entering
   a subsequent key (U) will then further refine that and scroll to the first 
   element with EU etc.
  ====================================================================</pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_gfdl.html
  
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  <h1><a name="gnu_free_documentation_license" id="gnu_free_documentation_license">GNU Free Documentation License</a></h1>
  <div class="level1">
  <pre class="code">                  GNU Free Documentation License
                      Version 1.2, November 2002
  
  
   Copyright (C) 2000,2001,2002  Free Software Foundation, Inc.
       51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
   Everyone is permitted to copy and distribute verbatim copies
   of this license document, but changing it is not allowed.
  
  
  0. PREAMBLE
  
  The purpose of this License is to make a manual, textbook, or other
  functional and useful document &quot;free&quot; in the sense of freedom: to
  assure everyone the effective freedom to copy and redistribute it,
  with or without modifying it, either commercially or noncommercially.
  Secondarily, this License preserves for the author and publisher a way
  to get credit for their work, while not being considered responsible
  for modifications made by others.
  
  This License is a kind of &quot;copyleft&quot;, which means that derivative
  works of the document must themselves be free in the same sense.  It
  complements the GNU General Public License, which is a copyleft
  license designed for free software.
  
  We have designed this License in order to use it for manuals for free
  software, because free software needs free documentation: a free
  program should come with manuals providing the same freedoms that the
  software does.  But this License is not limited to software manuals;
  it can be used for any textual work, regardless of subject matter or
  whether it is published as a printed book.  We recommend this License
  principally for works whose purpose is instruction or reference.
  
  
  1. APPLICABILITY AND DEFINITIONS
  
  This License applies to any manual or other work, in any medium, that
  contains a notice placed by the copyright holder saying it can be
  distributed under the terms of this License.  Such a notice grants a
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  A &quot;Modified Version&quot; of the Document means any work containing the
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  The &quot;Invariant Sections&quot; are certain Secondary Sections whose titles
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  <h1><a name="glossary_of_geda_and_eda_terms" id="glossary_of_geda_and_eda_terms">Glossary of gEDA (and EDA) terms</a></h1>
  <div class="level1">
  
  <p>
   The design of electronics involves a host of specific terms. Some words have a meaning that only vaguely resembles the use in everyday life. This glossary aims to be a dictionary of terms specific to the gEDA suite, as well as to the larger world of CAD for electronics. Unfortunately there is no universal naming scheme for concepts in the area of electronic design. The glossary will give hints on how things are called in other design suites.
  </p>
  
  <p>
  <span class="hilited">(Wiki-authors: Please insert new terms according to the alphabet)</span>
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>annular ring</strong>: The annular ring, sometimes also called <strong>annulus</strong>, is a diameter of copper that needs to be placed arround metalized holes like pads and vias. The minimum size of the annular ring is specified by the pcb-fab. A common requirements is 16 mil larger than the hole.</div>
  </li>
  <li class="level1"><div class="li"> <strong>design flow</strong>: The order or stages through which you take your design as you progress from initial concept, through schematic capture, attribute attachment, netlisting, and layout. One typically uses different tools to accomplish different tasks during the design process. The gEDA Suite uses entirely separate programs for different stages of the flow; each tool in the suite reads the output file produced by the previous tool, and writes a file to be read by the next tool in the flow. The gEDA design flow for designing a PCB is illustrated <a href="http://geda.seul.org/dokuwiki/doku.php?id=geda:usage#what_does_the_design_flow_in_geda_look_like"; class="urlextern" title="http://geda.seul.org/dokuwiki/doku.php?id=geda:usage#what_does_the_design_flow_in_geda_look_like";  rel="nofollow">here</a>. Note that the design flow for different tasks might look different. For example, if your goal is to simulate your circuit, you will use a different flow than that shown in the link above. Finally, other â?? usually simpler â?? PCB design tools use a monolithic approach in which one single program (albeit with different edit modes) is used for the entire design. Which approach is better usually is a matter of personal religion.</div>
  </li>
  <li class="level1"><div class="li"> <strong>footprint</strong>: The pattern of metal and silkscreen which defines where you place a component on a PCB. Footprints are the placed by the user onto the PC board during the â??placementâ?? phase of PCB layout (using e.g. the open-source tool PCB). A footprint is also sometimes called called a â??decalâ?? (PADS), or a â??land-patternâ??.</div>
  </li>
  <li class="level1"><div class="li"> <strong>net</strong>: A net is the representation of a wire, or electrical connection in your schematic diagram. It is basically a line connecting two symbol pins. The term â??netâ?? is also sometimes used loosely to talk about an electical connection (via a wire or PCB trace) in a real circuit. Some schematic capture tools call a net a â??wireâ??.</div>
  </li>
  <li class="level1"><div class="li"> <strong>netlist</strong>: A netlist is an text file representation of your circuit which emphasizes the connections between the different circuit elements, perhaps independently of the physical packages constituting the actual components in the circuit.</div>
  </li>
  <li class="level1"><div class="li"> <strong>pad</strong>: A pad is the patch of copper to which a SMD-component is to be soldered. Although pads are usually square, they can also be rounded.</div>
  </li>
  <li class="level1"><div class="li"> <strong>pin</strong>: A pin is a hole in the printed circuit that allows to connect a wired component. In many cases the hole is clad with copper by the pcb-fab.</div>
  </li>
  <li class="level1"><div class="li"> <strong>pcb</strong>: In the context of gEDA this acronm has two distict meanings:</div>
  <ol>
  <li class="level2"><div class="li"> An abbreviation of â??printed circuit boardâ??. This is the actual hardware that is used to connect electronic components. It is also sometimes called a â??printed wiring boardâ?? (PWB), although this usage may be dying out.</div>
  </li>
  <li class="level2"><div class="li"> A powerfull, open-source tool used to design the layout of a printed circuit board. The output of the gaf tools can be used as an input to pcb.(<a href="http://pcb.sourceforge.net/index.html"; class="urlextern" title="http://pcb.sourceforge.net/index.html";  rel="nofollow">homepage of pcb</a>)</div>
  </li>
  </ol>
  </li>
  <li class="level1"><div class="li"> <strong>rats nest</strong>: The lines drawn on the pcb working area that hint which pads still need need to be connected with tracks. Unlike the actual tracks the rats nest are straight lines. If multiple pads are involved in a net, pcb tries to draw rats nests with the shortest possible length.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes</strong>: Short for â??reference designatorâ??. The unique designator (or name) of a component. The gEDA tools rely on the refdefs to organize the components internally. Therefore, for successful creation of a printed circuit board every component has to be linked with a refdes. Usually, the refdes consists of a few upper case letters and a digit. Examples: R1, R2, U115, CONN3. (Protel: â??Designatorâ??)</div>
  </li>
  <li class="level1"><div class="li"> <strong>slot</strong>: Some components contain multiple, identical devices inside a signal package. The IOs for each component are mapped to different pin sets on the package. A classic example is the TTL 7400 quad nand gate. Gschem (like other schematic capture packages) handles this type of component by allowing you to draw four separate nand gate symbols, and then selecting which <strong>slot</strong> each symbol should have by attaching a slot attribute to the symbol. In the example of the 7400 quad nand, you would select <strong><code>slot=1</code></strong> for the first appearance of the symbol, slot=2 for the second appearance, and so on. Note that in gschem you need to attach power nets to a slotted component only <strong>once</strong>. (Other schematic capture programs like Orcad require you to attach common nets â?? like power nets â?? on each instantiation of the slotted symbol.)</div>
  </li>
  <li class="level1"><div class="li"> <strong>symbol</strong>: A symbol is the representation of a particular component in your schematic diagram. The classic examples are squiggley lines for resistors (in US usage anyway), or a triangle for an op-amp. Using a schematic capture program (e.g. gschem) you place symbols on your board, and then wire them up to create a representation of your circuit.</div>
  </li>
  <li class="level1"><div class="li"> <strong>via</strong>: A via is a metalized hole that is meant to electrically connect different layers of the pcb. Usually, vias are as small as possible to save valuable real estate on the pcb.</div>
  </li>
  </ul>
  
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  <h1><a name="gnetlist_man-page" id="gnetlist_man-page">gnetlist man-page</a></h1>
  <div class="level1">
  <pre class="code">gnetlist(1)			   20031231			   gnetlist(1)
  
  
  
  NAME
         gnetlist - gEDA/gaf Netlist extraction/generation
  
  SYNOPSIS
         gnetlist	 [-i] [-I] [-q] [-s] [-v] [-l schem_file] [-m schem_file ] [-g
         guile_procedure] [-c scheme_string ]  [-o  output_filename]  schematic1
         [... schematicN]
  
  DESCRIPTION
         gnetlist	 is  the  netlist  extraction/generation program which is part
         gEDA (GPL Electronic Design Automation) toolset.	 This program takes  a
         schematic for its input and outputs a netlist.
  
         gnetlist	 depends heavily on guile (a scheme based scripting language).
         It uses guile to define the output format.  Basically gnetlist reads  a
         schematic,  creates  an	internal representation of the various connec-
         tions, and then a guile	script	extracts  the  connections  into  some
         netlist format.
  
         gnetlist is very much so a work in progress.  Currently it supports the
         following backends:
  
  	       1) Allegro netlist format (-g allegro)
  
  	       2) BAE netlist format (-g bae)
  
  	       3) BOM / BOM2 - Bill of Materials (-g bom and -g bom2)
  
  	       4) Partslist 1,2,3 - More Bill of Materials (-g partslist[1-3])
  
  	       5) DRC - Start of a design rule checker (-g drc)
  
  	       6) DRC2 - A second design rule checker (-g drc2)
  
  	       7) gEDA - native format, mainly used for testing (-g geda)
  
  	       8) Gossip netlist format (-g gossip)
  
  	       9) PADS netlist format (-g pads)
  
  	       10) PCB / PCBboard (-g PCB and -g PCBboard)
  
  	       11) gsch2pcb backend (-g gsch2pcb)
  
  	       12) ProtelII netlist format (-g protelII)
  
  	       13) Spice compatible netlist format (-g spice)
  
  	       14) Enhanced spice compatible netlist format (-g spice-sdb)
  
  	       15) Switcap netlist format (-g switcap)
  
  	       16) Tango netlist format (-g tango)
  
  	       17) Verilog code (-g verilog)
  
  	       18) VHDL code (-g vhdl)
  
  	       19) VIPEC netlist format (-g vipec)
  
  	       20) Bartels Autoengineer netlist format (-g bae)
  
  	       21) GOSSIP system simulation system netlist format (-g gossip)
  
  	       22) MAXASCII netlist format (-g maxascii)
  
  	       23) VHDL-AMS netlist format (-g vams)
  
  	       24) Futurenet2 netlist format (-g futurenet2 )
  
  	       25)  SWITCAP  switched  capacitor  simulator netlist format (-g
         switcap )
  
  	       26) RF Cascade netlist format (-g cascade )
  
  	       27) RACAL-REDAC netlist format (-g redac )
  
  	       28) PCB actions file for forward annotating pin/pad names  from
  		schematic to layout (-g pcbpins)
  
  
         For more info on these formats please look at the README.*
  
         Please  read  the  official  (non-existant) documentation on how to use
         gnetlist, since this man page just describes the command line arguments
         and a few examples on how to run gnetlist.
  
  
  OPTIONS
         gnelist accepts the following options:
  
         -q      Quiet  mode  on.	  This	mode turns off all warnings/notes/mes-
  	       sages. (optional)
  
         -v      Verbose mode on.	 This mode gives as much feedback to the  user
  	       as possible. (optional)
  
         -g guile_procedure
  	       Specify	the  guile  procedure  which is executed to create the
  	       netlist.
  
         -o output_filename
  	       Specify the filename which will contain the  netlist  generated
  	       by gnetlist.  If this option is not specified the default file-
  	       name is &quot;output.net&quot;.
  
         -l scheme_file
  	       Specify a filename which contains scheme code to be loaded  and
  	       execute	before	any  backend  is loaded or any guile procedure
  	       (using -g flag) is executed.  This flag can be specified multi-
  	       ple times and can be used to pass information to backends.
  
         -m scheme_file
  	       Specify	a filename which contains scheme code to be loaded and
  	       execute after the backend is loaded but still before any	 guile
  	       procedure (using -g flag) is executed.  This flag can be speci-
  	       fied multiple times and can be  used  to	 pass  information  to
  	       backends.   This flag, for example, allows the user to override
  	       variables inside of the backends (such as paths).
  
         -c string
  	       Pass the specified  string  to  the  guile  interpreter.	  This
  	       allows  you to execute arbitrary guile scripts from the command
  	       line.  Be sure to surround the string  with  either  single  or
  	       double  quotes  to  satisfy  your shell.	 The string is execute
  	       before any init or netlist backend scheme  code	is  loaded  or
  	       executed.
  
         -I      Put  .INCLUDE &lt;filename&gt; in output file instead of model fileâ??s
  	       contents.
  
         -i      Interactive mode.  After the schematic is read  in  and	parsed
  	       then  go	 into  interactive  mode.  Interactive mode allows the
  	       user to execute guile procedures directly.
  
         -s      Sort output netlist (for Gnucap)
  
         schematic1 [... schematicN]
  	       At least one schematic file must	 be  specified.	  If  multiple
  	       schematics are specified then they are sequentially read in and
  	       parsed with the assumption that they are all part of  the  same
  	       design.	 It  is important that the schematic(s) follow all the
  	       options (ie last).
  
  
  EXAMPLES
         These examples assume that you have a stack_1.sch in the current direc-
         tory.
  
         gnetlist	 requires  that	 at least one schematic to be specified on the
         command line:
  
  	    ./gnetlist stack_1.sch
  
         This is not very useful since it does not direct gnetlist to do
         anything.
  
         Specify a guile procedure name to get gnetlist to output a netlist:
  
  	    ./gnetlist -g geda stack_1.sch
  
         The netlist output will be written to a file called &quot;output.net&quot;
         in the current working directory.
  
         You can specify the output filename by using the -o flag:
  
  	    ./gnetlist -g geda stack_1.sch -o stack.netlist
  
         The spice backend is run against the schematic(s) if you specify
         -g spice and the tango backend is run if you specify -g tango.
  
         To interact with the guile interpreter:
  
  	    ./gnetlist -i stack_1.sch
  
         You will get a prompt where you can execute guile procedures.
  
         To get a more verbose feedback as to what gnetlist is doing run
         with the -v flag:
  
  	    ./gnetlist -v -g geda stack_1.sch
  
  
  ENVIRONMENT
         No environment variables are used.
  
  
  AUTHOR
         Ales Hvezda and many others
  
  
  SEE ALSO
         gschem(1), gsymcheck(1)
  
  COPYRIGHT
         Copyright Â©  1999-2004 Ales Hvezda
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  
  Version			      December 31st, 2003		   gnetlist(1)</pre>
  
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gnetlist_users_guide" class="toc">gEDA gnetlist Users Guide</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#installation" class="toc">Installation</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#running_gnetlist" class="toc">Running gnetlist</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#schematic_symbol_requirements" class="toc">Schematic / symbol requirements</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#symbol_requirements" class="toc">Symbol requirements</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#schematic_requirements" class="toc">Schematic requirements</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#random_notes" class="toc">Random notes</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#hierarchy_support" class="toc">Hierarchy Support</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#specific_backend_info" class="toc">Specific backend info</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#scheme_backend_api" class="toc">Scheme backend API</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#overview1" class="toc">Overview</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#entry_point" class="toc">Entry Point</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#initialization_of_the_backend" class="toc">Initialization of the Backend</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#net_name_and_reference_designator_aliasing" class="toc">Net Name and Reference Designator Aliasing</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#debugging_hints" class="toc">Debugging Hints</a></span></div></li></ul>
  </li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gnetlist_users_guide" id="geda_gnetlist_users_guide">gEDA gnetlist Users Guide</a></h1>
  <div class="level1">
  
  <p>
  by: Ales Hvezda
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  September 21st, 2003
  </p>
  
  </div>
  <!-- SECTION [1-158] -->
  <h2><a name="introduction" id="introduction">Introduction</a></h2>
  <div class="level2">
  
  <p>
  This document describes how to use <strong>gnetlist</strong>. This document and <strong>gnetlist</strong> in general are pretty ALPHA, so keep that in mind as you use it to generate netlists. As all engineers know, it is very important that you do not blindly trust tools, assuming that they will always create correct output. <strong>gnetlist</strong> is certainly no exception to this rule. It is very important that you verify *every* netlists you create. As with most programs (including all the programs in gEDA), <strong>gnetlist</strong> comes with NO WARRANTY. Blah, I hate having to say that, but I&rsquo;m hoping that this warning will keep the user from assuming that <strong>gnetlist</strong> generates perfect netlists. Though if you find a bug, please let <strong>ahvezda@xxxxxxxxxxxxx</strong> know.<br/>
   This document is very rough, so please e-mail all corrections to <strong>ahvezda@xxxxxxxxxxxxx</strong> or file a bug report on the gEDA homepage at <a href="http://www.geda.seul.org/"; class="urlextern" title="http://www.geda.seul.org";  rel="nofollow">http://www.geda.seul.org</a>. Thanks!
  </p>
  
  </div>
  <!-- SECTION [159-1087] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  <strong>gnetlist</strong> is the gEDA netlister. It takes as input schematic files and produces a netlist. A netlist is a textual representation of a schematic. This textual representation has all of the connections between devices completely resolved. This means that all the connections associated with a net are grouped together. The netlister also handles hierarchies of schematics.<br/>
   <strong>gnetlist</strong> has a very  exible architecture. The main program, which is written in C, reads in a schematic (using routines from libgeda) and creates an internal representation of the schematic data. This internal representation is then manipulated by a backend which is responsible for writing the various netlist formats. The backend for each netlist format is written in scheme (specifically Guile). This architecture not only allows for an infinite number of netlist formats, but also allows the netlister to generate other reports (like bill of material lists).<br/>
   As of 20001006 <strong>gnetlist</strong> has scheme backends to support the following netlist formats:
  </p>
  <ol>
  <li class="level1"><div class="li"> PCB &amp; PCBboard - UNIX PCB netlist format.</div>
  </li>
  <li class="level1"><div class="li"> Allegro netlist format</div>
  </li>
  <li class="level1"><div class="li"> BAE netlist format</div>
  </li>
  <li class="level1"><div class="li"> BOM &amp; BOM2 - Bill of Material generators</div>
  </li>
  <li class="level1"><div class="li"> DRC - Start of a design rule checker</div>
  </li>
  <li class="level1"><div class="li"> gEDA - the native format of gEDA, mainly used for testing</div>
  </li>
  <li class="level1"><div class="li"> Gossip netlist format</div>
  </li>
  <li class="level1"><div class="li"> PADS netlist format</div>
  </li>
  <li class="level1"><div class="li"> ProtelII netlist format</div>
  </li>
  <li class="level1"><div class="li"> Spice compatible netlist format</div>
  </li>
  <li class="level1"><div class="li"> Tango netlist format</div>
  </li>
  <li class="level1"><div class="li"> Verilog code</div>
  </li>
  <li class="level1"><div class="li"> VHDL code</div>
  </li>
  <li class="level1"><div class="li"> VIPEC netlist format</div>
  </li>
  <li class="level1"><div class="li"> VAMS - VHDL-AMS netlist format</div>
  </li>
  </ol>
  
  <p>
   This list is constantly growing. Several lacking features (as of 20001006) are: no support for buses, error detection and reporting is fairly limited, and ... (many more).
  </p>
  
  </div>
  <!-- SECTION [1088-2791] -->
  <h2><a name="installation" id="installation">Installation</a></h2>
  <div class="level2">
  
  <p>
  Hopefully by now you have already installed <strong>gnetlist</strong> on your machine. This document does not cover installation. You can verify the installation by running:
  </p>
  <pre class="code">libgeda-config --version
  gesym-config --version
  which gnetlist
  ldd `which gnetlist`</pre>
  
  <p>
  The first two should return the version of the installed tools (libgeda and the symbol library) and the next command should return the path to the <strong>gnetlist</strong> binary. The final command (only on Unix-like operating systems which include the ldd utility for listing dynamic dependencies of executable files or shared objects) will return which libraries are linked to <strong>gnetlist</strong>; all of the request libraries must be found for <strong>gnetlist</strong> to run. If these commands do not return the expected results, then most likely the gEDA tools are not installed properly. Please see the appropriate INSTALL docs (which came with the distribution) for more info on installing the gEDA tools.
  </p>
  
  </div>
  <!-- SECTION [2792-3759] -->
  <h2><a name="running_gnetlist" id="running_gnetlist">Running gnetlist</a></h2>
  <div class="level2">
  
  <p>
  It is very easy to run <strong>gnetlist</strong>. <strong>gnetlist</strong> is a pure command line interface so there is no pesky <acronym title="Graphical User Interface">GUI</acronym> to get in the way <img src="lib/images/smileys/icon_smile.gif" class="middle" alt=":-)" /> For a list of command line arguments please run <code>gnetlist -h</code>.<br/>
   You need to specify the following two parameters to run gnetlists:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>-g pro</strong>c (this specifies which backend to run against the schematics)</div>
  </li>
  <li class="level1"><div class="li"> <strong>filename.sch</strong> (this specifies the schematic files)</div>
  </li>
  </ul>
  
  <p>
   You can specify multiple schematics on the command line. The default filename for the generated netlist goes into &ldquo;<strong>output.net</strong>&rdquo; You can change this default location by using the <strong>-o filename</strong> option.<br/>
   A few examples on running <strong>gnetlist</strong>: 
  </p>
  <pre class="code">gnetlist -g geda -o stack.net stack_1.sch</pre>
  
  <p>
  (output netlist (in <strong>stack.net</strong>) for <strong>stack_1.sch</strong> using the gEDA native format)
  </p>
  
  <p>
  There are also a few debugging flags. The first one is the <strong>-v</strong> flag which enables verbose mode. Verbose mode outputs a whole bunch of information on what <strong>gnetlist</strong> is doing as well a dump of the internal representation. The <strong>-i</strong> flag which puts <strong>gnetlist</strong> into a interactive mode is very useful in debugging scheme backends and typically is not used by the end user.<br/>
   For a detailed list of command line arguments please see the <strong>gnetlist</strong> man page.
  </p>
  
  </div>
  <!-- SECTION [3760-5041] -->
  <h2><a name="schematic_symbol_requirements" id="schematic_symbol_requirements">Schematic / symbol requirements</a></h2>
  <div class="level2">
  
  <p>
  This section describes what schematics/symbols need to have to be usable with <strong>gnetlist</strong>. In order for <strong>gnetlist</strong> to work correctly, both the schematics and supporting symbols must be correct. Basically these requirements consist of attribute specification. Attributes are used through out the gEDA system to represent information. Attributes are the only way of adding information to components, nets, pins, etc... For more detailed information about the attributes mentioned in this document, please see the  <a href="geda_master_attributes_list.html" class="wikilink1" title="geda:master_attributes_list">Master Attributes List</a> document.
  </p>
  
  </div>
  <!-- SECTION [5042-5666] -->
  <h3><a name="symbol_requirements" id="symbol_requirements">Symbol requirements</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> All symbols must have a <code>device=</code> attribute.</div>
  </li>
  <li class="level1"><div class="li"> All pins must have the <code>pin#=#</code> attribute. This attribute will eventually change form, but for now it is required as <code>pin#=#</code></div>
  </li>
  <li class="level1"><div class="li"> All pin should also have a <code>pinlabel=</code> attribute.</div>
  </li>
  <li class="level1"><div class="li"> For symbols which are slotted you also need the <code>slot=</code> attribute, for each slot a <code>slot#=#</code> attribute, and the <code>numslots=#</code> attribute. Slotting will also change in the near future, but for now it should be specified as above.</div>
  </li>
  <li class="level1"><div class="li"> For any power/gnd/arbitrary you need to put <code>net=</code> attributes inside the symbol. See the netattrib.txt document for more info.</div>
  </li>
  <li class="level1"><div class="li"> You can supply default values for various parameters (this is dependent on which backend you use) by taking advantage of the attribute &ldquo;promotion&rdquo; mechanism. See below for more info as well as the gschem documentation.</div>
  </li>
  <li class="level1"><div class="li"> For symbols which you want the netlister to completely ignore use the <code>graphical=1</code> attribute</div>
  </li>
  <li class="level1"><div class="li"> For more tips on symbols, please see the <a href="http://geda.seul.org/wiki/geda:scg"; class="wikilink1" title="geda:scg">Symbol Creation Guide</a>.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5667-6712] -->
  <h3><a name="schematic_requirements" id="schematic_requirements">Schematic requirements</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Most importantly, every component you want to show up in a netlist must have a <code>refdes=</code> attribute. This is <strong>VERY</strong> important. <strong>gnetlist</strong> should warn you if you have a component which doesn&rsquo;t have a <code>refdes=</code>, but there have been bugs which do not cause this warning.</div>
  </li>
  <li class="level1"><div class="li"> You can label all nets using the <code>label=</code> attribute. You only need to attach this label to one net segment (of an electrically connected net) for all the net segments to inherit the label.</div>
  </li>
  <li class="level1"><div class="li"> You can have multiple schematics in a design (which is actually a confusing term since it means many different things to people). To use multiple schematics to create a single netlist, just specify them on the <strong>gnetlist</strong> command line.</div>
  </li>
  <li class="level1"><div class="li"> If you name nets the same, then these nets will be electrically connected. Same net names spawn all the specified schematics.</div>
  </li>
  <li class="level1"><div class="li"> There are quite a few issues that deal with hierarchy please see the hierarchy section below.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6713-7689] -->
  <h3><a name="random_notes" id="random_notes">Random notes</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Attributes which are not attached to anything and are inside a symbol are &ldquo;promoted&rdquo; to the outside of the symbol when the symbol is placed inside a schematic (in gschem). These promoted attributes are always looked at/for first before going into the symbol. So, in other words, if there is an attribute with the same name is inside a symbol and attached to the outside of the instantiated component, then the outside attribute takes precedence.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [7690-8163] -->
  <h2><a name="hierarchy_support" id="hierarchy_support">Hierarchy Support</a></h2>
  <div class="level2">
  
  <p>
  TBA
  </p>
  
  </div>
  <!-- SECTION [8164-8198] -->
  <h2><a name="specific_backend_info" id="specific_backend_info">Specific backend info</a></h2>
  <div class="level2">
  
  <p>
  TBA
  </p>
  
  </div>
  <!-- SECTION [8199-8237] -->
  <h2><a name="scheme_backend_api" id="scheme_backend_api">Scheme backend API</a></h2>
  <div class="level2">
  
  <p>
  Please note that this section is still under construction. The information here should be correct, but it is not complete.
  </p>
  
  </div>
  <!-- SECTION [8238-8392] -->
  <h3><a name="overview1" id="overview1">Overview</a></h3>
  <div class="level3">
  
  <p>
  <strong>gnetlist</strong> operates by loading the schematic database from the .sch files, building an internal representation and then calling a function specific to the desired output netlist type which performs the actual netlisting. Each <strong>gnetlist</strong> backend is contained in a file called gnet-&lt;backend&gt;.scm. Where &lt;backend&gt; is the name of the particular backend. For example, gnet-switcap.scm contains the code used by &ldquo;gnetlist -g switcap&rdquo; and gnet-drc.scm contains the code used by &ldquo;gnetlist -g drc&rdquo;. The backends are written in the Scheme programming language. The particular implementation of scheme is guile which stands for GNU&rsquo;s Ubiquitous Intelligent Language for Extensions. More information about guile may be found at <a href="http://www.gnu.org/software/guile/guile.html"; class="urlextern" title="http://www.gnu.org/software/guile/guile.html";  rel="nofollow">http://www.gnu.org/software/guile/guile.html</a>.
  </p>
  
  </div>
  <!-- SECTION [8393-9182] -->
  <h3><a name="entry_point" id="entry_point">Entry Point</a></h3>
  <div class="level3">
  
  <p>
  Each netlist backend is required to provide a function whose name matches the netlist type. For example, the switcap backend contained in gnet-switcap.scm must provide a function called &ldquo;switcap&rdquo;. That is the function which <strong>gnetlist</strong> will call to initiate the netlisting. The entry point function is given a single argument which is the filename for the output netlist. Typically the first thing a netlister does is to open the output file for writing.<br/>
   The following excerpt from the switcap backend shows the start of the entry point function and shows the output file being opened. At the end of the function, the output file is closed. 
  </p>
  <pre class="code">;; ---------------------------------------
  ;; Switcap netlist generation -- top level
  ;; ---------------------------------------
  (define switcap
    (lambda (output-filename)
      (let ((port (open-output-file output-filename)))
  
  ;; rest of netlisting goes here
  
  ;; close the output file and return
        (close-output-port port))))</pre>
  
  </div>
  <!-- SECTION [9183-10192] -->
  <h3><a name="initialization_of_the_backend" id="initialization_of_the_backend">Initialization of the Backend</a></h3>
  <div class="level3">
  
  <p>
  After opening the output netlist, any specific initializations which must be done for the particular netlist are done. In the switcap example, we must initialize a net name and reference designator (refdes) aliasing database. This is because switcap has more restrictive requirements on its net names than gschem does. In addition, the reference designators in a switcap netlist have special requirements. To deal with this situation, <strong>gnetlist</strong> provides some general purpose functions which rename nets and reference designators to comply with the target netlist requirements. More details on this later. For now, just note that the switcap backend uses the following code:
  </p>
  <pre class="code">;; initialize the net-name aliasing
  (gnetlist:build-net-aliases switcap:map-net-names
      all-unique-nets)
  
  ;; initialize the refdes aliasing
  (gnetlist:build-refdes-aliases switcap:map-refdes
      packages)</pre>
  
  <p>
  The other initialization which is typically done, although not required by all netlist types, is to output some sort of header. This header may be explicitly contained in the entry point function or it may be contained in its own function for code clarity. In the switcap backend, the call is:
  </p>
  <pre class="code">(switcap:write-top-header port)</pre>
  
  <p>
  Note that the convention is for any backend specific functions to have their names prefixed by the backend name. For example all switcap specific functions begin with &ldquo;switcap:&rdquo;. Functions which are available to all backends and provided by <strong>gnetlist</strong> are prefixed by &ldquo;gnetlist:&rdquo;.<br/>
   The definition of &ldquo;switcap:write-top-header&rdquo; is 
  </p>
  <pre class="code">;;
  ;; Switcap netlist header
  ;;
  (define switcap:write-top-header
    (lambda (port)
      (display
        &quot;/* Switcap netlist produced by gnetlist (part of gEDA) */\n&quot;
        port)
      (display
        &quot;/* See http://www.geda.seul.org for more information. */\n&quot;
        port)
      (display
        &quot;/* Switcap backend written by Dan McMahill            */\n&quot;
        port)
      (display &quot;\n\n&quot; port)
      )
    )</pre>
  
  <p>
  The entry point function continues by calling functions for each section in the output netlist. The variable &ldquo;packages&rdquo; is predefined by <strong>gnetlist</strong> to be a list of all components in the design and &ldquo;all-unique-nets&rdquo; is a list of all the nets in the design. The various functions used by the backend for each section in the netlist will use these variables. For example, the main part of the switcap netlist which contains the components and their connectivity is written to the output file with 
  </p>
  <pre class="code">(switcap:write-netlist port packages)</pre>
  
  </div>
  <!-- SECTION [10193-12761] -->
  <h3><a name="net_name_and_reference_designator_aliasing" id="net_name_and_reference_designator_aliasing">Net Name and Reference Designator Aliasing</a></h3>
  <div class="level3">
  
  <p>
  It is common for a target netlist type to have a more restrictive requirement for the net names than gschem does. For example, there may be restrictions on length, allowed characters, or case. To address this issue, <strong>gnetlist</strong> provides a net name aliasing feature. To use this feature, the function &ldquo;gnetlist:build-netaliases&rdquo; is called as part of the initialization section of the entry point function.<br/>
   For example in the switcap backend, 
  </p>
  <pre class="code">;; initialize the net-name aliasing
  (gnetlist:build-net-aliases switcap:map-net-names
      all-unique-nets)</pre>
  
  <p>
  The function &ldquo;switcap:map-net-names&rdquo; is a backend specific (switcap in this case) function which accepts a gschem net name as an argument and returns a modified net name which meets the requirements for the output netlist format. In the case of switcap, the requirement is ground must be called &ldquo;0&rdquo;, nets may have no more than 7 characters, and the netlist is not case sensitive. 
  </p>
  <pre class="code">;; This procedure takes a net name as determined by
  ;; gnetlist and modifies it to be a valid SWITCAP net name.
  ;;
  (define switcap:map-net-names
    (lambda (net-name)
      (let ((rx (make-regexp &quot;^unnamed_net&quot;))
            (net-alias net-name)
            )
        ;; XXX we should use a dynamic regexp based on the
        ;; current value for the unnamed net base string.
  
        (cond
         ;; Change &quot;GND&quot; to &quot;0&quot;
         ((string=? net-name &quot;GND&quot;) (set! net-alias &quot;0&quot;))
         ;; remove the 'unnamed_net' part
         ((regexp-exec rx net-name)
             (set! net-alias (substring net-name 11)))
         (else net-name)
         )
  
        ;; Truncate to 7 characters
        (if (&gt; (string-length net-alias) 7)
            (set! net-alias (substring net-alias 0 7))
            )
  
    ;; Convert to all upper case
    (string-upcase net-alias)
  
    )
   )
  )</pre>
  
  <p>
  The function &ldquo;gnetlist:build-net-aliases&rdquo; creates a database which later on lets you look up the output net name from the gschem net name or the gschem net name from the output net name. In addition it does the very important task of ensuring that no shorts are created by modifying the net names. As an example suppose you had a net called &ldquo;MyNet&rdquo; and another called &ldquo;mynet&rdquo; in the schematic. Those are unique but after converting both to upper case they become a single net. &ldquo;gnetlist:build-net-aliases&rdquo; will detect this condition and issue an error and stop netlisting.<br/>
   Now that the database has been initialized, the netlister simply uses 
  </p>
  <pre class="code">(gnetlist:alias-net somenet)</pre>
  
  <p>
  to retrive the netlist net name from the gschem net name.<br/>
   A similar set of functions are provided for reference designator aliasing.
  </p>
  
  </div>
  <!-- SECTION [12762-15433] -->
  <h3><a name="debugging_hints" id="debugging_hints">Debugging Hints</a></h3>
  <div class="level3">
  
  <p>
  A useful debugging tool is to run <strong>gnetlist</strong> in interactive mode. This is done by using the &ldquo;-i&rdquo; option to <strong>gnetlist</strong>. This will give you a shell where you may enter scheme commands. This provides a simple way to examine various variables and try out various functions.<br/>
   An example of running <strong>gnetlist</strong> in interactive mode is shown below. 
  </p>
  <pre class="code">% gnetlist -i ../../gnetlist/examples/switcap/*.sch
  gEDA/gnetlist version 20041228
  gEDA/gnetlist comes with ABSOLUTELY NO WARRANTY; see COPYING for more details.
  This is free software, and you are welcome to redistribute it under certain
  conditions; please see the COPYING file for more details.
  
  Loading schematic [../../gnetlist/examples/switcap/analysis.sch]
  Loading schematic [../../gnetlist/examples/switcap/ckt.sch]
  Loading schematic [../../gnetlist/examples/switcap/clocks.sch]
  gnetlist&gt; all-unique-nets
    (&quot;unnamed_net6&quot; &quot;unnamed_net5&quot; &quot;unnamed_net4&quot; &quot;OUT&quot; &quot;unnamed_net3&quot;
     &quot;unnamed_net2&quot; &quot;unnamed_net1&quot; &quot;GND&quot;)
    gnetlist&gt; packages
    (&quot;TIMING&quot; &quot;CLK1&quot; &quot;S7&quot; &quot;S8&quot; &quot;S6&quot; &quot;S5&quot; &quot;C3&quot; &quot;S4&quot; &quot;C2&quot; &quot;C1&quot; &quot;E1&quot; &quot;S3&quot;
     &quot;S1&quot; &quot;V1&quot; &quot;S2&quot; &quot;OPTIONS&quot; &quot;TITLE&quot; &quot;ANA1&quot;)
    gnetlist&gt; (quit)
    %</pre>
  
  </div>
  <!-- SECTION [15434-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_grcsan.html
  
  Index: geda_grcsan.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gaf_rf_cascade_symbols_and_netlister" class="toc">gEDA/gaf RF Cascade Symbols and Netlister</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#requirements" class="toc">Requirements</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#creating_schematics" class="toc">Creating Schematics</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#extracting_the_cascade_input_file" class="toc">Extracting the Cascade Input File</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#running_cascade" class="toc">Running Cascade</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#appendix_a_--_symbols_in_the_library" class="toc">Appendix A -- Symbols in the Library</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#sources_cascade-source" class="toc">Sources (cascade-source)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#defaults_cascade-default" class="toc">Defaults (cascade-default)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#elements" class="toc">Elements</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#example" class="toc">Example</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#example_schematics" class="toc">Example Schematics</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#netlist_the_design" class="toc">Netlist the Design</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#run_the_analysis" class="toc">Run the Analysis</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_revision_history" class="toc">Document Revision History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gaf_rf_cascade_symbols_and_netlister" id="geda_gaf_rf_cascade_symbols_and_netlister">gEDA/gaf RF Cascade Symbols and Netlister</a></h1>
  <div class="level1">
  
  <p>
  by: Dan McMahill
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  December 3rd, 2003
  </p>
  
  </div>
  <!-- SECTION [1-173] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  This document describes the symbol library and gnetlist backend which support driving RF Cascade (<a href="http://rfcascade.sourceforge.net/"; class="urlextern" title="http://rfcascade.sourceforge.net";  rel="nofollow">http://rfcascade.sourceforge.net</a>) simulations from the gEDA/gaf system. Cascade is a noise figure and distortion analysis tool geared towards radio receiver design.<br/>
   The basic steps involved with using gEDA as the frontend for Cascade simulations are:
  </p>
  <ol>
  <li class="level1"><div class="li"> Create schematics of the circuit.</div>
  </li>
  <li class="level1"><div class="li"> Extract the netlist.</div>
  </li>
  <li class="level1"><div class="li"> Run Cascade.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [174-630] -->
  <h2><a name="requirements" id="requirements">Requirements</a></h2>
  <div class="level2">
  
  <p>
  You will need the following programs to be installed:
  </p>
  <ul>
  <li class="level1"><div class="li"> A recent version of gEDA/gaf. To see if your version is recent enough, see if the directory <strong><code>$prefix/share/gEDA/sym/cascade</code></strong> exists. <strong><code>$prefix</code></strong> is the installation prefix for gEDA on your system.</div>
  </li>
  <li class="level1"><div class="li"> RF Cascade. The executable is usually called cascade. If you do not have Cascade available on your system, you will need to get a copy from <a href="http://rfcascade.sourceforge.net/"; class="urlextern" title="http://rfcascade.sourceforge.net";  rel="nofollow">http://rfcascade.sourceforge.net</a>.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [631-1103] -->
  <h2><a name="creating_schematics" id="creating_schematics">Creating Schematics</a></h2>
  <div class="level2">
  
  <p>
  When creating a block diagram in the gschem schematic editor, use only the symbols from the cascade library. Every block diagram must have a \cascadesource&rdquo; element. In addition, the block diagram must be a simple cascade. No parallel paths or branches are allowed.<br/>
   All instances must have a unique reference designator. For a receiver block diagram, this is often times best achieved by manually entering them. The only restriction on reference designator names is that they contain no spaces. A descriptive name such as \RF Filter&rdquo; or \First Mixer&rdquo; is useful as it will show up in the cascade output report.
  </p>
  
  </div>
  <!-- SECTION [1104-1748] -->
  <h2><a name="extracting_the_cascade_input_file" id="extracting_the_cascade_input_file">Extracting the Cascade Input File</a></h2>
  <div class="level2">
  
  <p>
  To extract the Cascade input file, run: 
  </p>
  <pre class="code">gnetlist -g cascade -o test.cas file1.sch [file2.sch ...]</pre>
  
  <p>
  For the example file contained in this archive, you can run: 
  </p>
  <pre class="code">gnetlist -g cascade -o example.cas example.sch</pre>
  
  <p>
  The netlist will be left in <strong><code>example.cas</code></strong>.
  </p>
  
  </div>
  <!-- SECTION [1749-2078] -->
  <h2><a name="running_cascade" id="running_cascade">Running Cascade</a></h2>
  <div class="level2">
  
  <p>
  Cascade is exceptionally simple to run. Just run: 
  </p>
  <pre class="code">cascade example.cas &gt; example.out</pre>
  
  <p>
  to run the analysis on the system contained in the file <strong><code>example.cas</code></strong> and write the results to the file <strong><code>example.out</code></strong>. Refer to the Cascade documentation for complete details.
  </p>
  
  </div>
  <!-- SECTION [2079-2393] -->
  <h2><a name="appendix_a_--_symbols_in_the_library" id="appendix_a_--_symbols_in_the_library">Appendix A -- Symbols in the Library</a></h2>
  <div class="level2">
  
  <p>
  Please note that all instances must have the <strong><code>refdes=</code></strong> attribute set.
  </p>
  
  </div>
  <!-- SECTION [2394-2519] -->
  <h3><a name="sources_cascade-source" id="sources_cascade-source">Sources (cascade-source)</a></h3>
  <div class="level3">
  
  <p>
  Source. Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> C=Carrier level in dBm. Optional.</div>
  </li>
  <li class="level1"><div class="li"> CN0=Carrier to Noise Spectral Density Ratio in dBm/Hz. Optional.</div>
  </li>
  <li class="level1"><div class="li"> CN=Carrier to Noise Ratio in dB. Optional.</div>
  </li>
  <li class="level1"><div class="li"> BW=Signal Bandwidth in Hz. Optional, but requred if CN= is used.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2520-2798] -->
  <h3><a name="defaults_cascade-default" id="defaults_cascade-default">Defaults (cascade-default)</a></h3>
  <div class="level3">
  
  <p>
  This symbol sets the default impedance levels as well as the correlation coeffcient used for third order distortion calculations. There are two versions of this symbol. One is used to set the defaults at the beginnng of the definition. The other can be placed in series with the cascade to change the defaults part way through. This is useful if you wish to change impedance levels in the middle of the receiver chain. Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> RIN=Default block input resistance in Ohms. Optional.</div>
  </li>
  <li class="level1"><div class="li"> ROUT=Default block output resistance in Ohms. Optional.</div>
  </li>
  <li class="level1"><div class="li"> RHO=Default third order distortion correlation coeffcient. Optional.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2799-3458] -->
  <h3><a name="elements" id="elements">Elements</a></h3>
  <div class="level3">
  
  <p>
  Cascade characterizes each block in a system by its gain and optionally noise figure and third order intercept point. As such, there is no distinction between various elements such as amplifiers, filters, and mixers. The gEDA/gaf RF Cascade symbol library contains different symbols for clarity in the diagram only. The currently available element symbols are: Attributes: 
  </p>
  <table class="inline">
  	<tr>
  		<td>cascade-amp</td><td>Amplifier</td>
  	</tr>
  	<tr>
  		<td>cascade-filter</td><td>Filter</td>
  	</tr>
  	<tr>
  		<td>cascade-mixer</td><td>Mixer</td>
  	</tr>
  	<tr>
  		<td>cascade-transformer</td><td>Transformer</td>
  	</tr>
  	<tr>
  		<td colspan="2"> </td>
  	</tr>
  	<tr>
  		<td colspan="2"> Table 1: Element Types </td>
  	</tr>
  </table>
  <br />
  <ul>
  <li class="level1"><div class="li"> Gain is specified by one of the following:</div>
  <ul>
  <li class="level2"><div class="li"> <strong>G</strong>=Power gain in dB.</div>
  </li>
  <li class="level2"><div class="li"> <strong>GP</strong>=Power gain in dB.</div>
  </li>
  <li class="level2"><div class="li"> <strong>GV</strong>=Voltage gain in dB.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>NF</strong>=Noise Figure in dB. Optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong>IIP3</strong>=Input Third Order Intercept Point in dBm. Optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong>RIN</strong>=Block input resistance in Ohms. Optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong>ROUT</strong>=Block output resistance in Ohms. Optional.</div>
  </li>
  <li class="level1"><div class="li"> <strong>RHO</strong>=Third order distortion correlation coeffcient. Optional.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3459-4416] -->
  <h2><a name="example" id="example">Example</a></h2>
  <div class="level2">
  
  <p>
  This appendix provides a simple example of the entire process of generating a schematic, producing a Cascade input file, running an analysis and looking at the result.
  </p>
  
  </div>
  <!-- SECTION [4417-4605] -->
  <h3><a name="example_schematics" id="example_schematics">Example Schematics</a></h3>
  <div class="level3">
  
  <p>
  Figure 1 shows the schematic of a simple receiver signal chain.<br/>
   Figure 2 shows the contents of the example.cas file. 
  </p>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_rf_cascade_figure1.html" class="media" title="geda:rf_cascade_figure1.jpg"><img src="_media/geda_rf_cascade_figure1.jpg" class="media" title="rf_cascade_figure1.jpg" alt="rf_cascade_figure1.jpg" /></a> </td>
  	</tr>
  	<tr>
  		<td> <a href="_detail/geda_rf_cascade_figure2.html" class="media" title="geda:rf_cascade_figure2.jpg"><img src="_media/geda_rf_cascade_figure2.jpg" class="media" title="rf_cascade_figure2.jpg" alt="rf_cascade_figure2.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [4606-4829] -->
  <h3><a name="netlist_the_design" id="netlist_the_design">Netlist the Design</a></h3>
  <div class="level3">
  
  <p>
  To netlist the design, run: 
  </p>
  <pre class="code">gnetlist -g cascade example.cas example.sch</pre>
  
  </div>
  <!-- SECTION [4830-4944] -->
  <h3><a name="run_the_analysis" id="run_the_analysis">Run the Analysis</a></h3>
  <div class="level3">
  
  <p>
  Run the analysis with: 
  </p>
  <pre class="code">cascade example.cas</pre>
  
  </div>
  <!-- SECTION [4945-5028] -->
  <h2><a name="document_revision_history" id="document_revision_history">Document Revision History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td>December 3rd, 2003</td><td>Created cascade.tex</td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [5029-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_grenum_mp.html
  
  Index: geda_grenum_mp.html
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  <h1><a name="grenum_man-page" id="grenum_man-page">grenum man-page</a></h1>
  <div class="level1">
  <pre class="code">grenum(1)							     grenum(1)
  
  
  
  NAME
         grenum - An advanced refdes renumber utility
  
  
  SYNOPSIS
         grenum  [-v|--version  -h|--help -p|--pagejump] infile1.sch infile2.sch
         ...
  
  
  
  DESCRIPTION
         The grenum program will	renumber  the  refdes  definitions  read  from
         infile.
  
  
  OPTIONS
         -p, --pagejump
  	      This  will  switch on the page jump mode. It means that refdesÃ¢â?¬â?¢s
  	      from each inputfile gets renumbered from 100,200... etc.
  
         -v, --version
  	      prints version information
  
         -h, --help
  	      prints help message
  
  
  RETURN VALUE
         grenum will return 0 if all files processed successfully, -1  if	 there
         was  no	input file specified, -2 if I/O files canÃ¢â?¬â?¢t be opened/written,
         -3 if there is parse error in input file, -4 if	there  is  not	enough
         memory to store refdes prefixes.
  
  BUGS
         If you find one, please report it to:
  
  
  AUTHOR
         Levente Kovacs
  
         Levente.Kovacs@xxxxxxxxxxxx
  
  
  SEE ALSO
         gschem(1)
  
  
  
  								     grenum(1)
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  <h1><a name="gsch2pcb_gschem_to_pcb_readme" id="gsch2pcb_gschem_to_pcb_readme">gsch2pcb (gschem to PCB) README</a></h1>
  <div class="level1">
  <pre class="code">gsch2pcb
  --------
  gsch2pcb is a program that interfaces a set of schematics generated with
  with the gEDA gschem to PCB layout files.
  
  gsch2pcb is conceptually similar to the gschem2pcb shell script, but
  additionally handles multiple schematics, handles file element footprints,
  and removes pc board elements corresponding to components deleted from the
  schematics.  It also forward annotates component value changes.
  
  Using gsch2pcb allows you to drive all design changes from the gschem
  schematics without the headache of manually keeping PCB elements and
  element values in sync.
  
  It requires that the gnet-gsch2pcb.scm file be install into the gEDA
  scheme directory.  On Debian this is /usr/share/gEDA/scheme, but see
  the INSTALL file.
  
  Typical usage
  -------------
  1) Create your custom PCB elements and save each one into its own file.
     Some compatibility tips if you will be inserting elements into a
     layout manually as well as with gsch2pcb:
       *  Make the initial &quot;Description&quot; field of these elements the same
          as the file name because gsch2pcb depends on this name (which is
          the gschem footprint
          value) to know when footprints/elements are changed.
       *  Make the initial layout-name field (displayed when the &quot;name on PCB&quot;
          menu entry is selected) empty (ie &quot;&quot;) so that gsch2pcb
          will not delete your element when you want it to be in the layout
          even though it is not in the schematic.  You can later edit the
          layout-name to be some refdes value, but I'm not sure it makes sense
          to name a PCB element that is not referenced in the schematic.
  
     Note: since once a layout element is named PCB won't let you reset it
     to an empty name, a sort of kludge is that setting the first character
     of the layout-name to a non-alphanumeric will protect the element from
     being deleted by gsch2pcb.
  
     These file elements should be placed in a directory heirarchy that
     gsch2pcb will search.  The default directories /usr/local/pcb_lib and
     ./packages are searched in addition to any directories you specify with
     --elements-dir dirname arguments to gsch2pcb.
  
  2) Create your schematic with gschem.  Make sure each component has a
     unique refdes attribute and a footprint attribute that matches either
     a PCB m4 element or one of your custom file element names.  Beware of
     file element names that collide with PCB m4 macro names (or specify the
     use-files option).
     Make a project file if you wish.
  
  3) Run &quot;gsch2pcb foo.sch&quot; or &quot;gsch2pcb myproject&quot; if you've created the
     myproject file.  If you didn't specify an output name, this will generate
     a foo.pcb and a foo.net file.
     If you get errors about footprints not found, you need to create PCB
     elements for them and repeat this step until you get no errors.
     Or, just run gsch2pcb again and it will shift unfound elements to
     foo.new.pcb and you can proceed using PCB on foo.pcb if you wish to
     fix the errors from inside of PCB.
  
  4) Run &quot;pcb foo.pcb&quot;.  All the elements will be stacked on top of each other,
     so move them to desired locations.  Load the netlist file foo.net and
     proceed with using PCB.  
  
  5) Modify foo.sch and again run &quot;gsch2pcb foo.sch&quot;.
     * If components were added, PCB elements for them will be placed in the
       file foo.new.pcb.  If components were deleted, the elements for them
       will be removed from foo.pcb and the original foo.pcb will be renamed
       to a foo.pcb.bak sequence.
     * If elements can't be found for new schematic footprints, then the
       unfound elements will be indicated with PKG_ lines in foo.new.pcb
       unless you run &quot;gsch2pcb --remove-unfound foo.sch&quot; which will omit
       the PKG_ lines so you can go ahead and load foo.new.pcb into PCB.
     * Note that If you have added elements to the .pcb layout which
       will not exist on the schematics (mounting holes, etc), make sure
        there is no &quot;name on PCB&quot; (the gschem refdes) for them or else gsch2pcb
       will delete them when they don't match a schematic refdes and footprint.
       You could use the --preserve option to prevent deleting any elements at
       all, but this is really not the best way to use gsch2pcb.
  
  6) Run &quot;pcb foo.pcb&quot; and clean up any dangling traces left over from removed
     elements.  Load any new elements in foo.new.pcb with the &quot;Load layout
     data to paste-buffer&quot; function.  Load the new netlist foo.net.
  
  
  Caveats
  -------
  * gsch2pcb uses a gnetlist backend gnet-gsch2pcb.scm, so be sure when you
    install gsch2pcb that the gnet-gsch2pcb.scm file gets installed into the
    right place.  Look at the INSTALL file in the tarball.
  
  * WARNING:  if you wish to start processing with gsch2pcb any existing PCB
    files that have m4 elements and were originally generated with gschem2pcb,
    then be sure to run first with at least gsch2pcb 0.4:
  
       gsch2pcb --fix-elements
  
    on the PCB file schematics or else gsch2pcb will want to delete the
    m4 elements.
  
  * footprint information is saved into PCB element's Description fields,
    so it's probably not a good idea to change element Description values
    in your layout while using gsch2pcb unless it is a protected element
    that has an empty layout-name.
  
  
  
  Bill Wilson    billw@xxxxxx
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  <h1><a name="gschem2pcb_readme" id="gschem2pcb_readme">gschem2pcb README</a></h1>
  <div class="level1">
  <pre class="code">------------------------------------------------------------------
  JM Routoure. routoure@xxxxxxxxxxxxxx
  17/01/2000
  
  I would like to thank Stefan Petersen for debuging the scheme program.
  
  -------------------------------------------------------------------
  
  
  This document describes how to install (section I) and use (section II) the
  gschem2pcb package. Section III describes some of the footprints
  available in pcb
  
  The purpose of this package is to interface gschem with pcb. It uses a scheme 
  program and a script.
  
  
  Section I : Installation.
  
  1. Untar the gschem2pcb.tar. You must obtain 3 files gschem2pcb.sh, 
  GNET-PCBboard.scm and the README file.
  
  2. Move gschem2pcb.sh in a directory which is in your PATH (/usr/local/bin for
  instance ). Be sure that gschem2pcb.sh can be executed (chmod 755 gschem2pcb.sh)
  
  3. Move GNET-PCBboard.scm in the share directory of your gEDA distribution.
  Normally, it should be /usr/local/share/gEDA/scheme.
  
  4. Modify the common.m4 file of the pcb program (should be found in
  /usr/X11R6/lib/X11/pcb/m4/) like this : the include keywords at the end of the
  file  must be replace by
  
  include(/usr/X11R6/lib/X11/pcb/m4/connector.inc)
  include(/usr/X11R6/lib/X11/pcb/m4/dil.inc)
  include(/usr/X11R6/lib/X11/pcb/m4/misc.inc)
  include(/usr/X11R6/lib/X11/pcb/m4/plcc.inc)
  include(/usr/X11R6/lib/X11/pcb/m4/to.inc)
  include(/usr/X11R6/lib/X11/pcb/m4/qfp.inc)
  
  5. Edit the ~/.gEDA/gschemrc file and be sure that the following line exists : 
  (attribute-name &quot;footprint&quot;)
  
  
  6. Be sure that grep, sed and gawk are installed. That's all..
  
  
  Section II : using gschem2pcb.
  
  1. With gschem, create a schematic. All the device you want to have in pcb must
  have a Uref attribute. The footprint that you want to use in pcb are indicated
  by the footprint attribute (see section III for the description of the footprint
  in pcb)
  
  Be careful that the attributes Uref, name, value and device must not contain 
  space char.
  --------------------------------------------------------
  
  2. Save your work (ultralownoise.sch for instance -ambitious design!) and type in a shell
  
  	gschem2pcb.sh ultralownoise.sch.
  
  note : the gschem file must end by .sch
  
  Error messages will appear if some space characters are found in the
  attributes Uref, name, value and device and if the name of the footprint was not
  found. Warning, pcb files are created even if errors occur!
  
  - if  ultralownoise.pcb does not exist, it will be created. A netlist file
  ultralownoise.net will also be created. In pcb, load the pcb (load layout). All
  the footprints will appears at the top-left corner of the windows. Load the
  netlist (load netlist file) and type the key &quot;w&quot;. Place the footprints and type
  &quot;o&quot; to optimize the rastnet. See the pcb documentation for details.
  
  - if  ultralownoise.pcb exists, a ultralownoise.new.pcb file should be
  created. It should contain only the new device that have been added in the
  schematic since the last save of the ultralownoise.pcb file. Use &quot;load layout
  data to paste buffer&quot; to include the new footprints in the pcb file. The nestlist
  file is also updated so read it again. 
  
  
  Section III. Description of the name of the footprint in pcb. 
  pcb uses macro to define the footprints. For DIL packages, for instance, 2
  arguments are used to indicate the number of pins and the width in mil of the
  footprint. In gschem the footprint attribute of a 300 mil width and 8 pins DIL
  is: 
  DIL 8 300.
  Warning, for that attribute, you have to included the space char!
  
  In the following. I describe the footprint attribute that are to be used in
  gschem for the footprint avalaible in pcb. N stands
  for the number of pins, W the width in mil, L the length in mil and D the
  diameter in mil
  CONNECTOR ROWS COLS	# single connector
  DIN41_651LAY N		# DIN 41.651 laying
  DIN41_651STAND N	# DIN 41.651 standing
  SUBD_LAY_BASE N		# SUB-D connector laying
  SUBD_MALE_LAY_BASE N 	# SUB-D connector male laying
  SUBD_FEMALE_LAY_BASE N 	# SUB-D connector female laying
  DIL N W			# dual-inline standard
  D N			# dual inline with W=244
  DW N			# dual inline with W=419
  SD N			# SD (ZIP) 
  MULTIWATT15		# 15 pins multiwatt footprint
  R025			# standard 1/4W resistor !now attributes
  SIL N			# SIL 
  CSIL			# SIL package with a common pin
  QFP132			# QFP132 flat pack
  LED D			# standing LED
  DIODE_LAY L		# laying diode
  AXIAL_LAY L		# standard axial footprint
  CRYSTAL W		# crystal package
  OSC			# a can oscillator
  ISA8			# 8 bit ISA Slot card
  OVEN_OSC		# ovenized-oscillator package
  RADIAL_CAN W		# a radial capcitor package
  PLCC N			# pllc
  PLCC N add		# pllc with additionnal border add
  QFP N add		# qfp 	with additionnal border add
  No additional parameters for the to footprints
  TO3_90
  TO3_45
  TO5
  TO92
  TO126
  TO126LAY-WIDE
  TO126STAND-WIDE
  TO220
  TO220LAY-WIDE
  TO220STAND
  TO220STAND-WIDE
  
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  <h1><a name="gschem_man-page" id="gschem_man-page">gschem man-page</a></h1>
  <div class="level1">
  <pre class="code">gschem(1)			   20031231			     gschem(1)
  
  
  
  NAME
         gschem - gEDA/gaf Schematic Capture
  
  SYNOPSIS
         gschem  [-q]  [-v] [-t] [-r rcfilename] [-s scriptfilename] [-o output-
         filename] [-p] [schematic1 ... schematicN]
  
  DESCRIPTION
         gschem is the schematic capture program which is part gEDA  (GPL	 Elec-
         tronic  Design Automation) toolset.  This program is used to draw elec-
         tronic schematics.  Schematics consist of standard symbols  (which  are
         either  part of a standard library or created by the user) which repre-
         sent the various gates  and  components.	  These	 components  are  then
         interconnected  by  nets	 (wires).   Schematics	may  be	 printed  to a
         PostScript file for printing or further conversion to other output for-
         mats.
  
         gschem is also the symbol creation editor.  All the standard methods of
         creating schematics are used in the creation of symbols.	 There	are  a
         few  special  rules when creating symbols, so please refer to the (non-
         existant as of now) symbol creation document.
  
         Please read the official documentation (very minimal at this point)  on
         how  to use gschem, since this man page just describes the command line
         arguments and a few examples on how to run gschem.
  
  
  OPTIONS
         gschem accepts the following options:
  
         -q      Quiet mode on.  This mode  turns	 off  all  warnings/notes/mes-
  	       sages. (optional)
  
         -v      Verbose	mode on.  This mode gives as much feedback to the user
  	       as possible. (optional)
  
         -t      Print out more information when using mouse strokes.  With this
  	       command	line  flag  and the middle button configured for mouse
  	       strokes, gschem will output the stroke sequence numbers as  the
  	       user executes strokes.  These numbers can be used to define new
  	       strokes in the system-gschemrc file.
  
         -r filename
  	       Specify a rc filename.  Normally gschem searches for  the  sys-
  	       tem-gschemrc, then ~/.gEDA/gschemrc, and finally for a gschemrc
  	       in the current directory.  This	options	 allows	 the  user  to
  	       specify an additional rc file which is read after all the other
  	       rc files are read. (optional)
  
         -s filename
  	       Specify a guile script to be executed at startup. (optional)
  
         -o filename
  	       Specify a filename for postscript output.   This	 command  line
  	       argument	 is useful when running gschem from a shell script and
  	       with a guile script.  The filename can be changed  through  the
  	       print dialog box.
  
         -p      Automatically  place  the  window, especially useful if running
  	       gschem from the command line and generating output.
  
         schematic1 [... schematicN]
  	       Schematic file to be loaded.  Specifing	a  schematic  file  is
  	       optional.   If  multiple schematic files are specified they are
  	       read in sequentially and put on seperate pages.	It  is	impor-
  	       tant that the schematic(s) follow all the options (ie last).
  
  
  EXAMPLES
         These  examples	assume that you have a schematic called stack_1.sch in
         the current directory
  
         To run gschem and then interact with the program:
  
  	    ./gschem
  
         To run gschem in interactive mode but load a sample schematic:
  
  	    ./gschem adders_1.sch
  
         To run gschem and load up all schematics in the current subdirectory:
  
  	    ./gschem *.sch
  
  
  ENVIRONMENT
         No environment variables are used.
  
  
  AUTHOR
         Ales Hvezda and many others
  
  
  SEE ALSO
         gnetlist(1), gsymcheck(1)
  
  COPYRIGHT
         Copyright Â©  1999-2004 Ales Hvezda
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  
  Version			      December 31st, 2003		     gschem(1)</pre>
  
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gschem_user_guide" class="toc">gEDA gschem User Guide</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#about_this_document" class="toc">About this document ...</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#resources" class="toc">Resources</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#how_to_ask_questions" class="toc">How To Ask Questions</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#installing_gschem" class="toc">Installing gschem</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#latest_stable" class="toc">Latest Stable</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#geda_tools_suite_cd-rom" class="toc">&quot;gEDA Tools Suite&quot; CD-ROM</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#debian_distributions" class="toc">Debian distributions</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#red_hat_distributions" class="toc">Red Hat distributions</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#mac_osx_distributions" class="toc">Mac OSX distributions</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#cvs_unstable_testing" class="toc">CVS Unstable/Testing</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#configuring_gschem" class="toc">Configuring gschem</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#gschemrc" class="toc">gschemrc</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#gafrc" class="toc">gafrc</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#running_gschem" class="toc">Running gschem</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#confirming_gschem_is_installed" class="toc">Confirming gschem is installed</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#the_shell_prompt" class="toc">The Shell Prompt</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#backups" class="toc">Backups</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#classic_linux_backups" class="toc">Classic Linux backups</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#incremental_backups" class="toc">Incremental backups</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#relevant_configuration_settings" class="toc">Relevant configuration settings</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#on-line_documentation" class="toc">On-line documentation</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#electrical_connectivity" class="toc">Electrical Connectivity</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#components_symbols_objects_attributes" class="toc">Components &amp; Symbols &amp; Objects &amp; Attributes</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#components" class="toc">Components</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#symbols" class="toc">Symbols</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#objects" class="toc">Objects</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#attributes" class="toc">Attributes</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#the_main_window" class="toc">The Main Window</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#the_status_window" class="toc">The Status Window</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#the_schematic_file" class="toc">The Schematic File</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#the_symbol_file" class="toc">The Symbol File</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#symbol_libraries" class="toc">Symbol Libraries</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#the_log_file" class="toc">The Log File</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#grips" class="toc">Grips</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#menu_operations" class="toc">Menu Operations</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#file" class="toc">File</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#new_window_fw" class="toc">New Window (fw)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#new_page_fn" class="toc">New Page (fn)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#open_page..._fo" class="toc">Open Page... (fo)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#close_page_pc" class="toc">Close Page (pc)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#revert_page_pr" class="toc">Revert Page (pr)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#save_page_fs" class="toc">Save Page (fs)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#save_page_as..._fa" class="toc">Save Page As... (fa)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#save_all_fl_fl" class="toc">Save All (fl) (fl)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#print..._fp" class="toc">Print... (fp)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#write_png..._fi" class="toc">Write PNG... (fi)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#execute_script..._ft" class="toc">Execute Script... (ft)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#close_window_fc" class="toc">Close Window (fc)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#quit_alt-q" class="toc">Quit (Alt-q)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#edit" class="toc">Edit</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#undo_shift-u" class="toc">Undo (shift-u)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#redo_shift-r" class="toc">Redo (shift-r)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#select_mode_s" class="toc">Select Mode (s)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#edit..._ee" class="toc">Edit... (ee)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#edit_text..._ex" class="toc">Edit Text... (ex)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#copy_mode_ec" class="toc">Copy Mode (ec)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#move_mode_em" class="toc">Move Mode (em)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#delete_delete-key" class="toc">Delete (Delete-key)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#rotate_90_mode_er" class="toc">Rotate 90 Mode (er)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#mirror_mode_ei" class="toc">Mirror Mode (ei)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#slot..._e_shift-s" class="toc">Slot... (e shift-s)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#color..._eo" class="toc">Color... (eo)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#lock_el_unlock_e_shift-l" class="toc">Lock (el) / Unlock (e shift-l)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#line_width_type..._ew" class="toc">Line Width &amp; Type... (ew)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#fill_type..._ef" class="toc">Fill Type... (ef)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#symbol_translate..._et" class="toc">Symbol Translate... (et)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#embed_component_picture_eb" class="toc">Embed Component/Picture (eb)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#unembed_component_picture_eu" class="toc">Unembed Component/Picture (eu)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#update_component_ep" class="toc">Update Component (ep)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_hide_inv_text_en" class="toc">Show/Hide Inv Text (en)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#make_inv_text_vis_ev" class="toc">Make Inv Text Vis (ev)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#buffer" class="toc">Buffer</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#copy_into_1_2_3_4_5_yc" class="toc">Copy into 1/2/3/4/5 (yc)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#cut_into_1_2_3_4_5_yu" class="toc">Cut into 1/2/3/4/5 (yu)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#paste_from_1_2_3_4_5_yp" class="toc">Paste from 1/2/3/4/5 (yp)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#view" class="toc">View</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#redraw_vr" class="toc">Redraw (vr)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pan_x" class="toc">Pan (x)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#zoom_box_w" class="toc">Zoom Box (w)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#zoom_extents_ve" class="toc">Zoom Extents (ve)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#zoom_in_z" class="toc">Zoom In (z)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#zoom_out_z" class="toc">Zoom Out (Z)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#zoom_full_vf" class="toc">Zoom Full (vf)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#page" class="toc">Page</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#manager..._pm" class="toc">Manager... (pm)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#next" class="toc">Next (&gt;)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#previous" class="toc">Previous (&lt;)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#new_pe" class="toc">New (pe)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#revert_pr" class="toc">Revert (pr)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#close_pc" class="toc">Close (pc)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#discard_pd" class="toc">Discard (pd)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#add" class="toc">Add</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#component..._i" class="toc">Component... (i)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#net_n" class="toc">Net (n)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#bus_u" class="toc">Bus (u)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#attribute..._aa" class="toc">Attribute... (aa)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#text..._at" class="toc">Text... (at)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#line_l" class="toc">Line (l)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#box_b" class="toc">Box (b)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#circle_ai" class="toc">Circle (ai)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#arc_ar" class="toc">Arc (ar)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pin_ap" class="toc">Pin (ap)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#picture..._ag" class="toc">Picture... (ag)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#hierarchy" class="toc">Hierarchy</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#down_schematic_hd" class="toc">Down Schematic (Hd)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#down_symbol_hs" class="toc">Down Symbol (Hs)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#up_hu" class="toc">Up (Hu)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#documentation_ho" class="toc">Documentation (Ho)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#attributes1" class="toc">Attributes</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#attach_ta" class="toc">Attach (ta)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#detach_td" class="toc">Detach (td)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_value_tv" class="toc">Show Value (tv)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_name_tn" class="toc">Show Name (tn)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_both_tb" class="toc">Show Both (tb)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#toggle_visibility_tt" class="toc">Toggle Visibility (tt)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#find_specific_text..._t_shift-f" class="toc">Find Specific Text... (t shift-f)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#hide_specific_text..._th" class="toc">Hide Specific Text... (th)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_specific_text..._t_shift-h" class="toc">Show Specific Text... (t shift-h)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#autonumber_text..._tu" class="toc">Autonumber Text... (tu)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#options" class="toc">Options</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#text_size..._ot" class="toc">Text Size... (ot)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#toggle_grid_on_off_og" class="toc">Toggle Grid On/Off (og)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#toggle_snap_on_off_os" class="toc">Toggle Snap On/Off (os)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#snap_grid_spacing..._os" class="toc">Snap Grid Spacing... (oS)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#toggle_outline_box_oa" class="toc">Toggle Outline/Box (oa)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#toggle_net_rubberband_or" class="toc">Toggle Net/Rubberband (or)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_log_window_ol" class="toc">Show Log Window (ol)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#show_coord_window..._oc" class="toc">Show Coord Window... (oc)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#help" class="toc">Help</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#about..._ha" class="toc">About... (ha)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#manual..._hm" class="toc">Manual... (hm)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#hotkeys..._hh" class="toc">Hotkeys... (hh)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#component..._ho" class="toc">Component... (Ho)</a></span></div></li>
  </ul>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_a_--_heavy_vs_light_symbol_libraries" class="toc">Appendix A -- Heavy vs Light Symbol Libraries</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_b_--_printing_schematics_and_symbols" class="toc">Appendix B -- Printing Schematics and Symbols</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_c_--_writing_guile_scripts" class="toc">Appendix C -- Writing guile Scripts</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_d_--_i_want_to_build_a_printed_circuit_board" class="toc">Appendix D -- I Want To Build A Printed Circuit Board</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_e_--_i_want_to_simulate_my_design" class="toc">Appendix E -- I Want To Simulate My Design</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_f_--_change_gschemdoc_user-defined_preferences" class="toc">Appendix F -- Change gschemdoc User-Defined Preferences</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_g_--_breaking_a_large_symbol_into_smaller_symbols" class="toc">Appendix G -- Breaking a Large Symbol Into Smaller Symbols</a></span></div></li>
  <li class="level1"><div class="li"><span class="li"><a href="#appendix_h_--_definition_of_terms" class="toc">Appendix H -- Definition of Terms</a></span></div></li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gschem_user_guide" id="geda_gschem_user_guide">gEDA gschem User Guide</a></h1>
  <div class="level1">
  
  <p>
  by: Ales Hvezda / September 21st, 2003
  </p>
  
  <p>
  The latest version of this document may be found at: <a href="http://www.someplace.come/some-page.html"; class="urlextern" title="http://www.someplace.come/some-page.html";  rel="nofollow">http://www.someplace.come/some-page.html</a>
  </p>
  
  <p>
  This document is released under the <a href="geda_gfdl.html" class="wikilink1" title="geda:gfdl">GNU Free Documentation License (GFDL)</a>.
  </p>
  
  <p>
   Please report any errors/inconsistencies in this document by commenting in the Discussion area at the bottom of the associated page.
  </p>
  
  </div>
  <!-- SECTION [1-397] -->
  <h1><a name="about_this_document" id="about_this_document">About this document ...</a></h1>
  <div class="level1">
  
  <p>
  gEDA gschem Users Guide
  </p>
  
  <p>
  This document was generated using the LaTeX2HTML translator Version 2002-2-1 (1.70)
  </p>
  
  <p>
  Copyright Â© 1993, 1994, 1995, 1996, Nikos Drakos, Computer Based Learning Unit, University of Leeds. Copyright Â© 1997, 1998, 1999, Ross Moore, Mathematics Department, Macquarie University, Sydney.
  </p>
  
  <p>
  The command line arguments were: latex2html -local_icons gschem
  </p>
  
  <p>
  The translation was initiated by Ales Hvezda on 2005-08-20
  </p>
  
  </div>
  <!-- SECTION [398-870] -->
  <h1><a name="introduction" id="introduction">Introduction</a></h1>
  <div class="level1">
  
  <p>
  This document describes the installation, configuration, and operation of the <strong>gschem</strong> application.<br/>
   This document does not describe the process of generating schematics. For this, refer to the various tutorials on using the gEDA Tool Suite:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html";  rel="nofollow">Bill Wilson's gschem warmup</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">Bill Wilson's gsch2pcb tutorial</a></div>
  </li>
  <li class="level1"><div class="li"> &ldquo;Optical Proximity Sensor for Robots (Part 1), Simple PCB Design with the gEDA Suite&rdquo;, by Stuart Brorson (March 2006 Circuit Cellar article)</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf"; class="urlextern" title="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf";  rel="nofollow">Starting with gEDA at the Cambridge University Engineering Department</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/SPICE/t1.html"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/t1.html";  rel="nofollow">&quot;Circuit simulation using gEDA and SPICE -- HOWTO&quot; by Stuart Brorson</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.circuitcellar.com/magazine/176toc.htm"; class="urlextern" title="http://www.circuitcellar.com/magazine/176toc.htm";  rel="nofollow">&quot;gEDA Design Suite for Linux&quot; by Stuart Brorson, Ales Hvezda, &amp; Dan McMahill (03 Mar 2005 Circuite Cellar article)</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.linuxjournal.com/article/8438"; class="urlextern" title="http://www.linuxjournal.com/article/8438";  rel="nofollow">&quot;Circuit Design on Your Linux Box Using gEDA&quot; by Stuart Brorson (29 November 2005 Linux Journal article)</a></div>
  </li>
  <li class="level1"><div class="li"> Optical Proximity Sensor for Robots (Part 1): Simple PCB Design with the gEDA Suite, by Stuart Brorson, Circuit Cellar magazine, March 2006 (Issue 188), p. 48</div>
  </li>
  <li class="level1"><div class="li"> And, of course, <a href="http://www.google.com/search?hl=en&lr=&q=gEDA+%22schematic+capture%22+tutorial&btnG=Search"; class="urlextern" title="http://www.google.com/search?hl=en&amp;lr=&amp;q=gEDA+%22schematic+capture%22+tutorial&amp;btnG=Search";  rel="nofollow">Google is your friend</a>.</div>
  </li>
  </ul>
  
  <p>
   This document assumes you understand basic schematic capture concepts. For example: that a component represents something and that nets and buses interconnect these components to form a schematic, etc... For a basic understanding of the various work-flows available in the gEDA Tool Suite, please read the above tutorials. For more detailed understanding of specific tool issues, please refer to <a href="docs_20060124_gschem_ug_how_to_ask_questions.html" class="wikilink2" title="docs:20060124:gschem_ug:how_to_ask_questions">How To Ask Questions</a> and to the <a href="docs_20060124_gschem_ug_resources.html" class="wikilink2" title="docs:20060124:gschem_ug:resources">Resources</a>.
  </p>
  
  </div>
  <!-- SECTION [871-2899] -->
  <h1><a name="overview" id="overview">Overview</a></h1>
  <div class="level1">
  
  <p>
  <strong>gschem</strong> is the schematic capture program in the gEDA Tool Suite. Its purpose is to facilitate the graphical input of:
  </p>
  <ul>
  <li class="level1"><div class="li"> circuit schematics</div>
  </li>
  <li class="level1"><div class="li"> component symbols</div>
  </li>
  <li class="level1"><div class="li"> block diagrams</div>
  </li>
  </ul>
  
  <p>
   Once <strong>gschem</strong> has been used to enter the symbols/schematics for your design, several gEDA Tool Suite &ldquo;utility&rdquo; programs are used to extract information for other purposes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>gattrib</strong> &ndash; <strong>gattrib</strong> is a gEDA Tool Suite productivity aid. <strong>gattrib</strong> reads a [hierarchical set of] gschem schematic files and creates a spreadsheet showing all components in rows, with the associated component attributes listed in the columns. It allows the user to add, modify, or delete component attributes outside of <strong>gschem</strong>, and then save the .sch files.</div>
  </li>
  <li class="level1"><div class="li"> <strong>gnetlist</strong> &ndash; A tool that converts a [hierarchical set of] schematic files into an equivalent netlist (a textual representation of a schematic) in various formats. Various gnetlist back-ends are used to create:</div>
  <ul>
  <li class="level2"><div class="li"> Bill of Materials (BOM) files.</div>
  </li>
  <li class="level2"><div class="li"> Design Rule Checks (DRCs).</div>
  </li>
  <li class="level2"><div class="li"> Netlist files for use as input to various printed circuit board layout programs (e.g., Allegro, PADS, <strong>pcb</strong> (part of the gEDA Tool Suite), Protell, Tango, RACAL-REDAC, etc.).</div>
  </li>
  <li class="level2"><div class="li"> Files for input to SPICE simulation programs.</div>
  </li>
  <li class="level2"><div class="li"> VHDL code.</div>
  </li>
  <li class="level2"><div class="li"> Verilog code.</div>
  </li>
  <li class="level2"><div class="li"> etc.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>grenum</strong> &ndash; <strong>grenum</strong> is a gEDA Tool Suite productivity aid that will renumber the reference designators (i.e., refdes) in a [hierarchical set of] schematic files.</div>
  </li>
  <li class="level1"><div class="li"> <strong>gsch2pcb</strong> &ndash; The prefered method to create a netlist for the <strong>pcb</strong> printed circuit board layout tool (part of the gEDA Tool Suite).</div>
  </li>
  <li class="level1"><div class="li"> <strong>gspiceui</strong> &ndash; GNU Spice <acronym title="Graphical User Interface">GUI</acronym> (i.e., <strong>gspiceui</strong>) provides a <acronym title="Graphical User Interface">GUI</acronym> for freely available Spice electronic cicuit simulation engines (e.g., <strong>gnucap</strong> and <strong>ngspice</strong>). It uses <strong>gnetlist</strong> (to convert schematic files to net list files) and <strong>gwave</strong> (to display simulation results). gSchem is the preferred schematic capture tool.</div>
  </li>
  <li class="level1"><div class="li"> <strong>gsymcheck</strong> &ndash; A checker for symbols created with gEDA Tool Suite (e.g., <strong>gschem</strong>, <strong>tragesym</strong>, etc.).</div>
  </li>
  <li class="level1"><div class="li"> <strong>pcb</strong> &ndash; A tool for the layout of printed circuit boards.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes_renum</strong> &ndash; Reads a [hierarchical set of] <strong>gschem</strong> schematic files and renumbers all reference designators. The reference designators are numbered starting with 1 and the old schematic file is replaced by the modified schematic file.</div>
  </li>
  <li class="level1"><div class="li"> <strong>tragesym</strong> &ndash; A python script that creates geda symbols from structured textfiles. The symbols usually need to be &ldquo;cleaned up&rdquo; in gschem.</div>
  </li>
  </ul>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_gschem_workflow_01.html" class="media" title="geda:gschem_workflow_01.jpg"><img src="_media/geda_gschem_workflow_01.jpg" class="media" title="gschem_workflow_01.jpg" alt="gschem_workflow_01.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [2900-5480] -->
  <h1><a name="resources" id="resources">Resources</a></h1>
  <div class="level1">
  
  <p>
  The following on-line resources are useful for designers using <strong>gschem</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html";  rel="nofollow">Bill Wilson's gschem warmup tutorial</a> &ndash; If you are new to the gEDA tools, read this before you read Bill&rsquo;s &ldquo;Bill Wilson&rsquo;s gsch2pcb tutorial&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">Bill Wilson's gsch2pcb tutorial</a> &ndash; If you are new to the gEDA tools, this tutorial will bring you up to speed quickly.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.circuitcellar.com/"; class="urlextern" title="http://www.circuitcellar.com/";  rel="nofollow">Circuit Cellar Magazine</a> &ndash; Practical, hands-on applications and solutions for embedded designers:</div>
  <ul>
  <li class="level2"><div class="li"> gEDA Design Suite for Linux, by Stuart Brorson, Ales Hvezda, &amp; Dan McMahill, Circuit Cellar magazine, March 2005 (Issue 176), p. 12</div>
  </li>
  <li class="level2"><div class="li"> Optical Proximity Sensor for Robots (Part 1): Simple PCB Design with the gEDA Suite, by Stuart Brorson, Circuit Cellar magazine, March 2006 (Issue 188), p. 48</div>
  </li>
  <li class="level2"><div class="li"> Optical Proximity Sensor for Robots (Part 2): Open-Source PCB Layout Editor, by Stuart Borson, Circuit Cellar magazine, April 2006 (Issue 189), p. 40</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/index.html"; class="urlextern" title="http://www.geda.seul.org/index.html";  rel="nofollow">gEDA Project home page</a> &ndash; The homepage for the gEDA Tools Suite. A rather mature site, includes (but not limited to):</div>
  <ul>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/news/index.html"; class="urlextern" title="http://www.geda.seul.org/news/index.html";  rel="nofollow">News</a> &ndash; from 2002</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/screenshots/index.html"; class="urlextern" title="http://www.geda.seul.org/screenshots/index.html";  rel="nofollow">Screenshots</a> &ndash; <strong>gschem</strong> in action</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/tools/index.html"; class="urlextern" title="http://www.geda.seul.org/tools/index.html";  rel="nofollow">Tools</a> &ndash; links to project homepages</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/download.html"; class="urlextern" title="http://www.geda.seul.org/download.html";  rel="nofollow">Download</a> &ndash; <acronym title="International Organization for Standardization">ISO</acronym> images, binaries, and sources</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/mailinglist/index.html"; class="urlextern" title="http://www.geda.seul.org/mailinglist/index.html";  rel="nofollow">Lists</a> &ndash; e-mail list subscription and archives</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/docs/index.html"; class="urlextern" title="http://www.geda.seul.org/docs/index.html";  rel="nofollow">Docs</a> &ndash; current gEDA/gaf documentation (not gEDA Tools Suite documentation), wiki, slide presentations</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/developer.html"; class="urlextern" title="http://www.geda.seul.org/developer.html";  rel="nofollow">Devel</a> &ndash; nonymous <acronym title="Concurrent Versions System">CVS</acronym> access</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/search.html"; class="urlextern" title="http://www.geda.seul.org/search.html";  rel="nofollow">Search</a> &ndash; by Google</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.geda.seul.org/links.html"; class="urlextern" title="http://www.geda.seul.org/links.html";  rel="nofollow">Links</a> &ndash; links associated with gEDA, projects developed using gEDA Tools Suite, gEDA-related press</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <a href="http://sourceforge.net/tracker/?group_id=161080&atid=818426"; class="urlextern" title="http://sourceforge.net/tracker/?group_id=161080&amp;atid=818426";  rel="nofollow">gEDA Bug Tracker</a> &ndash; On SourceForge</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/dokuwiki/doku.php?id=geda"; class="urlextern" title="http://geda.seul.org/dokuwiki/doku.php?id=geda";  rel="nofollow">gEDA Project's Wiki</a> &ndash; All things related to the gEDA Tools Suite.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.gedasymbols.org/"; class="urlextern" title="http://www.gedasymbols.org";  rel="nofollow">gedasymbols.org</a> &ndash; On-line repository of user-developed symbols for <strong>gschem</strong>, SPICE models, and footprints for <strong>pcb</strong>.</div>
  </li>
  <li class="level1"><div class="li"> John C. Luciani&rsquo;s proposed <a href="http://www.luciani.org/geda/pcb/footprint-name-spec.pdf"; class="urlextern" title="http://www.luciani.org/geda/pcb/footprint-name-spec.pdf";  rel="nofollow">Land Pattern Naming Convention</a> &ndash; Footprint naming conventions document, used by him, and often used by those submitting to the <a href="http://www.gedasymbols.org/"; class="urlextern" title="http://www.gedasymbols.org";  rel="nofollow">gedasymbols.org</a> symbols/footprint repository.</div>
  </li>
  <li class="level1"><div class="li"> John C. Luciani&rsquo;s <a href="http://geda.seul.org/shared/HomePages/dhart/index.html"; class="urlextern" title="file:///shared/HomePages/dhart/index.html"  rel="nofollow">PCB Footprints Library</a> &ndash; A rather inclusive collection of non-<acronym title="GNU General Public License">GPL</acronym> licensed footprints and the scripts used to create them.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.opencollector.org/"; class="urlextern" title="http://www.opencollector.org/";  rel="nofollow">OpenCollector</a> carries listings and news for free EDA software and circuit designs. Open Collector supports gEDA.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf"; class="urlextern" title="http://alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf";  rel="nofollow">PCB Design Tutorial; RevA</a> &ndash; Document describing the process of taking a schematic to a pcb. Excellent for the beginner.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://pcblibraries.com/"; class="urlextern" title="http://pcblibraries.com/";  rel="nofollow">PCB Libraries website</a> &ndash; Advocates of the IPC standard Land Pattern (a.k.a., footprint) Naming Conventions and Land Pattern Calculators. A useful site if you have the money to subscribe to the services.</div>
  <ul>
  <li class="level2"><div class="li"> The free (windows-based) <a href="http://landpatterns.ipc.org/default.asp"; class="urlextern" title="http://landpatterns.ipc.org/default.asp";  rel="nofollow">IPC-7351 Land Pattern Viewer</a> is a very useful tool for viewing the latest IPC footprints.</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://www.pcblibraries.com/resources/LibDoc.asp"; class="urlextern" title="http://www.pcblibraries.com/resources/LibDoc.asp";  rel="nofollow">CAD Data Files to be used with PCB Libraries' IPC-7351A LP Programs</a> &ndash; please note the license restrictions.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <a href="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf"; class="urlextern" title="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf";  rel="nofollow">Starting with gEDA at the Cambridge University Engineering Department</a> &ndash; The Cambridge University Engineering Department&rsquo;s tutorial for using gEDA.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/"; class="urlextern" title="http://www.brorson.com/gEDA/";  rel="nofollow">Stuart Brorson's gEDA tools and tips</a> &ndash; gEDA related tools and information.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5481-9782] -->
  <h1><a name="how_to_ask_questions" id="how_to_ask_questions">How To Ask Questions</a></h1>
  <div class="level1">
  
  <p>
  <strong>gschem</strong> is an OpenSource, community driven, development. As such, the emphasis has been on developing the gEDA Tools Suite, not on developing commercial-level documentation and support. Much of the burden on learning how to use the gEDA Tools Suite applications is placed on the user, who must understand the basics of electronics, Electronics Design Automation (EDA), and the terminology used in schematic capture, circuit simulation, and printed circuit board design.<br/>
   As a typical OpenSource development, the gEDA Tools Suite development community provides timely and insightful response to user inquiries, but please perform the following steps before bothering the developers (they need to focus on making gEDA Tools Suite applications better, and you can actually learn to answer your own questions and become independent of the developers):
  </p>
  <ol>
  <li class="level1"><div class="li"> Read Rick Moen&rsquo;s <a href="http://www.catb.org/~esr/faqs/smart-questions.html"; class="urlextern" title="http://www.catb.org/~esr/faqs/smart-questions.html";  rel="nofollow">How To Ask Questions The Smart Way</a>, about how to ask for help. This is a must read for everybody.</div>
  </li>
  <li class="level1"><div class="li"> Read this document. I know, it&rsquo;s a lot to expect engineers to actually read a user&rsquo;s guide. The latest version of this document is maintained on the gEDA web-site at <span class="hilited">TBD</span>. The information should be here. If it isn&rsquo;t, comment to the fact in one of the on-line document&rsquo;s &ldquo;Discussion&rdquo; areas (at the bottom of each wiki-page). Helpful comments are clear, to the point, and may even contain the wording that should be inserted into the document.</div>
  </li>
  <li class="level1"><div class="li"> Read the <a href="http://geda.seul.org/dokuwiki/doku.php?id=geda:faq-gschem"; class="urlextern" title="http://geda.seul.org/dokuwiki/doku.php?id=geda:faq-gschem";  rel="nofollow">gschem Frequently Asked Questions (FAQ)</a> wiki-page. This on-line document is updated often to reflect user and developer experiences with <strong>gschem</strong>.</div>
  </li>
  <li class="level1"><div class="li"> Read the <a href="http://www.geda.seul.org/docs/current/index.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/index.html";  rel="nofollow">gEDA/gaf Documentation</a>. This information was installed on your computer if the gEDA Tools Suite was installed from the gEDA Tools Suite CD-ROM.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.google.com/"; class="urlextern" title="http://www.google.com";  rel="nofollow">Google</a> is your friend. People that have asked questions that obviously didnâ??t do any simple Google search will not be treated well when asking for help. This is particularly true if your problem is not unique to the gEDA Tools Suite applications.</div>
  </li>
  <li class="level1"><div class="li"> Ask for a pointer to the right direction. It is considered good &ldquo;net etiquette&rdquo; to ask for a pointer to information, so that you can learn where such information can be found, rather than have someone search the information for you.</div>
  </li>
  <li class="level1"><div class="li"> If you are software literate, look at the source code to see what it is doing.</div>
  </li>
  <li class="level1"><div class="li"> Subscribe to the gEDA e-mail lists (i.e., you can only post to the e-mail lists if you are a subscriber). Then:</div>
  <ol>
  <li class="level2"><div class="li"> Start reading recent messages in the <a href="http://archives.seul.org/geda/user/"; class="urlextern" title="http://archives.seul.org/geda/user/";  rel="nofollow">geda-user e-mail list archives</a>. Get a feel for the list&rsquo;s ettiquite so that you learn how to properly ask questions.</div>
  </li>
  <li class="level2"><div class="li"> Search the archives for issues similar to yours. You may find the question has been asked of the developers and users before, and answered.</div>
  </li>
  <li class="level2"><div class="li"> In the event that you can find no information concerning your problem, submit a concise description of the problem and a request for the type of help you are requesting.</div>
  </li>
  </ol>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [9783-12964] -->
  <h1><a name="installing_gschem" id="installing_gschem">Installing gschem</a></h1>
  <div class="level1">
  
  <p>
  As a mature OpenSource project, the gEDA Tools Suite and its components have been installed on many Linux distributions. The following are by no means the only methods of installing the gEDA Tools Suite and/or its components.
  </p>
  
  </div>
  <!-- SECTION [12965-13223] -->
  <h2><a name="latest_stable" id="latest_stable">Latest Stable</a></h2>
  <div class="level2">
  
  <p>
  <strong>gschem</strong> is a component of the gEDA/gaf set of tools which tend to integrate together in the development and maintenance of schematics and symbols. The term &ldquo;gaf&rdquo; stands for &ldquo;<em class="u">g</em>EDA <em class="u">a</em>nd <em class="u">f</em>riends&rdquo;). The gEDA/gaf applications are actually rather stable, and receive significant testing prior to release.<br/>
   There are multiple methods of installing <strong>gschem</strong>. The appropriate method depends on your distribution. See the following for some examples.
  </p>
  
  </div>
  <!-- SECTION [13224-13708] -->
  <h3><a name="geda_tools_suite_cd-rom" id="geda_tools_suite_cd-rom">&quot;gEDA Tools Suite&quot; CD-ROM</a></h3>
  <div class="level3">
  
  <p>
  The recommended method is installation from the &ldquo;gEDA Tools Suite&rdquo; CD-ROM, gratefully prepared by Stuart Brorson. The latest version of this CD-ROM is available on-line for free download as an <acronym title="International Organization for Standardization">ISO</acronym> image from the <a href="http://www.geda.seul.org/download.html"; class="urlextern" title="http://www.geda.seul.org/download.html";  rel="nofollow">gEDA Downloads</a> web-page. Simply burn this <acronym title="International Organization for Standardization">ISO</acronym> image to a CD-ROM using your favorite CD burning software (e.g., K3b, ...). Insert the CD-ROM, and if your computer supports autodetection of the CD-ROM, the built-in installation wizzard will launch. This wizzard will first check if your computer has some required software (informing you if you don&rsquo;t and optionally installing these if you want), then build all of the &ldquo;gEDA Tool Suite&rdquo; applications (including <strong>gschem</strong>) from source. The whole process can take 2 hours on a slower computer.
  </p>
  
  <p>
  If the installation wizzard did not launch, enter as follows to install the gEDA Tool Suite for access by all users on this computer (i.e., when prompted for the installation directory, enter something like: â??/usr/local/gEDA-20060124â??): <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0"><strong>sudo sh /media/cdrecorder/installer &ndash;log &ndash;verbose</strong></font></pre>
  </p>
  
  <p>
  The above command requires superuser permissions configured for the user invoking the command. If you do not have the proper permissions to execute this command, ask your administrator to install the gEDA Tool Suite for you.
  </p>
  
  <p>
  If the installation wizzard did not launch, enter as follows to install the gEDA Tool Suite for access by just the user doing the installation(i.e., when prompted for the installation directory, accept the default &ldquo;/home/{login id}/geda-install&rdquo;): <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0"><strong>sh /media/cdrecorder/installer &ndash;log &ndash;verbose</strong></font></pre>
  </p>
  
  </div>
  <!-- SECTION [13709-15395] -->
  <h3><a name="debian_distributions" id="debian_distributions">Debian distributions</a></h3>
  <div class="level3">
  
  <p>
  For Debian distributions, you may wish to download the <a href="http://www.geda.seul.org/download.html"; class="urlextern" title="http://www.geda.seul.org/download.html";  rel="nofollow">latest DEB binaries</a> prepared by Hamish Moffatt. These are not always current with the latest &ldquo;gEDA Tools Suite&rdquo; <acronym title="International Organization for Standardization">ISO</acronym> image above, and do not include many of the other tools available on the &ldquo;gEDA Tools Suite&rdquo; <acronym title="International Organization for Standardization">ISO</acronym> image.
  </p>
  
  </div>
  <!-- SECTION [15396-15744] -->
  <h3><a name="red_hat_distributions" id="red_hat_distributions">Red Hat distributions</a></h3>
  <div class="level3">
  
  <p>
  For Red Hat distributions (and possibly others) you may wish to download the latest RPM binaries]] prepared by Wojciech Kazubski.
  </p>
  
  </div>
  <!-- SECTION [15745-15907] -->
  <h3><a name="mac_osx_distributions" id="mac_osx_distributions">Mac OSX distributions</a></h3>
  <div class="level3">
  
  <p>
  For Mac OSX distributions you may wish to download the <a href="http://www.geda.seul.org/download.html"; class="urlextern" title="http://www.geda.seul.org/download.html";  rel="nofollow">latest Fink binaries</a> prepared by Charles Lepple.
  </p>
  
  </div>
  <!-- SECTION [15908-16087] -->
  <h2><a name="cvs_unstable_testing" id="cvs_unstable_testing">CVS Unstable/Testing</a></h2>
  <div class="level2">
  
  <p>
  For those already familiar with the gEDA/gaf applications on the &ldquo;gEDA Tools Suite&rdquo; CD-ROM, access to the <acronym title="Concurrent Versions System">CVS</acronym> repository is available. This is the latest developer source-code version of the application.<br/>
   Installation from <acronym title="Concurrent Versions System">CVS</acronym> is appropriate for those:
  </p>
  <ul>
  <li class="level1"><div class="li"> Seeking a solution to a specific problem that was submitted to the development team, to test the &ldquo;fix&rdquo; so that the developers can be informed that the &ldquo;fix&rdquo; works.</div>
  </li>
  <li class="level1"><div class="li"> With significant working knowledge of the &ldquo;gEDA Tools Suite&rdquo; and industry expertise, wishing to test the latest version of the application(s) prior to the next release. This usually requires access to several existing designs known to work in the current stable release of the &ldquo;gEDA Tools Suite&rdquo; <acronym title="International Organization for Standardization">ISO</acronym> image, so that comparisons can be made and issues brought to the attention of the developer/user community (via the e-mail lists).</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [16088-16978] -->
  <h1><a name="configuring_gschem" id="configuring_gschem">Configuring gschem</a></h1>
  <div class="level1">
  
  <p>
  Assume that you have installed the gEDA Tools Suite from CD-ROM (the most common installation method), and that you are ready to configure <strong>gschem</strong> to your personal likes. When installing, you were prompted for the path where the gEDA executables would be placed. The default was the <strong>/home/{login id}/geda-install</strong> directory, where {login id} is the username you logged into your account with, but you may have changed this to another directory on the computer. This directory is referred to below as the <strong>{binary-install-path}</strong> because this is where the gEDA binary executables are placed. If you forgot where the binaries were installed, simply issue the following command to find where <strong>gschem</strong> is installed (in this case the {binary-install-path} is <strong>/usr/local/gEDA-20060124</strong>): <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">% which gschem
  /usr/local/gEDA-20060124/bin/gschem
  %</font></pre>
  </p>
  
  <p>
  The gEDA Tools Suite applications follow normal Unix/Linux conventions for placement of configuration files; there are usually system-wide, user-wide, and project-specific configuration settings. The system-wide settings are placed in a sub-directory of the {binary-install-path}. The user-wide settings are placed in the user&rsquo;s home directory, also known as the login directory (referred to in Unix/Linux parlance as the <strong>$HOME</strong> directory). The project-specific settings are placed in a project-specific directory.<br/>
  
  </p>
  
  <p>
  Now that we know the above, we can configure <strong>gschem</strong>.<br/>
   <strong>gschem</strong> is highly configurable. All configuration is handled through the following resource files (written using the GNU Guile programming language, an interpreter for Scheme, a version of Lisp):
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>system-gschemrc</strong>: The system-wide initialization file for <strong>gschem</strong>. Installed in the {binary-install-path}/share/gEDA/system-gschemrc file, it is required for <strong>gschem</strong> to run. Users should not modify this file, but should override the settings in this file by creating their own $HOME/gschemrc file and/or &lsquo;pwd&rsquo;/gschemrc file and putting the new settings in those files. The {binary-install-path} directory is where your gEDA/gaf  executables were installed, including <strong>gschem</strong>. Depends on your install method. Refer to <a href="docs_20060124_gschem_ug_installing_gschem.html" class="wikilink2" title="docs:20060124:gschem_ug:installing_gschem">Installing gschem</a> for more details.</div>
  </li>
  <li class="level1"><div class="li"> <strong>$HOME/gschemrc</strong>: The per-user initialization file for <strong>gschem</strong>. Created by the user in the user&rsquo;s home directory. Settings placed in this file will override settings in the system-gschemrc file. Users should put settings in this file they want to apply to all of their sessions, such as (to change the default black background color scheme to a light background color scheme):</div>
  </li>
  </ul>
  
  <p>
  <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">; Load up a color scheme
  (load (string-append gedadatarc &quot;/gschem-lightbg&quot;)) ; light background</font></pre>
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>&lsquo;pwd&rsquo;/gschemrc</strong>: The per-project initialization file for <strong>gschem</strong>. Created by the user in the user&rsquo;s project directory. Settings placed in this file will override settings in both the system-gschemrc file and the $HOME/gschemrc file. Users should put settings in this file they want to apply to this particular project, such as (to autonumber reference designators when components are placed on the schematic):</div>
  </li>
  </ul>
  
  <p>
  <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">; Comment in this scheme code if you want automatic numbering when
  ; placing new component and copying components
  ;
  (load (string-append gedadatarc &quot;/scheme/auto-uref.scm&quot;))
  (add-hook! add-component-hook auto-uref)</font></pre>
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>system-gafrc</strong>: The system-wide initialization file for gEDA/gaf applications (includes <strong>gschem</strong>, <strong>gnetlist</strong>). Installed in the {binary-install-path}/share/gEDA/system-gafrc file, it is required for <strong>gschem</strong> to run. Users should not modify this file, but should override the settings in this file by creating their own $HOME/gafrc file and/or &lsquo;pwd&rsquo;/gafrc file and putting the new settings in those files. The {binary-install-path} directory is where your gEDA/gaf  executables were installed, including <strong>gschem</strong>. Depends on your install method. Refer to <a href="docs_20060124_gschem_ug_installing_gschem.html" class="wikilink2" title="docs:20060124:gschem_ug:installing_gschem">Installing gschem</a> for more details.</div>
  </li>
  <li class="level1"><div class="li"> <strong>$HOME/gafrc</strong>: The per-user initialization file for gEDA/gaf applications. Created by the user in the user&rsquo;s home directory. Settings placed in this file will override settings in the system-gafrc file. Users should put settings in this file they want to apply to all of their sessions. </div>
  </li>
  <li class="level1"><div class="li"> <strong>&lsquo;pwd&rsquo;/gafrc</strong>: The per-project initialization file for the gEDA/gaf applications. Created by the user in the user&rsquo;s project directory. Settings placed in this file will override settings in both the system-gafrc file and the $HOME/gafrc file. Users should put settings in this file they want to apply to this particular project. Settings such as the <strong>component-library</strong> or <strong>source-library</strong> keywords go into this file.</div>
  </li>
  <li class="level1"><div class="li"> <strong>gschem-gtkrc</strong>: Installed in the {binary-install-path}/share/gEDA/gschem-gtkrc file. Used to define the font for all gtk+ widgets in <strong>gschem</strong>.</div>
  </li>
  </ul>
  
  <p>
   A few comments about changing the files:
  </p>
  <ul>
  <li class="level1"><div class="li"> Don&rsquo;t break any guile syntax rules. Doing so will cause the scheme interpreter (guile) to stop interpreting.</div>
  </li>
  <li class="level1"><div class="li"> To add a setting to the $HOME/gschemrc file (or to the &lsquo;pwd&rsquo;/gschemrc file), copy the setting&rsquo;s text from the {binary-install-directory}/share/gEDA/system-gschemrc file to the $HOME/gschemrc file (or the &lsquo;pwd&rsquo;/gschemrc file) and make the setting change there.</div>
  </li>
  <li class="level1"><div class="li"> To add a setting to the $HOME/gafrc file (or the &lsquo;pwd&rsquo;/gafrc file), copy the relevant setting&rsquo;s text from the {binary-install-directory}/share/gEDA/system-gafrc file to the $HOME/gafrc file (or the &lsquo;pwd&rsquo;/gafrc file) and make the setting change there.</div>
  </li>
  <li class="level1"><div class="li"> Keywords/defaults always override what came before, with the exception of cumulative keywords (like component-library).</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [16979-22701] -->
  <h2><a name="gschemrc" id="gschemrc">gschemrc</a></h2>
  <div class="level2">
  
  <p>
  The {binary-install-path}/share/gEDA/system-gschemrc file is well commented. Read this file for more details on the settings available.<br/>
   Some of the settings appropriate for override (by placing in either the user&rsquo;s $HOME/gschemrc file or the project&rsquo;s &lsquo;pwd&rsquo;/gschemrc file) are:
  </p>
  
  </div>
  <!-- SECTION [22702-23003] -->
  <h2><a name="gafrc" id="gafrc">gafrc</a></h2>
  <div class="level2">
  
  <p>
  The {binary-install-path}/share/gEDA/system-gafrc file is well commented. Read this file for more details on the settings available.<br/>
   Some of the settings appropriate for override (by placing in either the user&rsquo;s $HOME/gafrc file or the project&rsquo;s &lsquo;pwd&rsquo;/gafrc file) are:
  </p>
  
  </div>
  <!-- SECTION [23004-23293] -->
  <h1><a name="running_gschem" id="running_gschem">Running gschem</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [23294-23323] -->
  <h2><a name="confirming_gschem_is_installed" id="confirming_gschem_is_installed">Confirming gschem is installed</a></h2>
  <div class="level2">
  
  <p>
  You should determine if <strong>gschem</strong> has been correctly installed on your Linux computer.<br/>
   Log into your Linux account, and launch your favorite interactive shell. The different Linux distributions will usually offer more than one interactive shell such as xterm, gnome-term, konsole, etc.<br/>
   You will see a shell prompt, which will depend on your Linux distribution and on your selection of interactive shell. It is common practice in Linux documentation to refer to the user&rsquo;s interactive login shell prompt as &ldquo;<strong>%</strong>&ldquo;, and to refer to the superuser&rsquo;s (i.e., user &ldquo;root&rdquo;) interactive login shell prompt as &ldquo;<strong>#</strong>&ldquo;.<br/>
   At the shell prompt, enter the following commands to determine if <strong>gschem</strong> is installed:
  </p>
  
  <p>
  <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">% <strong>echo $PATH</strong>
  <strong>/usr/local/gEDA-20060124/bin</strong>:/usr/kerberos/bin:/usr/local/bin:/bin:/usr/bin:/usr/X11R6/bin:/home/<strong>gEDA</strong>/bin
  % <strong>which gschem</strong>
  /usr/local/gEDA-20060124/bin/gschem
  % <strong>ldd /usr/local/gEDA-20060124/bin/gschem</strong>
      linux-gate.so.1 =&gt;  (0x00345000)
      libgeda.so.25 =&gt; /usr/local/gEDA-20060124/lib/libgeda.so.25 (0x00d7d000)
      libguile.so.12 =&gt; /usr/lib/libguile.so.12 (0x00588000)
      libguile-ltdl.so.1 =&gt; /usr/lib/libguile-ltdl.so.1 (0x00b62000)
      libqthreads.so.12 =&gt; /usr/lib/libqthreads.so.12 (0x009f7000)
      libpthread.so.0 =&gt; /lib/libpthread.so.0 (0x006d4000)
      libcrypt.so.1 =&gt; /lib/libcrypt.so.1 (0x03266000)
      libgdk-x11-2.0.so.0 =&gt; /usr/lib/libgdk-x11-2.0.so.0 (0x00c10000)
      libgdk_pixbuf-2.0.so.0 =&gt; /usr/lib/libgdk_pixbuf-2.0.so.0 (0x006ac000)
      libm.so.6 =&gt; /lib/libm.so.6 (0x008df000)
      libpangoxft-1.0.so.0 =&gt; /usr/lib/libpangoxft-1.0.so.0 (0x003e7000)
      libpangox-1.0.so.0 =&gt; /usr/lib/libpangox-1.0.so.0 (0x00a57000)
      libpango-1.0.so.0 =&gt; /usr/lib/libpango-1.0.so.0 (0x00bd8000)
      libgobject-2.0.so.0 =&gt; /usr/lib/libgobject-2.0.so.0 (0x00a01000)
      libgmodule-2.0.so.0 =&gt; /usr/lib/libgmodule-2.0.so.0 (0x009fb000)
      libdl.so.2 =&gt; /lib/libdl.so.2 (0x00906000)
      libglib-2.0.so.0 =&gt; /usr/lib/libglib-2.0.so.0 (0x0448e000)
      libgtk-x11-2.0.so.0 =&gt; /usr/lib/libgtk-x11-2.0.so.0 (0x06a81000)
      libatk-1.0.so.0 =&gt; /usr/lib/libatk-1.0.so.0 (0x00c96000)
      libSM.so.6 =&gt; /usr/X11R6/lib/libSM.so.6 (0x00d4f000)
      libICE.so.6 =&gt; /usr/X11R6/lib/libICE.so.6 (0x00d33000)
      libX11.so.6 =&gt; /usr/X11R6/lib/libX11.so.6 (0x00921000)
      libc.so.6 =&gt; /lib/libc.so.6 (0x007b4000)
      /lib/ld-linux.so.2 (0x00796000)
      libXrandr.so.2 =&gt; /usr/X11R6/lib/libXrandr.so.2 (0x00bac000)
      libXi.so.6 =&gt; /usr/X11R6/lib/libXi.so.6 (0x00cca000)
      libXinerama.so.1 =&gt; /usr/X11R6/lib/libXinerama.so.1 (0x00bb2000)
      libXft.so.2 =&gt; /usr/X11R6/lib/libXft.so.2 (0x00ad1000)
      libfreetype.so.6 =&gt; /usr/lib/libfreetype.so.6 (0x00af8000)
      libfontconfig.so.1 =&gt; /usr/lib/libfontconfig.so.1 (0x00111000)
      libXfixes.so.3 =&gt; /usr/X11R6/lib/libXfixes.so.3 (0x00d0d000)
      libXcursor.so.1 =&gt; /usr/X11R6/lib/libXcursor.so.1 (0x00bcc000)
      libXrender.so.1 =&gt; /usr/X11R6/lib/libXrender.so.1 (0x00ba2000)
      libXext.so.6 =&gt; /usr/X11R6/lib/libXext.so.6 (0x00a82000)
      libpangoft2-1.0.so.0 =&gt; /usr/lib/libpangoft2-1.0.so.0 (0x05362000)
      libexpat.so.0 =&gt; /usr/lib/libexpat.so.0 (0x0068b000)
      libz.so.1 =&gt; /usr/lib/libz.so.1 (0x0090c000)</font></pre>
  </p>
  
  <p>
  The <strong>echo $PATH</strong> command displays the user&rsquo;s current setting for the <strong>PATH</strong> environment variable. In the above example for a Fedora Core 4 installation, user <strong>gEDA</strong> executed the command and determined that the <strong>PATH</strong> included the /usr/local/gEDA-20060124/bin directory (this will differ depending on where you put the gEDA Tools Suite executables). If you installed from the gEDA Tools Suite CD-ROM (the most common method of installing the gEDA tools), as the last step of the installation wizzard you were prompted to:
  </p>
  <ol>
  <li class="level1"><div class="li"> Set your $PATH environment variable to {the directory in which the install wizzard installed gEDA&rsquo;s executables}</div>
  </li>
  <li class="level1"><div class="li"> Set your $LD_LIBRARY_PATH environment variable to {the directory in which the install wizzard installed gEDA&rsquo;s libraries}</div>
  </li>
  </ol>
  
  <p>
   The <strong>which</strong> command displays the full path of a command&rsquo;s executable, searching for the command on the user&rsquo;s list of directories, as defined in the <strong>PATH</strong> environment variable. In this case, it will return the full path to the <strong>gschem</strong> executable if it is on the user&rsquo;s <strong>PATH</strong>. If this command does not return the full path to the <strong>gschem</strong> executable, make sure your <strong>PATH</strong> environment variable has been properly set.
  </p>
  
  <p>
  The <strong>ldd</strong> command displays shared libraries required by a program. All of the requested libraries must be found for <strong>gschem</strong> to run. Don&rsquo;t be intimidated by the long list of libraries, this is common for mature Linux applications. If we had not received this output (or something very similar), we would have to check on our setting for the <strong>LD_LIBRARY_PATH</strong> environment variable.
  </p>
  
  <p>
  And of course, there is always attempting to just run <strong>gschem</strong> as follows: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">%  <strong>gschem -h</strong>
  Usage: gschem [OPTIONS] schematic_filename1 ... schematic_filenameN
    -q            Quiet mode
    -v            Verbose mode on
    -r filename   Rc filename
    -s filename   Script (guile) filename
    -o filename   Output filename (for printing)
    -p            Automatically place the window
    -t            Print stroke information
    -h            Help; this message</font></pre>
  </p>
  
  <p>
  where we displayed the <strong>gschem</strong> help.
  </p>
  
  <p>
  If these commands do not return the expected results, then most likely the gEDA tools are not installed properly. Please see the appropriate INSTALL docs (which came with the gEDA distribution) for more info on installing the gEDA tools. If you installed from the gEDA Tools Suite CD-ROM, read the INSTALL document on the CD-ROM first.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [23324-29029] -->
  <h2><a name="the_shell_prompt" id="the_shell_prompt">The Shell Prompt</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_terminal_screenshot_001.html" class="media" title="geda:terminal_screenshot_001.jpg"><img src="_media/geda_terminal_screenshot_001.jpg" class="media" title="terminal_screenshot_001.jpg" alt="terminal_screenshot_001.jpg" /></a> </td>
  	</tr>
  	<tr>
  		<td> Figure 1 &ndash; gnome-terminal </td>
  	</tr>
  </table>
  <br />
  
  <p>
   You launch <strong>gschem</strong> from your favorite shell prompt (in this case, gnome-terminal on Fedora Core 4).<br/>
   There are several command-line switches:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>-q</strong> &ndash; Quiet mode<br/>
   Turns on &ldquo;quiet mode&rdquo;. Output (i.e., stdout and stderr) is not generated to the shell. Useful if calling <strong>gschem</strong> from a script (e.g., bash, sh, csh, etc.) to perform batch operations such as printing a large number of schematics or symbols.</div>
  </li>
  <li class="level1"><div class="li"> <strong>-v</strong> &ndash; Verbose mode ON<br/>
   Generate verbose information. Not used very much in <strong>gschem</strong>.</div>
  </li>
  <li class="level1"><div class="li"> <strong>-r filename</strong> &ndash; Process additional configuration settings from <strong>filename</strong><br/>
   <strong>filename</strong> is a file containing settings of the form found in either system-gschemrc or system-gafrc<br/>
   In addition to the following files, <strong>gschem</strong> will process <strong>filename</strong> for additional configuration settings:<br/>
     * {binary-install-path}/share/gEDA/system-gschemrc<br/>
     * $HOME/gschemrc<br/>
     * &lsquo;pwd&rsquo;/gschemrc<br/>
     * {binary-install-path}/share/gEDA/system-gafrc<br/>
    * $HOME/gafrc<br/>
     * &lsquo;pwd&rsquo;/gafrc</div>
  </li>
  <li class="level1"><div class="li"> <strong>-s filename</strong> &ndash; Process <strong>filename</strong> as a guile script<br/>
   The name of a script file (written in guile) for <strong>gschem</strong> to process.<br/>
   Refer to <a href="docs_20060124_gschem_ug_app_b.html" class="wikilink2" title="docs:20060124:gschem_ug:app_b">Appendix B -- Printing Schematics and Symbols</a> and <a href="docs_20060124_gschem_ug_app_c.html" class="wikilink2" title="docs:20060124:gschem_ug:app_c">Appendix C -- Writing guile Scripts</a> for more details.<br/>
   For example, in your $HOME/geda-sources/gedagaf/{gEDA Tools Suite version}/scripts/ directory is the <strong>print.scm</strong> file, a template script file directing <strong>gschem</strong> to generate a PostScript file of a schematic appropriate for printing. This <strong>print.scm</strong> file works as is, but you may want to customize it for your own needs. To print the schematic_1.sch schematic to the schematic_1.ps PostScript file from within a bash script, you would enter: <code>gschem  -q -p -o schematic_1.ps -s print.scm schematic_1.sch</code><br/>
   Then, simply use your favorite printing solution to print the file, such as: <code>lp schematic_1.ps</code><br/>
   to a PostScript printer.</div>
  </li>
  <li class="level1"><div class="li"> <strong>-o filename</strong> &ndash; Output <strong>filename</strong> (e.g., for printing)<br/>
   Specify the output filename. For example, as used to specify the Postscript filename in the example above.</div>
  </li>
  <li class="level1"><div class="li"> <strong>-p</strong> &ndash; Automatically place the window<br/>
   Don&rsquo;t wait for the windowmanager to place the window.<br/>
   When a new window is opened, some window managers display the bounding box of the window and wait for the user to place the window manually. The &ldquo;-p&rdquo; option avoids that, letting the window manager decide where to put the new window.</div>
  </li>
  <li class="level1"><div class="li"> <strong>-t</strong> &ndash; Print stroke information<br/>
   </div>
  </li>
  <li class="level1"><div class="li"> <strong>-h</strong> &ndash; Help<br/>
   Generate a short usage printout.</div>
  </li>
  </ul>
  
  <p>
   Running <strong>gschem</strong> is straightforward once you have installed it on your GNU/Linux system.<br/>
   Although <strong>gschem</strong> is a <acronym title="Graphical User Interface">GUI</acronym> application, <strong>gschem</strong> is meant to be launched from the command-line, as it takes command-line arguements (see Figure 1 above).<br/>
   To open an empty schematic, run: <code><strong>% gschem</strong></code><br/>
  
  </p>
  
  <p>
  To open a specific schematic, run: <code><strong>% gschem schematic_name.sch</strong></code><br/>
  
  </p>
  
  <p>
  To open a list of schematics, run: <code><strong>% gschem schematic_1.sch schematic_2.sch, schematic_3.sch ...</strong></code><br/>
   or use wildcards to specify multiple filenames: <code><strong>% gschem schematic_*.sch</strong></code>
  </p>
  
  <p>
  As operations are performed in the <strong>gschem</strong> <a href="docs_20060124_gschem_ug_the_main_window.html" class="wikilink2" title="docs:20060124:gschem_ug:the_main_window">Main Window</a> the <strong>gschem</strong> <a href="docs_20060124_gschem_ug_the_status_window.html" class="wikilink2" title="docs:20060124:gschem_ug:the_status_window">Status Window</a> continues to output information, and the shell prompt&rsquo;s window continues to output information, consisting of:
  </p>
  <ul>
  <li class="level1"><div class="li"> ...</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [29030-32564] -->
  <h2><a name="backups" id="backups">Backups</a></h2>
  <div class="level2">
  
  <p>
  There are two basic mechanisms in <strong>gschem</strong> for backing up schematics and symbols, classic Linux backups and incremental backups.
  </p>
  
  </div>
  <!-- SECTION [32565-32716] -->
  <h3><a name="classic_linux_backups" id="classic_linux_backups">Classic Linux backups</a></h3>
  <div class="level3">
  
  <p>
  While creating and/or editing schematic file(s) or symbol file(s), snapshots are triggered by the <strong>autosave</strong> interval setting in the {binary-install-path}/share/gEDA/system-gschemrc file (see <a href="#relevant_configuration_settings" title="geda:gschem_ug &crarr;" class="wikilink1">Relevant configuration settings</a> below). If the file has not been manually saved, and the interval expires (current default 2 minutes), the snapshot is saved the next time a change is made in the <strong>gschem</strong> main window (to either a schematic or to a symbol). The interval timer starts again as soon as the snapshot file(s) have been written, and once the timer expires the next change to the main window will trigger the snapshot to be written.<br/>
   This snapshot includes all work up to, but not including, the last operation performed in the <strong>gschem</strong> main window. This is to allow for easier recovery from a crash that may have been caused by the last operation.<br/>
   When <strong>gschem</strong> exits normally, the snapshot file(s) are deleted. So, if <strong>gschem</strong> were to crash, or not terminate normally for some reason (e.g., power failure, soda &rarr; keyboard, etc.), the shapshot file(s) would be found the next time <strong>gschem</strong> opened the file(s). <strong>gschem</strong> will display the following warning message when it finds a snapshot file associated with the schematic file(s) or symbol file(s) it opens: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">WARNING: Found and autosave backup file:
    {full path to autosave file}
  
  The backup copy is newer than the schematic, so it seems you
  should load it instead of the original fil.
  Gschem usually makes backup copies automatically, and this
  situation happens when it crashed or it was forced to exit
  abruptely.
  
  If you load the original file, the backup file will be overwritten in
  the next autosave timeout and it will be lost.
  
  Do you want to load the backup file?</font></pre>
  </p>
  
  <p>
  The snapshots are saved to a file whose filename is constructed from the original filename (schematic or symbol) as follows:
  </p>
  <ul>
  <li class="level1"><div class="li"> add a &ldquo;#&rdquo; to the beginning of the original filename</div>
  </li>
  <li class="level1"><div class="li"> add a &ldquo;#&rdquo; to the end</div>
  </li>
  </ul>
  
  <p>
   so that:
  </p>
  <ul>
  <li class="level1"><div class="li"> &ldquo;schematic_1.sch&rdquo; becomes &ldquo;#schematic_1.sch#&rdquo;</div>
  </li>
  <li class="level1"><div class="li"> &ldquo;symbol.sym&rdquo; becomes &ldquo;#symbol.sym#&rdquo;</div>
  </li>
  </ul>
  
  <p>
   And yes, the &ldquo;#&rdquo; at the front and back of the filename are part of the filename.<br/>
  
  </p>
  
  <p>
  When the user does finally manually save the file, the original file (i.e., the file that was opened) is renamed to &ldquo;{filename~}&rdquo; and the latest snapshot file (i.e., &ldquo;#{filename}#&rdquo;) gets copied as &ldquo;{filename}&rdquo;. Note that this new &ldquo;{filename}&rdquo; file may not contain the latest information as displayed on the <strong>gschem</strong> main window, as the <strong>autosave</strong> interval timer may not have expired since the last change to the schematic/symbol.<br/>
   When the user finally decides to close <strong>gschem</strong>, the latest snapshot file (i.e., &ldquo;#{filename}#&rdquo;) is saved to the original file (i.e., &ldquo;{filename}&rdquo;.<br/>
   When you exit <strong>gschem</strong> and are prompted to save any unsaved schematic file(s) or symbol file(s), this constitutes a manual save.
  </p>
  
  </div>
  <!-- SECTION [32717-35623] -->
  <h3><a name="incremental_backups" id="incremental_backups">Incremental backups</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [35624-35657] -->
  <h3><a name="relevant_configuration_settings" id="relevant_configuration_settings">Relevant configuration settings</a></h3>
  <div class="level3">
  
  <p>
  There are the following configuration settings in the {binary-install-path}/share/gEDA/system-gschemrc file that effect backups:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>undo-control</strong> : Controls if the undo feature is enabled or not.</div>
  </li>
  <li class="level1"><div class="li"> <strong>undo-levels</strong> : Determines the number of levels of undo. Basically this number decides how many backup schematics are saved.</div>
  </li>
  <li class="level1"><div class="li"> <strong>undo-type</strong> : Controls which kind of undo is used, disk or memory. The default is to use the disk as the storage medium (i.e., after every action the undo information is stored to a new file on disk). The disk mechanism is nice because you get that many backups of the schematic, written to disk as backups, so you should never lose a schematic due to a crash.</div>
  </li>
  <li class="level1"><div class="li"> <strong>autosave</strong> : Controls if a backup copy is made every &ldquo;interval&rdquo; seconds. Note that a backup copy is only made when you make some change to the schematic, and there were more than &ldquo;interval&rdquo; seconds from the last autosave. Autosaving will not be allowed if the &ldquo;interval&rdquo; setting is set to zero.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [35658-36699] -->
  <h2><a name="on-line_documentation" id="on-line_documentation">On-line documentation</a></h2>
  <div class="level2">
  
  <p>
  For a listing of the various command line flags run &ldquo;<strong>gschem -h</strong>&ldquo;: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">% <strong>gschem -h</strong>
  Usage: gschem [OPTIONS] schematic_filename1 ... schematic_filenameN
    -q            Quiet mode
    -v            Verbose mode on
    -r filename   Rc filename
    -s filename   Script (guile) filename
    -o filename   Output filename (for printing)
    -p            Automatically place the window
    -t            Print stroke information
    -h            Help; this message</font></pre>
  </p>
  
  <p>
  For a detailed explanation of the command line flags look at the <strong>gschem</strong> man page: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">% <strong>man gschem</strong>
  gschem(1)			   20031231			     gschem(1)
  
  
  
  NAME
         gschem - gEDA/gaf Schematic Capture
  
  SYNOPSIS
         gschem  [-q]  [-v] [-t] [-r rcfilename] [-s scriptfilename] [-o output-
         filename] [-p] [schematic1 ... schematicN]
  
  DESCRIPTION
         gschem is the schematic capture program which is part gEDA  (GPL	 Elec-
         tronic  Design Automation) toolset.  This program is used to draw elec-
         tronic schematics.  Schematics consist of standard symbols  (which  are
         either  part of a standard library or created by the user) which repre-
         sent the various gates  and  components.	  These	 components  are  then
         interconnected  by  nets	 (wires).   Schematics	may  be	 printed  to a
         PostScript file for printing or further conversion to other output for-
         mats.
  
         gschem is also the symbol creation editor.  All the standard methods of
         creating schematics are used in the creation of symbols.	 There	are  a
         few  special  rules when creating symbols, so please refer to the (non-
         existant as of now) symbol creation document.
  
         Please read the official documentation (very minimal at this point)  on
         how  to use gschem, since this man page just describes the command line
         arguments and a few examples on how to run gschem.
  
  
  OPTIONS
         gschem accepts the following options:
  
         -q      Quiet mode on.  This mode  turns	 off  all  warnings/notes/mes-
  	       sages. (optional)
  
         -v      Verbose	mode on.  This mode gives as much feedback to the user
  	       as possible. (optional)
  
         -t      Print out more information when using mouse strokes.  With this
  	       command	line  flag  and the middle button configured for mouse
  	       strokes, gschem will output the stroke sequence numbers as  the
  	       user executes strokes.  These numbers can be used to define new
  	       strokes in the system-gschemrc file.
  
         -r filename
  	       Specify a rc filename.  Normally gschem searches for  the  sys-
  	       tem-gschemrc, then ~/.gEDA/gschemrc, and finally for a gschemrc
  	       in the current directory.  This	options	 allows	 the  user  to
  	       specify an additional rc file which is read after all the other
  	       rc files are read. (optional)
  
         -s filename
  	       Specify a guile script to be executed at startup. (optional)
  
         -o filename
  	       Specify a filename for postscript output.   This	 command  line
  	       argument	 is useful when running gschem from a shell script and
  	       with a guile script.  The filename can be changed  through  the
  	       print dialog box.
  
         -p      Automatically  place  the  window, especially useful if running
  	       gschem from the command line and generating output.
  
         schematic1 [... schematicN]
  	       Schematic file to be loaded.  Specifing	a  schematic  file  is
  	       optional.   If  multiple schematic files are specified they are
  	       read in sequentially and put on seperate pages.	It  is	impor-
  	       tant that the schematic(s) follow all the options (ie last).
  
  
  EXAMPLES
         These  examples	assume that you have a schematic called stack_1.sch in
         the current directory
  
         To run gschem and then interact with the program:
  
  	    ./gschem
  
         To run gschem in interactive mode but load a sample schematic:
  
  	    ./gschem adders_1.sch
  
         To run gschem and load up all schematics in the current subdirectory:
  
  	    ./gschem *.sch
  
  
  ENVIRONMENT
         No environment variables are used.
  
  
  AUTHOR
         Ales Hvezda and many others
  
  
  SEE ALSO
         gnetlist(1), gsymcheck(1)
  
  COPYRIGHT
         Copyright Â©  1999-2004 Ales Hvezda
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  
  Version			      December 31st, 2003		     gschem(1)</font></pre>
  </p>
  
  </div>
  <!-- SECTION [36700-41169] -->
  <h1><a name="electrical_connectivity" id="electrical_connectivity">Electrical Connectivity</a></h1>
  <div class="level1">
  
  <p>
  As you draw schematics you need be aware of what is considered to be electrically connected by the gEDA programs.<br/>
   Nets which are visually connected to other nets are electrically connected. This connection may be endpoint to endpoint or endpoint to midpoint. When a single endpoint to endpoint (net or pin endpoint) connection is drawn, the visual dangling net cue disappears. When an endpoint ends in the middle of another net (or multiple endpoints coming together at a single point) then a circular filled connectivity cue is drawn. You cannot connect a net to the middle of a pin. Nets can only be connected to the endpoints of pins. You cannot connect to a net if that net is not orthogonal (horizontal or vertical). The visual cues are the primary way of telling if nets/pins are connected.<br/>
   Bus are similar to nets with the exception that you cannot connect a net to the endpoint of a bus (only to the middle). If you do try to connect a net to the end of a bus you will see a big red X at the invalid endpoint connection. Buses are still very new so there are still many quirks.<br/>
   You can label nets by using the <code>label=</code> attribute. Do not attach more than one <code>label=</code> to a net. You only need to attach the <code>label=</code> attribute to one net segment. Different nets (i.e. multiple net segments which arenâ??t connected together) which have the same attribute <code>label=</code> attached to them are also considered electrically connected. You will not get any indication of this connection by <strong>gschem</strong>, but the netlister (<strong>gnetlist</strong>) considers nets with the same <code>label=</code> attribute electrically connected. The naming convention for buses has not been formalized yet.
  </p>
  
  </div>
  <!-- SECTION [41170-42886] -->
  <h1><a name="components_symbols_objects_attributes" id="components_symbols_objects_attributes">Components &amp; Symbols &amp; Objects &amp; Attributes</a></h1>
  <div class="level1">
  
  <p>
  There is a hierarchical association between components, symbols, objects, and attributes.
  </p>
  
  </div>
  <!-- SECTION [42887-43035] -->
  <h2><a name="components" id="components">Components</a></h2>
  <div class="level2">
  
  <p>
  A component is the instantiation of a specific symbol, as placed on the schematic. When discussing a schematic you refer to <em class="u">components</em> on the schematic, not <em class="u">symbols</em> on the schematic. Think of symbols as being <em class="u">conceptual</em>, and components as being <em class="u">concrete</em>.<br/>
   The component consists of a graphic representation and the attributes describing the component&rsquo;s features.<br/>
   The component inherits all of the attributes defined in the symbol. Certain attributes in the symbol:
  </p>
  <ul>
  <li class="level1"><div class="li"> those explicitly defined as visible unattached attributes (see <a href="#attributes" title="geda:gschem_ug &crarr;" class="wikilink1">Attributes</a>)</div>
  </li>
  <li class="level1"><div class="li"> specific attributes such as <code>symversion</code> and <code>refdes</code></div>
  </li>
  </ul>
  
  <p>
   are promoted to the component level for manipulation by the circuit designer. These attributes may optionally be exposed (made viewable) with the component&rsquo;s graphic, and their values may be changed.<br/>
   Any attribute not defined in the symbol may be defined in the component. For example, if the symbol does not define the <code>comment</code> attribute, this attribute may be added to the component, perhaps to add a comment for the Bill of Material or Assembly Instructions.<br/>
   Unfortunately, it is difficult to determine a component&rsquo;s attributes from <strong>gschem</strong> while entering the schematic. You have to place a symbol on the schematic, select the resulting component, and select <strong>Hierarchy | Down Symbol</strong> from the pull-down menus. Then, you have to unhide all attributes with <strong>Edit | Make Inv Text Vis</strong> from the pull-down menus. Then you have to expand your view of the symbol with <strong>View | Extents</strong>. Then, you have to go back to the schematic by selecting <strong>Hierarchy | Up</strong> from the pull-down menus. Then, you have to select <strong>Edit | Edit...</strong> to bring up the &ldquo;Edit Attributes&rdquo; dialog box to determine if any attributes have been added at the component level.
  </p>
  
  </div>
  <!-- SECTION [43036-44850] -->
  <h2><a name="symbols" id="symbols">Symbols</a></h2>
  <div class="level2">
  
  <p>
  Symbols are just a collection of objects and attributes.<br/>
   The objects have positional significance in the symbol, and define the graphic that is viewed.<br/>
   Attributes may be attached to objects, or they may be attached to the symbol itself (termed as &ldquo;unattached&rdquo; attributes, because they are not attached to an object).
  </p>
  
  </div>
  <!-- SECTION [44851-45192] -->
  <h2><a name="objects" id="objects">Objects</a></h2>
  <div class="level2">
  
  <p>
  The following are objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Line</div>
  </li>
  <li class="level1"><div class="li"> Box</div>
  </li>
  <li class="level1"><div class="li"> Circle</div>
  </li>
  <li class="level1"><div class="li"> Arc</div>
  </li>
  <li class="level1"><div class="li"> Pin</div>
  </li>
  <li class="level1"><div class="li"> Picture</div>
  </li>
  <li class="level1"><div class="li"> Text</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [45193-45305] -->
  <h2><a name="attributes" id="attributes">Attributes</a></h2>
  <div class="level2">
  
  <p>
  An attribute is text which is in the form <code>name=value</code> (there are no spaces to the left or right of the name,value pair). An attribute can be either attached to an object or unattached. Attributes are used extensively in the gEDA project to convey information (e.g., device name, pin numbers, hidden nets, and unit reference numbers). Check <a href="http://www.geda.seul.org/docs/current/attributes/index.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/attributes/index.html";  rel="nofollow">gEDA/gaf Master Attribute Document</a> for a complete list of attributes.<br/>
   There are three kinds of attributes:</p>
  <dl>
  <dt><span class='term'> Attached attributes</span></dt>
  <dd>These are attributes which take on the standard form and are attached to some object (pin, net, component, or box etc...) to associate a value with the attribute. For example: a pin number associated with a pin. <span class="hilited">These attributes are usually yellow in color.</span></dd>
  <dt><span class='term'> Unattached attributes</span></dt>
  <dd>These are attributes which take on the standard form, but are not attached to any object and usually convey some information which is global in nature. For example: a <code>device=</code> attribute (which lives inside symbols) and specifies what device the entire symbol represents. These attributes are also known as floating or toplevel attributes.</dd>
  <dt><span class='term'> Promoted attributes</span></dt>
  <dd>These are unattached attributes in the symbol&rsquo;s definition that get turned into attached attributes in the component&rsquo;s definition when the symbol is instantiated as a component when placed in the schematic. If you place an unattached visible attribute inside a symbol and then instantiate that symbol, then that unattached attribute gets &ldquo;promoted&rdquo;; that is, it becomes an attached attribute. This mechanism of attribute reattachement (from within a symbol) is known as attribute promotion.</dd>
  </dl>
  <p>There are some gotchas about attribute promotion:
  </p>
  <ul>
  <li class="level1"><div class="li"> Promotion <strong>only</strong> happens when the symbol is first placed. That means that if you place a symbol (e.g., sym1) and then change it on disk (by adding or removing new unattached attributes), existing sym1&rsquo;s will not reflect these new unattached attributes (i.e., they won&rsquo;t get promoted) in any schematic.</div>
  </li>
  <li class="level1"><div class="li"> The <code>device=</code> attribute is not promoted.</div>
  </li>
  <li class="level1"><div class="li"> Invisible attributes are not promoted by default. If you add an unattached attribute (e.g., numslots=#) and make it invisible, it will not be promoted.</div>
  </li>
  </ul>
  
  <p>
   Now, in order to make everybody happy, this attribute promotion behavior is configurable.<br/>
   The system-gschemrc file defines: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(attribute-promotion &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  which enables attribute promotion.<br/>
   If you override the system-gschemrc&rsquo;s default promote-invisible setting by adding: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(promote-invisible &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  to either your user&rsquo;s ~/gschemrc or local &lsquo;pwd&rsquo;/gschemrc file, invisible unattached attributes will also be promoted <span class="hilited">(and in memory removed)</span>.
  </p>
  
  <p>
  However, if you do this, component slotting will break because <strong>gschem</strong> expects certain unattached attributes inside the symbol <span class="hilited">(in memory even though they are invisible)</span>.<br/>
   So you can add: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(keep-invisible &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  to either your user&rsquo;s ~/gschemrc or local &lsquo;pwd&rsquo;/gschemrc file. This is enabled by default, but has no effect unless promote-invisible is enabled.
  </p>
  
  <p>
  So, to summarize, attribute promotion takes unattached attributes inside symbols and attaches them to the outside of a placed symbol. Three *rc keywords control this behavior: attribute-promotion, promote-invisible, and keep-invisible.
  </p>
  
  </div>
  <!-- SECTION [45306-48692] -->
  <h1><a name="the_main_window" id="the_main_window">The Main Window</a></h1>
  <div class="level1">
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_gschem_screenshot_001.html" class="media" title="geda:gschem_screenshot_001.jpg"><img src="_media/geda_gschem_screenshot_001.jpg" class="media" title="gschem_screenshot_001.jpg" alt="gschem_screenshot_001.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  <p>
   There are several ways to interact with <strong>gschem</strong>. <strong>gschem</strong> requires a keyboard and mouse. There are three ways to initiate an operation or command:
  </p>
  <ul>
  <li class="level1"><div class="li"> Using the mouse to select the operation off a menu</div>
  </li>
  <li class="level1"><div class="li"> Typing the keyboard shortcut(s).</div>
  </li>
  <li class="level1"><div class="li"> Draw the appropriate stroke (if stroke support is enabled)</div>
  </li>
  </ul>
  
  <p>
   To make usage matters more confusing, selecting an operation off of the menus behaves slightly differently than typing the keyboard shortcut. Most of the operations operate on the currently selected object(s), hence you need to select the object first before manipulating them. The menu selected operations usually require some more input (usually a mouse click) after they are picked off of the menu. The keyboard shortcut operations take that required input as the current mouse position. This saves an extra click since you can position the mouse at the right place, type in the shortcut(s), and the command then executes. Note, you can change this so that both menu and shortcut behavior is exactly the same. See the section on the resource file for more info on how to configure this.<br/>
   Most of the interaction with <strong>gschem</strong> is fairly mode oriented (similar to the great text editor vi). If you select operations off of the menu, then you are placed into the corresponding mode (like copy or move mode). You must then select an anchor point (or whatever the appropriate point is) to continue the operation. Most of the commands off of the menu expect the objects to be already selected. Some of the modes persist after being execute while other immediately return you into select mode (the default mode).<br/>
   The shortcuts are also mode like in nature. Most of the default shortcuts are for the various commands are not single keystrokes. There are a few which are single keystrokes (like zoom in: `z&rsquo; or pan: `x&rsquo;), but most are typically two keystrokes long. As examples, to execute File/Save you would type `f&rsquo; and `s&rsquo; (without the quotes) or Add/Line is `a&rsquo; and `l&rsquo;. You can get a listing of the shortcuts by picking Help/Hotkeys. You can also see the hotkey assignments in the pulldown menus as well. The shortcuts are defined in the resource files (<strong>system-gschemrc</strong>, <strong>/.gEDA/gschemrc</strong>, or <strong>`pwd`/gschemrc</strong>). See the section on the resource file for more info.<br/>
   The mouse button actions in <strong>gschem</strong> are mostly configurable. The first mouse button is always used to select objects or pick points. This button is not configurable. The second mouse button is either a copy/move action (when held down over an object), a repeat last command or used to draw a stroke to execute a command. The third mouse button is either a mouse pan (when held down as the mouse is moved) or a popup menu. The behavior of the second and third mouse buttons is controlled through the resource file (see the section below for more info).
  </p>
  
  </div>
  <!-- SECTION [48693-51606] -->
  <h1><a name="the_status_window" id="the_status_window">The Status Window</a></h1>
  <div class="level1">
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_status_screenshot.html" class="media" title="geda:status_screenshot.jpg"><img src="_media/geda_status_screenshot.jpg" class="media" title=":geda:status_screenshot.jpg" alt=":geda:status_screenshot.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  <p>
   Add some details about what gets displayed in the status window.
  </p>
  
  </div>
  <!-- SECTION [51607-51769] -->
  <h1><a name="the_schematic_file" id="the_schematic_file">The Schematic File</a></h1>
  <div class="level1">
  
  <p>
  Schematic files. These files contain components, nets, text, and sometimes primitive objects (like lines, circles, box etc...) Schematics do not contain pins. Schematic filenames should follow this convention: name_#.sch where:
  </p>
  <ul>
  <li class="level1"><div class="li"> name is a text string which describes what this schematic contains.</div>
  </li>
  <li class="level1"><div class="li"> _# is an underscore and a number (like _1, _2, _7, _13, etc...) This number is used to sequence schematic pages in a multiple page schematic.</div>
  </li>
  <li class="level1"><div class="li"> .sch is the schematic extension/suffix. It is important the schematic pages have this extension.</div>
  </li>
  </ul>
  
  <p>
   Schematic files are pure <acronym title="American Standard Code for Information Interchange">ASCII</acronym> and will always be pure <acronym title="American Standard Code for Information Interchange">ASCII</acronym>. gEDA does not support any binary file formats. The file format for schematics is described in the gEDA file formats document.
  </p>
  
  </div>
  <!-- SECTION [51770-52539] -->
  <h1><a name="the_symbol_file" id="the_symbol_file">The Symbol File</a></h1>
  <div class="level1">
  
  <p>
  Symbol files. The schematic and symbol file formats are identical. <strong>gschem</strong> (or a text editor) is used to create symbol files as well as schematics. Symbol files contain lines, circles, boxes, arcs, pins, text, and attributes.<br/>
   The naming convention for symbol files is: name-#.sym where:
  </p>
  <ul>
  <li class="level1"><div class="li"> name is a text string which describes what the symbol represents.</div>
  </li>
  <li class="level1"><div class="li"> -# is a dash and a number (like -1, -2 etc...) The number is used to allow for a symbols to have the same name yet different contents. There might be multiple representations for resistors so these symbols should be called: resistor-1.sym, resistor-2.sym, and resistor-3.sym.</div>
  </li>
  <li class="level1"><div class="li"> .sym is the symbol extension/suffix. It is important the symbols have this extension.</div>
  </li>
  </ul>
  
  <p>
   The way of specifying hierarchy is by using the source= attribute. Please see the master attribute document for info on this mechanism.<br/>
   The hierarchy mechanism is still in heavy flux, so there might be some more changes.
  </p>
  
  </div>
  <!-- SECTION [52540-53526] -->
  <h1><a name="symbol_libraries" id="symbol_libraries">Symbol Libraries</a></h1>
  <div class="level1">
  
  <p>
  Components are searched for by specifying (component-library &ldquo;...&rdquo;) inside one of the *rc files. See below for more info.
  </p>
  
  </div>
  <!-- SECTION [53527-53680] -->
  <h1><a name="the_log_file" id="the_log_file">The Log File</a></h1>
  <div class="level1">
  
  <p>
  Log file. This file contains informative, error, warnings etc... messages when <strong>gschem</strong> was run. This file is created in the working directory that <strong>gschem</strong> was started in. This allows the user to preserve log files between independent projects.
  </p>
  
  </div>
  <!-- SECTION [53681-53958] -->
  <h1><a name="grips" id="grips">Grips</a></h1>
  <div class="level1">
  
  <p>
  Grips are a mechanism used in <strong>gschem</strong> to provide an easy way of modifying objects inside schematics. When you select an object, little squares are placed in strategic locations (line end points or circle radius point or corners of a box) which allow you to change the object quickly. Grip support currently exists for lines, nets, pins, buses, circles, and boxes. Arcs do not yet have grips, but will eventually have them.
  </p>
  
  <p>
  Using grips is easy:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the object you want to change. The grips (the little boxes) will appear.</div>
  </li>
  <li class="level1"><div class="li"> Click and hold the first mouse button inside the box.</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse around till you have the object where you want it</div>
  </li>
  <li class="level1"><div class="li"> Release the mouse button.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [53959-54668] -->
  <h1><a name="menu_operations" id="menu_operations">Menu Operations</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [54669-54698] -->
  <h2><a name="file" id="file">File</a></h2>
  <div class="level2">
  
  <p>
  The <strong>gschem</strong> application is primarily used for the creation of schematic files (i.e., filename.sch) and symbol files (filename.sym).<br/>
   The following operations are related to the manipulation of these files.<br/>
   Note that <strong>gschem</strong> automatically maintains backups of open schematic/symbol files, in the /tmp directory, for the purpose of Undo/Redo. <strong>gschem</strong> cleans up these files when it exits gracefully. If <strong>gschem</strong> does not exit gracefully, the next time you launch <strong>gschem</strong> you will be prompted with a dialog similar to: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">WARNING: Found an autosave backup file:
          {filename}
  
        The backup copy is newer than the schematic, so it seems you
        load it instead of the original file.
        gschem usually makes backup copies automatically, and this
        situation happens when it crashed or it was forced to exit
        abruptly.
  
        If you load the original file, the backup file will be overwritten in
        the next autosave timeout and it will be lost.
  
        Do you want to load the backup file?</font></pre>
  </p>
  
  <p>
  The following are available from the <strong>gschem</strong> main window&rsquo;s menu-bar when you expand <strong>File</strong>:
  </p>
  
  </div>
  <!-- SECTION [54699-55852] -->
  <h3><a name="new_window_fw" id="new_window_fw">New Window (fw)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | New Window</strong> opens a new window, in addition to any already open windows. Each window is totally separate from the other windows.
  </p>
  
  </div>
  <!-- SECTION [55853-56018] -->
  <h3><a name="new_page_fn" id="new_page_fn">New Page (fn)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | New Page</strong> opens a new page, in addition to any existing open pages. Usually this page will be named &ldquo;untitled_N.sch&rdquo;, where N is an incrementing number.
  </p>
  
  </div>
  <!-- SECTION [56019-56206] -->
  <h3><a name="open_page..._fo" id="open_page..._fo">Open Page... (fo)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Open Page...</strong> opens an existing page from disk.<br/>
   The &ldquo;Open...&rdquo; dialog box pops up providing:
  </p>
  <ul>
  <li class="level1"><div class="li"> Directory navigation aids</div>
  </li>
  <li class="level1"><div class="li"> Filters for restricting the displayed files:</div>
  <ul>
  <li class="level2"><div class="li"> Schematics</div>
  </li>
  <li class="level2"><div class="li"> Symbols</div>
  </li>
  <li class="level2"><div class="li"> Schematics and Symbols</div>
  </li>
  <li class="level2"><div class="li"> All files</div>
  </li>
  </ul>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [56207-56494] -->
  <h3><a name="close_page_pc" id="close_page_pc">Close Page (pc)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Close Page</strong> closes the currently displayed page. This will prompt you to save if you have modified the page.
  </p>
  
  </div>
  <!-- SECTION [56495-56640] -->
  <h3><a name="revert_page_pr" id="revert_page_pr">Revert Page (pr)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Revert Page</strong> closes and reopens the currently displayed page. This will not prompt you to save the current page, but will quickly discard any changes you have made and reopen the saved schematic from disk. Use with caution.
  </p>
  
  </div>
  <!-- SECTION [56641-56902] -->
  <h3><a name="save_page_fs" id="save_page_fs">Save Page (fs)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Save Page</strong> saves the current page. The current filename is displayed in the <strong>gschem</strong> status-bar.<br/>
   If the page&rsquo;s filename is &ldquo;untitled_N.sch&rdquo; (where N is a integer), then the Save As... dialog box will be displayed, prompting for a new filename.<br/>
   If the page&rsquo;s filename is NOT &ldquo;untitled_N.sch&rdquo; (where N is a integer), then the Save As... dialog box will NOT be displayed, and:
  </p>
  <ul>
  <li class="level1"><div class="li"> the backup file will be created for the previous version, named {filename}~ That is, the &ldquo;~&rdquo; (tilde character) is appended to the filename. Any previous backup file is lost.</div>
  </li>
  <li class="level1"><div class="li"> the file will be saved to the current filename.<br/>
  </div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [56903-57550] -->
  <h3><a name="save_page_as..._fa" id="save_page_as..._fa">Save Page As... (fa)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Save Page As...</strong> opens the Save As.. dialog box.<br/>
   If the current filename is &ldquo;untitled_N.sch&rdquo;, the Save As... dialog box prompts for a new filename.<br/>
   If the current filename is NOT &ldquo;untitled_N.sch&rdquo;, the Save As... dialog box prompts for a new filename, filling in the current filename as a default.<br/>
   In either case the filename may be changed, and a new file created when the Save As button is clicked.
  </p>
  
  </div>
  <!-- SECTION [57551-57998] -->
  <h3><a name="save_all_fl_fl" id="save_all_fl_fl">Save All (fl) (fl)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Save All</strong> unconditionally saves all schematics loaded in memory.
  </p>
  
  </div>
  <!-- SECTION [57999-58103] -->
  <h3><a name="print..._fp" id="print..._fp">Print... (fp)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Print...</strong> brings up the Print... dialog box.<br/>
   The following may be selected:
  </p>
  <ul>
  <li class="level1"><div class="li"> Filename (if <strong>gschem</strong> has multiple pages loaded, this filename defaults to the page currently displayed).</div>
  </li>
  <li class="level1"><div class="li"> Paper size (that is loaded into your printer).</div>
  </li>
  <li class="level1"><div class="li"> The print type:</div>
  <ul>
  <li class="level2"><div class="li"> Extents with margins &ndash; the current page, with margins where the printer doesn&rsquo;t output.</div>
  </li>
  <li class="level2"><div class="li"> Extents no margins &ndash; the current page, but without margins where the printer doesn&rsquo;t output. The printer output may be scaled larger than when using &ldquo;Entents with margins&rdquo;, but at the loss along the borders of the schematic.</div>
  </li>
  <li class="level2"><div class="li"> Current window &ndash; Scaled to fit the page size, but not optimally.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Orientation:</div>
  <ul>
  <li class="level2"><div class="li"> Landscape</div>
  </li>
  <li class="level2"><div class="li"> Portrait</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Pressing Print will generate a PostScript file with the filname format of the form {filename}.ps (e.g., printing schematic file First_1.sch would generate First_1.ps).<br/>
   Printing the PostScript file to your printer is distribution dependent:</p>
  <dl>
  <dt><span class='term'> Fedora Core (from the command-line):</span></dt>
  <dd><code>lp First_1.ps</code></dd>
  </dl>
  <p>
  </p>
  
  </div>
  <!-- SECTION [58104-59150] -->
  <h3><a name="write_png..._fi" id="write_png..._fi">Write PNG... (fi)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Write <acronym title="Portable Network Graphics">PNG</acronym>...</strong> brings up the Write <acronym title="Portable Network Graphics">PNG</acronym>... dialog box. Note you must have libgdgeda installed (and any required dependencies) if you want to output images.<br/>
   The dialog box allows you to select:
  </p>
  <ul>
  <li class="level1"><div class="li"> Width x Height:</div>
  <ul>
  <li class="level2"><div class="li"> 320 x 240</div>
  </li>
  <li class="level2"><div class="li"> 640 x 480</div>
  </li>
  <li class="level2"><div class="li"> 800 x 600</div>
  </li>
  <li class="level2"><div class="li"> 1024 x 768</div>
  </li>
  <li class="level2"><div class="li"> 1280 x 960</div>
  </li>
  <li class="level2"><div class="li"> 1600 x 1200</div>
  </li>
  <li class="level2"><div class="li"> 3200 x 2400</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Filename (if <strong>gschem</strong> has multiple pages loaded, the currently displayed page&rsquo;s filname is given)</div>
  </li>
  </ul>
  
  <p>
   When the OK button is clicked, a <acronym title="Portable Network Graphics">PNG</acronym> graphic file with a filename of the form {filename}.png is created (e.g., writing a <acronym title="Portable Network Graphics">PNG</acronym> for schematic file First_1.sch will generate a First_1.png file).<br/>
   This file may be used any way a <acronym title="Portable Network Graphics">PNG</acronym> file is used (e.g., web-page, document insertion, image manipulation with the GIMP, etc.).
  </p>
  
  </div>
  <!-- SECTION [59151-59945] -->
  <h3><a name="execute_script..._ft" id="execute_script..._ft">Execute Script... (ft)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Execute Script...</strong> .....TBD
  </p>
  
  </div>
  <!-- SECTION [59946-60017] -->
  <h3><a name="close_window_fc" id="close_window_fc">Close Window (fc)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Close Window</strong> closes the current window. If there are any modified schematics, the â??There are unsaved schematicsâ?? dialog box will appear. Clicking OK will cause all unsaved schematics to be lost.
  </p>
  
  </div>
  <!-- SECTION [60018-60256] -->
  <h3><a name="quit_alt-q" id="quit_alt-q">Quit (Alt-q)</a></h3>
  <div class="level3">
  
  <p>
  <strong>File | Quit</strong> closes all opened windows and exits <strong>gschem</strong>. A â??There are unsaved schematicsâ?? dialog box will appear for each window that has unsaved schematics.
  </p>
  
  </div>
  <!-- SECTION [60257-60449] -->
  <h2><a name="edit" id="edit">Edit</a></h2>
  <div class="level2">
  
  <p>
  The following are available from the <strong>gschem</strong> main windowâ??s menu-bar when you expand <strong>Edit</strong>:
  </p>
  
  </div>
  <!-- SECTION [60450-60566] -->
  <h3><a name="undo_shift-u" id="undo_shift-u">Undo (shift-u)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Undo</strong> does exactly that, it undos the last action which changed the schematic.<br/>
   The depth of undo (how many undo steps can be performed) is set in the system-gschemrc file. The default is 10. Simply override this setting by placing the following lines in either your ~/.gEDA/gschemrc file or your local gschemrc file: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">; undo-levels number
  ;
  ; Determines the number of levels of undo.  Basically this number decides 
  ; how many backup schematics are saved on disk.
  ;
  (undo-levels 10)</font></pre>
  </p>
  
  <p>
  After every action (including zooming and panning) the schematic is saved to disk (in /tmp). The undo-levels setting determines how many of these temporary files are maintained in the /tmp directory. <strong>gschem</strong> does clean-up after itself when you exit.<br/>
   Should <strong>gschem</strong> crash, the saved files remain in /tmp for disaster recovery. You will be prompted the next time the schematic is opened to recover from the backup.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [60567-61525] -->
  <h3><a name="redo_shift-r" id="redo_shift-r">Redo (shift-r)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Redo</strong> only applies after you have done an <strong>Edit | Undo</strong>. You can undo something and then immediately redo it. However if you do anything in between you will lose the undo info. You can undo and redo to your hearts desire up and down till you reach the max undo levels.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [61526-61834] -->
  <h3><a name="select_mode_s" id="select_mode_s">Select Mode (s)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Select Mode</strong> is the initial mode in which <strong>gschem</strong> starts.<br/>
   When in <strong>Select Mode</strong>, an unlocked object (i.e., component, line, box, circle, ...) may be selected by placing the mouse pointer within the outline of the object and single-clicking, or by dragging a box (i.e., holding down the first mouse-button) around the object. Selecting an already selected object will leave the object selected (i.e., you can not unselect an object by single-clicking it). Multiple unlocked objects may be selected by dragging a box around the objects.<br/>
   A locked object may be selected by dragging a box around the object.<br/>
   To de-select all objects, single-click anywhere on the schematic where there is no object.<br/>
   A visible attribute for an unlocked component may be selected by placing the mouse pointer over the component&rsquo;s visible attribute and single-clicking. Placing the mouse pointer over the unlocked component&rsquo;s visible attribute and double-clicking will open the edit dialog box appropriate for the attribute.<br/>
   Objects will change color when selected.<br/>
   You stay in <strong>Select Mode</strong> until you select one of the other Modes (e.g., Line, Copy, Move, etc.).<br/>
   Your current Mode is displayed on the status-bar, in the lower-right corner of the <strong>gschem</strong> window.<br/>
   If multiple objects overlap, single-clicking where they overlap will cycle through the objects.<br/>
   If you hold down the SHIFT key and single-click, you can select and deselect multiple objects. Doing this with multiple overlapping objects will cause the selection to cycle among the possible object selections.<br/>
   If you hold down the CONTROL key and single-click, you will toggle the object in and out of the current selection list.<br/>
   If you hold down the SHIFT key while drawing a selection box you will add to the currently selected objects. Objects cannot be removed using the selection box and holding down the SHIFT key.<br/>
   If you hold down the CONTROL key while drawing a selection box then you will toggle any encompassed objects. If an object was selected then it will be unselected and vice versa.<br/>
   If you pick a component, its visible and invisible attributes are selected as well. If you just want to select the object, you must deselect the attributes.<br/>
   The selection mechanisms are not obvious and do require some practice. There are some quirks so please report them as you come across them.
  </p>
  
  </div>
  <!-- SECTION [61835-64242] -->
  <h3><a name="edit..._ee" id="edit..._ee">Edit... (ee)</a></h3>
  <div class="level3">
  
  <p>
  First, select the object to be edited (i.e., in <strong>Select Mode</strong>).<br/>
   If the object is a component, <strong>Edit | Edit...</strong> then pops up a dialog box that allows you to edit the component&rsquo;s attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> Existing attributes (e.g., refdes) are displayed.</div>
  </li>
  <li class="level1"><div class="li"> A drop-down list of pre-defined attributes permits selection, and a edit-box provides association of a value to the attribute.</div>
  </li>
  <li class="level1"><div class="li"> The attribute&rsquo; name and/or value may be made visible or invisible,</div>
  </li>
  </ul>
  
  <p>
   If the ojbect is a text string, <strong>Edit...</strong> then pops up a dialog box that allows you to modify the text string&rsquo;s attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> The text string may be modified. Multiple lines of text may be entered by inserting carriage-returns.</div>
  </li>
  <li class="level1"><div class="li"> The text color may be modified.</div>
  </li>
  <li class="level1"><div class="li"> The text size may be modified.</div>
  </li>
  <li class="level1"><div class="li"> The text alignment:</div>
  <ul>
  <li class="level2"><div class="li"> Lower/middle/upper left</div>
  </li>
  <li class="level2"><div class="li"> Lower/middle/upper middle</div>
  </li>
  <li class="level2"><div class="li"> Lower/middle/upper right</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Apply the changes by pressing OK.
  </p>
  
  <p>
  <strong>Notes:</strong><br/>
   If you need to change the attributes to more than just a few components, consider saving your schematics, closing <strong>gschem</strong>, and using the <strong>gattrib</strong> application, the <strong>grenum</strong> application, or the <strong>refdes_renum</strong> application to make the changes.
  </p>
  
  </div>
  <!-- SECTION [64243-65437] -->
  <h3><a name="edit_text..._ex" id="edit_text..._ex">Edit Text... (ex)</a></h3>
  <div class="level3">
  
  <p>
  First, select the text object to be edited (i.e., in <strong>Select Mode</strong>).<br/>
   <strong>Edit | Edit Text...</strong> allows you to edit just text.<br/>
   <strong>Edit | Edit Text...</strong> then pops up a dialog box that allows you to modify the text string&rsquo;s attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> The text string may be modified. Multiple lines of text may be entered by inserting carriage-returns.</div>
  </li>
  <li class="level1"><div class="li"> The text color may be modified.</div>
  </li>
  <li class="level1"><div class="li"> The text size may be modified.</div>
  </li>
  <li class="level1"><div class="li"> The text alignment:</div>
  <ul>
  <li class="level2"><div class="li"> Lower/middle/upper left</div>
  </li>
  <li class="level2"><div class="li"> Lower/middle/upper middle</div>
  </li>
  <li class="level2"><div class="li"> Lower/middle/upper right</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Apply the changes by pressing OK.
  </p>
  
  <p>
  <strong>Notes:</strong><br/>
   If you need to change the attributes to more than just a few text strings, consider saving your schematics, closing <strong>gschem</strong>, and using the <strong>gattrib</strong> application, the <strong>grenum</strong> application, or the <strong>refdes_renum</strong> application to make the changes.
  </p>
  
  </div>
  <!-- SECTION [65438-66296] -->
  <h3><a name="copy_mode_ec" id="copy_mode_ec">Copy Mode (ec)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Copy Mode</strong> allows you to copy (i.e., duplicate) the currently selected objects.<br/>
   To copy the object(s):
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the objects to be copied (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Copy Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Observe the status-bar now indicates <strong>Copy Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Click on the selected component(s) to establish an origin of reference</div>
  </li>
  <li class="level1"><div class="li"> Observe a shadow/outline appears for the selected components that moves with the mouse</div>
  </li>
  <li class="level1"><div class="li"> Place the components where you want them</div>
  </li>
  <li class="level1"><div class="li"> Click to anchor the copied components in place.</div>
  </li>
  </ul>
  
  <p>
   After finishing the copy, you automatically return to <strong>Select Mode</strong>.<br/>
   Holding down the CONTROL key as you move the outline around will constrain the movement to be either horizontal or vertical.<br/>
   To copy objects using the shortcut keys is almost the same as above except that the origin point is selected automatically for you once you hit the copy mode shortcut.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [66297-67221] -->
  <h3><a name="move_mode_em" id="move_mode_em">Move Mode (em)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Move Mode</strong> allows you to move the currently selected objects.<br/>
   To move the object(s):
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the objects to be moved (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Move Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Observe the status-bar now indicates <strong>Move Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Click on the selected component(s) to establish an origin of reference</div>
  </li>
  <li class="level1"><div class="li"> Observe a shadow/outline appears for the selected components that moves with the mouse</div>
  </li>
  <li class="level1"><div class="li"> Place the components where you want them</div>
  </li>
  <li class="level1"><div class="li"> Click to anchor the moved components in place.</div>
  </li>
  </ul>
  
  <p>
   After finishing the move, you automatically return to <strong>Select Mode</strong>.<br/>
   Holding down the CONTROL key as you move the outline around will constrain the movement to be either horizontal or vertical.<br/>
   To move objects using the shortcut keys is almost the same as above except that the origin point is selected automatically for you once you hit the copy mode shortcut.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [67222-68126] -->
  <h3><a name="delete_delete-key" id="delete_delete-key">Delete (Delete-key)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Delete</strong> allows you to remove objects off of the page.<br/>
   To delete objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Delete</strong></div>
  </li>
  </ul>
  
  <p>
   The object(s) will be deleted immediately. If you inadvertantly delete a component, you can use Undo to recover.
  </p>
  
  </div>
  <!-- SECTION [68127-68445] -->
  <h3><a name="rotate_90_mode_er" id="rotate_90_mode_er">Rotate 90 Mode (er)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Rotate 90 Mode</strong> allows you to rotate objects 90 degrees around a pivot/center point.<br/>
   To rotate objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Rotate 90 Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Click on the pivot (or center) point of the rotate</div>
  </li>
  </ul>
  
  <p>
   The object(s) will be rotated 90Âº counter-clockwise immediately. If you inadvertantly rotate a component, you can use Undo to recover.<br/>
   Rotating objects using the shortcut keys is similar to above except that the center point is the last mouse position at which you typed the shortcut.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [68446-69035] -->
  <h3><a name="mirror_mode_ei" id="mirror_mode_ei">Mirror Mode (ei)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Mirror Mode</strong> allows you to mirror objects horizontally around a pivot point.<br/>
   To mirror objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Mirror Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Click on the pivot (or center) point of the mirror</div>
  </li>
  </ul>
  
  <p>
   Mirroring objects using the shortcut keys is similar to above except that the pivot point is the last mouse position at which you typed the shortcut.<br/>
   Objects are mirrored horizontally about the pivot point. If you want to get a vertical mirror then rotate and mirror the object(s) till you get the desired position.<br/>
   Mirroring of embedded components is not supported.
  </p>
  
  </div>
  <!-- SECTION [69036-69692] -->
  <h3><a name="slot..._e_shift-s" id="slot..._e_shift-s">Slot... (e shift-s)</a></h3>
  <div class="level3">
  
  <p>
  Some physical packages (e.g., the classic 7400 Quad NAND gate) contain more than one logical component (e.g., one of the NAND gates). In <strong>gchem</strong> terminology, each of these logical components is termed a &ldquo;slot&rdquo; (e.g., there would be 4 slots in the 7400 Quad NAND gate). Each slot is associated with specific pins on the physical package.<br/>
   <strong>Edit | Slot...</strong> allows you to change the slot number of a multiple-slot package. The package must support slotting. Refer to the <a href="http://www.geda.seul.org/docs/current/symbols/index.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/symbols/index.html";  rel="nofollow">gEDA/gaf Symbol Creation Document</a> for more details.<br/>
   To change the slot number (i.e., select which package pins are associated with a logical component):
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired logical component (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Slot...</strong></div>
  </li>
  <li class="level1"><div class="li"> Change the &ldquo;slot=n&rdquo; value in the &ldquo;Edit slot number&rdquo; dialog box</div>
  </li>
  <li class="level1"><div class="li"> Press OK</div>
  </li>
  </ul>
  
  <p>
   Note that selecting the slot on a package often effects the layout of the printed circuit board, as the slot may be on the wrong side of the package for effecient routing of nets. Don&rsquo;t worry, you can always come back and change the slot selection once you start laying out your board and know which slots route best.
  </p>
  
  </div>
  <!-- SECTION [69693-70909] -->
  <h3><a name="color..._eo" id="color..._eo">Color... (eo)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Color...</strong> allows you to change the color of any selected object (with the exception of components).<br/>
   To change the color of the currently selected objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Color...</strong></div>
  </li>
  <li class="level1"><div class="li"> The &ldquo;Edit | Color Edit&rdquo; dialog box, with a drop down list for colors, will appear:</div>
  <ul>
  <li class="level2"><div class="li"> 1 | pin | black</div>
  </li>
  <li class="level2"><div class="li"> 2 | net endpoint | red</div>
  </li>
  <li class="level2"><div class="li"> 3 | graphic | green4</div>
  </li>
  <li class="level2"><div class="li"> 4 | net | blue2</div>
  </li>
  <li class="level2"><div class="li"> 5 | attribute | black</div>
  </li>
  <li class="level2"><div class="li"> 6 | logic bubble | DarkCyan</div>
  </li>
  <li class="level2"><div class="li"> 8 | detached attribute | red</div>
  </li>
  <li class="level2"><div class="li"> 9 | text | green4</div>
  </li>
  <li class="level2"><div class="li"> 10 | bus | green2</div>
  </li>
  <li class="level2"><div class="li"> 11 | select | firebrick</div>
  </li>
  <li class="level2"><div class="li"> 12 | bounding box | orange</div>
  </li>
  <li class="level2"><div class="li"> 13 | zoom box | DarkCyan</div>
  </li>
  <li class="level2"><div class="li"> 14 | stroke | grey90</div>
  </li>
  <li class="level2"><div class="li"> 15 | lock | grey40</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Pick the new color</div>
  </li>
  <li class="level1"><div class="li"> Press Apply</div>
  </li>
  </ul>
  
  <p>
   The color change will take effect once you press Apply.<br/>
   You can leave this dialog box up and select other objects and change their color by pressing Apply.
  </p>
  
  </div>
  <!-- SECTION [70910-71868] -->
  <h3><a name="lock_el_unlock_e_shift-l" id="lock_el_unlock_e_shift-l">Lock (el) / Unlock (e shift-l)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Lock</strong> and <strong>Edit | Unlock</strong> allow you to lock/unlock components in a schematic. A locked component cannot be selected by a single click. To select locked component(s), drag a box around the component(s).<br/>
   Locking a component is useful for components such as title blocks, which should not be selectable because there are other objects inside its boundaries. If the titleblock was not locked, and you missed selecting a component by clicking it with the mouse, you would end up selecting the titleblock instead.<br/>
   Locking a component is also useful just to prevent it from being inadvertantly selected.<br/>
   To lock/unlock components:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Lock</strong> or <strong>Edit | Unlock</strong></div>
  </li>
  </ul>
  
  <p>
   The locked/unlocked state of components is preserved when <strong>gschem</strong> exits, so components which were locked remain locked the next time the schematic is opened.<br/>
   You can lock and unlock regular objects (e.g., lines, pins, boxes...). This is nice when you are drawing something and an object is in the way. Just lock it, and you will not have to think about it when you click to select other objects. Locking an object is not preserved in the file format, so once you quit <strong>gschem</strong> any locked objects will be unlocked the next time the schematic is opened.<br/>
   Note that if a component is locked, you can not single-click to select a visible attribute, or double-click to select and edit a visible component. First unlock such locked components.
  </p>
  
  </div>
  <!-- SECTION [71869-73407] -->
  <h3><a name="line_width_type..._ew" id="line_width_type..._ew">Line Width &amp; Type... (ew)</a></h3>
  <div class="level3">
  
  <p>
  The <strong>Edit | Line Width &amp; Type...</strong> dialog box lets you control the width and type of lines, boxes, circles, and arcs on the schematic/symbol.<br/>
   To change the <strong>Line Width &amp; Type...</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the desired object(s) (i.e., in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Line Width &amp; Type...</strong></div>
  </li>
  <li class="level1"><div class="li"> The &ldquo;Edit Line Width * Type&rdquo; dialog box displays</div>
  </li>
  <li class="level1"><div class="li"> Change the following as suites the object:</div>
  <ul>
  <li class="level2"><div class="li"> Line Width</div>
  </li>
  <li class="level2"><div class="li"> Line Type</div>
  </li>
  <li class="level2"><div class="li"> Line Dash Length</div>
  </li>
  <li class="level2"><div class="li"> Line Dash Space</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Press OK to apply the changes</div>
  </li>
  </ul>
  
  <p>
   Note that if the line width doesn&rsquo;t seem to change, just pick a larger value.
  </p>
  
  </div>
  <!-- SECTION [73408-74023] -->
  <h3><a name="fill_type..._ef" id="fill_type..._ef">Fill Type... (ef)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Fill Type...</strong> is used to fill boxes and circles.<br/>
   To fill a box or circle:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the box or circle.</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Fill Type...</strong>. The &ldquo;Edit FIll Type&rdquo; dialog box is displayed.</div>
  </li>
  <li class="level1"><div class="li"> Enter:</div>
  <ul>
  <li class="level2"><div class="li"> Fill Type</div>
  </li>
  <li class="level2"><div class="li"> Line Width</div>
  </li>
  <li class="level2"><div class="li"> Angle 1</div>
  </li>
  <li class="level2"><div class="li"> Pitch 1</div>
  </li>
  <li class="level2"><div class="li"> Angle 2</div>
  </li>
  <li class="level2"><div class="li"> Pitch 2</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Press OK.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [74024-74364] -->
  <h3><a name="symbol_translate..._et" id="symbol_translate..._et">Symbol Translate... (et)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Symbol Translate...</strong> is used when creating a symbol, to translate the symbol to an origin for subsequent placement. The symbol may take an optional offset (in mils), as appropriate to the symbol.<br/>
   To translate the symbol:
  </p>
  <ul>
  <li class="level1"><div class="li"> Open a file for the symbol</div>
  </li>
  <li class="level1"><div class="li"> Set the grid snap spacing to 100 mils (<strong>Options</strong> | <strong>Snap Grid Spacing...</strong>).</div>
  </li>
  <li class="level1"><div class="li"> Toggle the grid ON (<strong>Options</strong> | <strong>Toggle Grid On/Off</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Toggle the grid snap ON (<strong>Options</strong> | <strong>Toggle Snap On/Off</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Zoom as appropriate for the symbol&rsquo;s dimensions</div>
  </li>
  <li class="level1"><div class="li"> Draw the symbol, according to the recommendations in the <a href="http://www.geda.seul.org/docs/current/symbols/index.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/symbols/index.html";  rel="nofollow">gEDA/gaf Symbol Creation Document</a></div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Symbol Translate...</strong></div>
  </li>
  <li class="level1"><div class="li"> The &ldquo;Translate&rdquo; dialog box is displayed.</div>
  </li>
  <li class="level1"><div class="li"> Enter 0 to translate to the origin, or enter a value (in mils), positive or negative, to offset the symbol from the origin.</div>
  </li>
  <li class="level1"><div class="li"> Press OK to apply</div>
  </li>
  <li class="level1"><div class="li"> Save the symbol to the file</div>
  </li>
  </ul>
  
  <p>
   If you enter a 0, then all the objects will be translated to the origin.<br/>
   If you enter a non-zero offset, this will be applied equally in both the X and the Y directions.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [74365-75529] -->
  <h3><a name="embed_component_picture_eb" id="embed_component_picture_eb">Embed Component/Picture (eb)</a></h3>
  <div class="level3">
  
  <p>
  <strong>gschem</strong> supports the concept of embedded components and graphics, where all the information necessary to display a component/graphic is placed in the schematic file. <strong>Edit | Embed Component/Picture</strong> causes schematic files to be significantly larger, but it makes it easy to share schematics with other people or archive schematics. You should only embed components when absolutely necessary.<br/>
   To <strong>Embed Component/Picture</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the component/picture (in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Embed Component/Picture</strong></div>
  </li>
  </ul>
  
  <p>
   Save the schematic. The schematic file will now contain the text strings for the embedded component or embedded graphic.<br/>
   The <strong>Add Component...</strong> dialog box allows you to optionally embed the component.<br/>
   The <strong>Add Picture...</strong> dialog box does NOT allow you to optionally embed the component.<br/>
   You can only embed and unembed components. Also, you cannot embed and then mirror a component (this is a limitation of <strong>gschem</strong> and will eventually be fixed).
  </p>
  
  </div>
  <!-- SECTION [75530-76559] -->
  <h3><a name="unembed_component_picture_eu" id="unembed_component_picture_eu">Unembed Component/Picture (eu)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Unembed Component/Picture</strong> will move the component&rsquo;s or graphic&rsquo;s information from the schematic file&rsquo;s contents and output it to the original file&rsquo;s path/filename (i.e., the schematic file includes the path/filename information). To <strong>Unembed Component/Picture</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the component/picture (in <strong>Select Mode</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Unembed Component/Picture</strong></div>
  </li>
  </ul>
  
  <p>
   Save the schematic. The schematic file will now NOT contain the text strings for the embedded component or embedded graphic.<br/>
   You can only embed and unembed components.
  </p>
  
  </div>
  <!-- SECTION [76560-77149] -->
  <h3><a name="update_component_ep" id="update_component_ep">Update Component (ep)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Update Component</strong> updates a component&rsquo;s definition.<br/>
   A symbol can be modified from within <strong>gschem</strong> using the following sequence:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the component for which the symbol should be changed.</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Hierarchy | Down Symbol</strong>. This takes you to the symbol editor</div>
  </li>
  <li class="level1"><div class="li"> Modify the symbol. This includes modifying the symbol&rsquo;s graphic objects, adding/changing/deleting attributes, and moving objects with respect to the origin</div>
  </li>
  <li class="level1"><div class="li"> Don&rsquo;t forget to <strong>Edit | Symbol Translate</strong></div>
  </li>
  <li class="level1"><div class="li"> Select <strong>File | Save Page</strong> to save the symbol to it&rsquo;s file</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Hierarchy | Up Symbol</strong>. This returns you to the schematic editor</div>
  </li>
  <li class="level1"><div class="li"> With the component still selected, select <strong>Edit | Update Component</strong> to update the componet&rsquo;s description from the modified symbol&rsquo;s definition</div>
  </li>
  <li class="level1"><div class="li"> Select each component on the schematic(s) made from this symbol, and select <strong>Edit | Update Component</strong></div>
  </li>
  </ul>
  
  <p>
   New components placed on the schematic from this updated symbol will use the new symbol definition.<br/>
   Components placed on the schematic from this symbol will be updated the next time this schematic is opened.<br/>
   The symbol&rsquo;s <code>symversion</code> attribute will automatically be incremented for non-trivial changes when the symbol is saved. When a schematic is opened by <strong>gschem</strong>, all symbols used by the schematic are read from their libraries. The <code>symversion</code> attribute of the symbol read from the library is compared to the <code>symversion</code> attribute of the components in the schematic. If the <code>symversion</code> attributes are different, the <code>symversion</code> attribute is exposed on the schematic for those symbols effected. Note that:
  </p>
  <ul>
  <li class="level1"><div class="li"> This is a &ldquo;hint&rdquo; to the designer to check the symbol.</div>
  </li>
  <li class="level1"><div class="li"> You need to actually open a schematic file with <strong>gschem</strong> for the components to be updated.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [77150-78959] -->
  <h3><a name="show_hide_inv_text_en" id="show_hide_inv_text_en">Show/Hide Inv Text (en)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Show/Hide Inv Text</strong> is most appropriate when creating or editing symbols, to view or hide the text for all of the symbol&rsquo;s invisible attributes.<br/>
   <a href="#make_inv_text_vis" title="geda:gschem_ug &crarr;" class="wikilink1">Make Inv Text Vis</a> is most appropriate when adding symbols to schematics, to view the text for the symbol&rsquo;s modifiable invisible attributes.<br/>
   <strong>Edit | Show/Hide Inv Text</strong> toggles between making all invisible text visible and hiding all invisible text. When selected, all objects in the symbol are effected.<br/>
   Visible text always remains visible.<br/>
   A symbol has the following <em class="u">potential</em> attributes :
  </p>
  <ul>
  <li class="level1"><div class="li"> netname</div>
  </li>
  <li class="level1"><div class="li"> refdes</div>
  </li>
  <li class="level1"><div class="li"> slot</div>
  </li>
  <li class="level1"><div class="li"> value</div>
  </li>
  <li class="level1"><div class="li"> net</div>
  </li>
  <li class="level1"><div class="li"> device</div>
  </li>
  <li class="level1"><div class="li"> pinnumber</div>
  </li>
  <li class="level1"><div class="li"> pinseq</div>
  </li>
  <li class="level1"><div class="li"> pintype</div>
  </li>
  <li class="level1"><div class="li"> pinlabel</div>
  </li>
  <li class="level1"><div class="li"> source</div>
  </li>
  <li class="level1"><div class="li"> numslots</div>
  </li>
  <li class="level1"><div class="li"> slotdef</div>
  </li>
  <li class="level1"><div class="li"> graphical</div>
  </li>
  <li class="level1"><div class="li"> footprint</div>
  </li>
  <li class="level1"><div class="li"> description</div>
  </li>
  <li class="level1"><div class="li"> documentation</div>
  </li>
  <li class="level1"><div class="li"> symversion</div>
  </li>
  <li class="level1"><div class="li"> comment</div>
  </li>
  <li class="level1"><div class="li"> file</div>
  </li>
  <li class="level1"><div class="li"> model-name</div>
  </li>
  </ul>
  
  <p>
   Not all attributes need to be used to define a symbol (see the discussion of <a href="docs_20060124_gschem_ug_app_a.html" class="wikilink2" title="docs:20060124:gschem_ug:app_a">Appendix A -- Heavy vs Light Symbol Libraries</a>). The <strong>gschem</strong> default is to define symbols as &ldquo;light&rdquo;, indicating that the symbol includes as few attributes as necessary to describe the symbol. &ldquo;light&rdquo; symbols depend on the designer attaching additional descriptive attributes to the symbol when the symbol is placed on the schematic. For example: a &ldquo;light&rdquo; symbol for a resistor might include just the graphic for a resistor, its pin attributes, and the &ldquo;refdes&rdquo; attribute. This describes a resistor. It would be the designer&rsquo;s responsibility, after the resistor has been placed on the schematic, to add the &ldquo;value&rdquo; and &ldquo;footprint&rdquo; attributes appropriate for the specific resistor in the circuit. A &ldquo;heavy&rdquo; symbol includes more descriptive attributes. Using &ldquo;light&rdquo; vs. &ldquo;heavy&rdquo; symbols is up to the designer.<br/>
   A symbol&rsquo;s attributes may be flagged as either visible or invisible. Attributes are flagged as invisible to reduce the clutter around a symbol on the schematic.<br/>
   When creating or editing the symbol, and changing a visible attribute to an invisible attribute, the attribute can not be viewed during further editing of the symbol. It becomes difficult to place attribute text. To view both the visible and invisible text, select <strong>Edit | Show/Hide Inv Text</strong>.<br/>
   When a symbol is instantiated on a schematic as a component, only the symbol&rsquo;s visible attributes are promoted to the component. For example: if a resistor&rsquo;s symbol defines &ldquo;refdes&rdquo; as the only visible attribute defined in the symbol, the only attribute that the component contains is the &ldquo;refdes&rdquo; attribute). Those attributes not included in the symbol definition may be added at the schematic level, component-by-component.<br/>
   This operation is useful when drawing/debugging symbols.<br/>
   When hidden text is visible, &ldquo;Show Hidden&rdquo; will appear on the status-bar in the lower right.
  </p>
  
  </div>
  <!-- SECTION [78960-81787] -->
  <h3><a name="make_inv_text_vis_ev" id="make_inv_text_vis_ev">Make Inv Text Vis (ev)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Edit | Make Inv Text Vis</strong> is a quick method of making all of a component&rsquo;s invisible attributes visible. The same effect can be accomplished by double-clicking on the component and marking all of the entries in the Attributes listbox as &ldquo;Vis?&rdquo; (i.e., visible).<br/>
   To <strong>Make Inv Text Vis</strong> for a component:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select the component(s) in <strong>Select Mode</strong></div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Edit | Make Inv Text Vis</strong></div>
  </li>
  </ul>
  
  <p>
   The attributes that had been hidden are displayed.<br/>
   To hide the attributes again, you need to double-click the component to bring up it&rsquo;s &ldquo;Edit Attributes&rdquo; dialog box, and explicitly place a check for each attribute you want hidden.
  </p>
  
  </div>
  <!-- SECTION [81788-82451] -->
  <h2><a name="buffer" id="buffer">Buffer</a></h2>
  <div class="level2">
  
  <p>
  <strong>gschem</strong> supports 5 copy/cut/paste buffers which are visible across all opened pages and windows.
  </p>
  
  </div>
  <!-- SECTION [82452-82571] -->
  <h3><a name="copy_into_1_2_3_4_5_yc" id="copy_into_1_2_3_4_5_yc">Copy into 1/2/3/4/5 (yc)</a></h3>
  <div class="level3">
  
  <p>
  To copy something into a buffer:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the objects you want to copy.</div>
  </li>
  <li class="level1"><div class="li"> Select Buffer/Copy/Copy into buffer #.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [82572-82724] -->
  <h3><a name="cut_into_1_2_3_4_5_yu" id="cut_into_1_2_3_4_5_yu">Cut into 1/2/3/4/5 (yu)</a></h3>
  <div class="level3">
  
  <p>
  Cut is like copy in that it removes the objects from the schematic
  </p>
  
  </div>
  <!-- SECTION [82725-82826] -->
  <h3><a name="paste_from_1_2_3_4_5_yp" id="paste_from_1_2_3_4_5_yp">Paste from 1/2/3/4/5 (yp)</a></h3>
  <div class="level3">
  
  <p>
  To paste a buffer into the current schematic:
  </p>
  <ol>
  <li class="level1"><div class="li"> Fill the buffer using the above Copy or Cut.</div>
  </li>
  <li class="level1"><div class="li"> Go to the new schematic page/window.</div>
  </li>
  <li class="level1"><div class="li"> Select Buffer/Paste/Paste from buffer #.</div>
  </li>
  <li class="level1"><div class="li"> Click the first mouse button to pick an anchor point.</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse to the final spot.</div>
  </li>
  <li class="level1"><div class="li"> Click the first mouse button again.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [82827-83180] -->
  <h2><a name="view" id="view">View</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [83181-83198] -->
  <h3><a name="redraw_vr" id="redraw_vr">Redraw (vr)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Redraw</strong> re-paints the current window.<br/>
   This is useful when you have mouse/component/line/text etc... droppings left over from a previous action. It is also useful when you want to update all visual connectivity cues.
  </p>
  
  </div>
  <!-- SECTION [83199-83449] -->
  <h3><a name="pan_x" id="pan_x">Pan (x)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Pan</strong> lets you change the focus of the display.<br/>
   To pan the display:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Pan</strong></div>
  </li>
  <li class="level1"><div class="li"> Click the first mouse button at the new center of the display.</div>
  </li>
  </ul>
  
  <p>
   To pan the display using the shortcut is much simpler, simply place the mouse pointer where you want the display centered and type &ldquo;x&rdquo;. The display will jump to the mouse&rsquo;s location.<br/>
   Pan behavior is configurable. The system-gschemrc file defines: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(third-button &quot;popup&quot;)</font></pre>
  </p>
  
  <p>
  If you override the system-gschemrc&rsquo;s default, of popping up a menu when the third mouse button is clicked, by adding: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(third-button &quot;mousepan&quot;)</font></pre>
  </p>
  
  <p>
  to either your user&rsquo;s ~/gschemrc file or local &lsquo;pwd&rsquo;/gschemrc file, the third mouse button (i.e., the right mouse button on scroll-wheel mice) will allow you to pan the schematic by holding down the third mouse button and dragging.<br/>
   The system-gschemrc file also defines: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(fast-mousepan &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  If you override the system-gschemrc&rsquo;s default by adding: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(fast-mousepan &quot;disabled&quot;)</font></pre>
  </p>
  
  <p>
  to either your user&rsquo;s ~/gschemrc file or local &lsquo;pwd&rsquo;/gschemrc file, text will be displayed properly when the third mouse button is held down while dragging. The <code>(third-button &ldquo;mousepan&rdquo;)</code> setting must also be applied for this to work. Disabling <code>fast-mousepan</code> adversely effects rendering speed while panning on large &ldquo;complicated&rdquo; schematics.<br/>
   The system-gschemrc file also defines: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  If you override the system-gschemrc&rsquo;s default by adding: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;disabled&quot;)</font></pre>
  </p>
  
  <p>
  to either your user&rsquo;s ~/gschemrc file or local &lsquo;pwd&rsquo;/gschemrc file, whenever you zoom in/out, the zoom will NOT center on the mouse pointer, effectively removing the pan feature of the zoom in/out operations.
  </p>
  
  </div>
  <!-- SECTION [83450-85246] -->
  <h3><a name="zoom_box_w" id="zoom_box_w">Zoom Box (w)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Zoom Box</strong> allows you to draw a box around a part of the <strong>gschem</strong> window and zoom  in.<br/>
   To use <strong>View | Zoom Box</strong>:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Zoom Box</strong></div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer at one corner of the box you want to draw</div>
  </li>
  <li class="level1"><div class="li"> Click and hold down the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Drag the mouse, drawing the zoom box around the area to which you want to zoom</div>
  </li>
  <li class="level1"><div class="li"> Release the mouse button and the display will zoom</div>
  </li>
  </ul>
  
  <p>
   To use <strong>View | Zoom Box</strong> by typing the equivalent shortcut (i.e., &ldquo;<strong>w</strong>&ldquo;) is more convenient. Simply position the mouse pointer at one corner of the zoom box, then type &ldquo;<strong>w</strong>&ldquo;.  The zoom box will start immediately using the current mouse location as the first corner of the box.<br/>
   <strong>View | Zoom Box</strong> will attempt to zoom to the requested area, but some boxes are not legal and <strong>gschem</strong> will do it&rsquo;s best to zoom the requested area.
  </p>
  
  </div>
  <!-- SECTION [85247-86127] -->
  <h3><a name="zoom_extents_ve" id="zoom_extents_ve">Zoom Extents (ve)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Extents</strong> will zoom the display to fit all of the placed objects into the current window.<br/>
   To view all of the current window&rsquo;s objects:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Extents</strong></div>
  </li>
  </ul>
  
  <p>
   Typing the <strong>View | Extents</strong> shortcut (i.e., &ldquo;<strong>ve</strong>&ldquo;) is particularly convenient for those that have learned to navigate the schematics using the shortcuts.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [86128-86494] -->
  <h3><a name="zoom_in_z" id="zoom_in_z">Zoom In (z)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Zoom In</strong> zooms the display in. The current center of the window is the center of the new window. This command zooms in by a factor.<br/>
   To zoom in:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Zoom In</strong></div>
  </li>
  </ul>
  
  <p>
   The (zoom-with-pan &ldquo;enabled&rdquo;) configuration setting in the gschemrc files effects the operation of the zoom in shortcut (i.e., &ldquo;<strong>z</strong>&ldquo;). The default system-gschemrc setting for: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  enables zooming in, using the mouse pointer&rsquo;s location as the new center of the window. If this changed to: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;disabled&quot;)</font></pre>
  </p>
  
  <p>
  in either your user&rsquo;s ~/gschemrc file or local &lsquo;pwd&rsquo;/gschemrc file, whenever you zoom in, the zoom will NOT center on the mouse pointer but will center on the current center of the window, effectively removing the pan feature of the zoom in operation.<br/>
   To zoom in using the shortcut:
  </p>
  <ul>
  <li class="level1"><div class="li"> If the default (zoom-with-pan &ldquo;enabled&rdquo;) is configured in one of the gschemrc files, position the mouse pointer in the window where you want the new center</div>
  </li>
  <li class="level1"><div class="li"> Type &ldquo;<strong>z</strong>&rdquo;</div>
  </li>
  </ul>
  
  <p>
   Typing &ldquo;<strong>z</strong>&rdquo; is particularly convenient for those that have learned to navigate the schematics using the shortcuts.
  </p>
  
  </div>
  <!-- SECTION [86495-87656] -->
  <h3><a name="zoom_out_z" id="zoom_out_z">Zoom Out (Z)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Zoom Out</strong> zooms the display out. The current center of the window is the center of the new window. This command zooms out by a factor.<br/>
   To zoom out:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Zoom Out</strong></div>
  </li>
  </ul>
  
  <p>
   The (zoom-with-pan &ldquo;enabled&rdquo;) configuration setting in the gschemrc files effects the operation of the zoom out shortcut (i.e., &ldquo;<strong>z</strong>&ldquo;). The default system-gschemrc setting for: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;enabled&quot;)</font></pre>
  </p>
  
  <p>
  enables zooming out, using the mouse pointer&rsquo;s location as the new center of the window. If this changed to: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">(zoom-with-pan &quot;disabled&quot;)</font></pre>
  </p>
  
  <p>
  in either your user&rsquo;s ~/gschemrc file or local &lsquo;pwd&rsquo;/gschemrc file, whenever you zoom out, the zoom will NOT center on the mouse pointer but will center on the current center of the window, effectively removing the pan feature of the zoom out operation.<br/>
   To zoom out using the shortcut:
  </p>
  <ul>
  <li class="level1"><div class="li"> If the default (zoom-with-pan &ldquo;enabled&rdquo;) is configured in one of the gschemrc files, position the mouse pointer in the window where you want the new center</div>
  </li>
  <li class="level1"><div class="li"> Type &ldquo;<strong>Z</strong>&rdquo; (i.e., shift-z)</div>
  </li>
  </ul>
  
  <p>
   Typing &ldquo;<strong>Z</strong>&rdquo; is particularly convenient for those that have learned to navigate the schematics using the shortcuts.
  </p>
  
  </div>
  <!-- SECTION [87657-88845] -->
  <h3><a name="zoom_full_vf" id="zoom_full_vf">Zoom Full (vf)</a></h3>
  <div class="level3">
  
  <p>
  <strong>View | Zoom Full</strong> will zoom the display to the maximum possible displayable view.<br/>
  
  </p>
  
  <p>
  To view the maximum displayable area:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>View | Zoom Full</strong></div>
  </li>
  </ul>
  
  <p>
   The window contents will immediately change to show the maximum possible displayable view.<br/>
  
  </p>
  
  <p>
  To view the maximum displayable area using the keyboard shortcut (i.e., &ldquo;<strong>vf</strong>&ldquo;):
  </p>
  <ul>
  <li class="level1"><div class="li"> Type &ldquo;<strong>vf</strong>&rdquo;</div>
  </li>
  </ul>
  
  <p>
   The window contents will immediately change to show the maximum possible displayable view.<br/>
  
  </p>
  
  <p>
  <strong>View | Zoom Full</strong> is useful if you like to put your working notes outside the titleblock for you schematic, for example. Just remember, these notes would now be considered part of the windows extents, so if you were to <strong>View | Extents</strong>, the display would show the titleblock and your working notes.
  </p>
  
  </div>
  <!-- SECTION [88846-89624] -->
  <h2><a name="page" id="page">Page</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [89625-89643] -->
  <h3><a name="manager..._pm" id="manager..._pm">Manager... (pm)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89644-89671] -->
  <h3><a name="next" id="next">Next (&gt;)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89672-89692] -->
  <h3><a name="previous" id="previous">Previous (&lt;)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89693-89717] -->
  <h3><a name="new_pe" id="new_pe">New (pe)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89718-89738] -->
  <h3><a name="revert_pr" id="revert_pr">Revert (pr)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89739-89762] -->
  <h3><a name="close_pc" id="close_pc">Close (pc)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89763-89785] -->
  <h3><a name="discard_pd" id="discard_pd">Discard (pd)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [89786-89810] -->
  <h2><a name="add" id="add">Add</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [89811-89827] -->
  <h3><a name="component..._i" id="component..._i">Component... (i)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Component...</strong> opens a dialog box which lets you place components from the component libraries.<br/>
   To place a component:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>Add |Component...</strong></div>
  </li>
  <li class="level1"><div class="li"> Select a component Library from the left list-box</div>
  </li>
  <li class="level1"><div class="li"> Select a component from the right list-box</div>
  </li>
  <li class="level1"><div class="li"> Confirm the symbol is correct by reviewing the image in the Preview window</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse into the main drawing window (you should see an outline follow the mouse pointer).</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button to anchor the component</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer, and keep pressing the first mouse button to anchor additional instances of the component</div>
  </li>
  <li class="level1"><div class="li"> When finished anchoring components, press the last mouse button or the ESC key</div>
  </li>
  </ul>
  
  <p>
   If a component name is already selected, hitting apply and moving the mouse into the main window will allow you to place that component again.<br/>
   You can rotate the component before you place it by clicking the middle button. For every button click, the component will be rotate counter-clockwise 90 degrees.<br/>
   Care has been taken to give components descriptive names in the libraries, though it is sometimes difficult to determine what the component really represents from its name.<br/>
   For example: in the analog library there are four capacitor entries:
  </p>
  <ul>
  <li class="level1"><div class="li"> capacitor-1.sym</div>
  </li>
  <li class="level1"><div class="li"> capacitor-2.sym</div>
  </li>
  <li class="level1"><div class="li"> capacitor-3.sym</div>
  </li>
  <li class="level1"><div class="li"> capacitor-4.sym</div>
  </li>
  </ul>
  
  <p>
   It helps to preview the symbol in the &ldquo;Select Component&rdquo; dialog box before selecting and placing the symbol.
  </p>
  
  </div>
  <!-- SECTION [89828-91304] -->
  <h3><a name="net_n" id="net_n">Net (n)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Net</strong> draws a net segment.<br/>
   A net is typically a contiguous set of line segments between two pins, though it is possible to draw nets between a pin and a point on another net, or between two nets.<br/>
   For example, the following diagram shows 3 net segments:
  </p>
  <ul>
  <li class="level1"><div class="li"> Between R1 and R2</div>
  </li>
  <li class="level1"><div class="li"> Between R3 and R4</div>
  </li>
  <li class="level1"><div class="li"> Between the two nets</div>
  </li>
  </ul>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_nets.html" class="media" title="geda:nets.jpg"><img src="_media/geda_nets.jpg" class="media" title="nets.jpg" alt="nets.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  <p>
   Note the small red segment at the end of the resistor&rsquo;s pins. All pins in <strong>gschem</strong> have this red segment. This is the connectivity cue for the pin. It is sometimes difficult to &ldquo;grab&rdquo; this attachment point when drawing nets, you may need to zoom in on the pin. To zoom in, press the &ldquo;z&rdquo; key. To zoom out, press the &ldquo;Z&rdquo; (i.e., shift-z) key.<br/>
   To begin drawing a net using the menu:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>Add | Net</strong></div>
  </li>
  <li class="level1"><div class="li"> Zoom in on the component where the net is to start, so that you can easily grab the pin&rsquo;s attachment point</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer over the pin&rsquo;s connectivity cue</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button to start the net</div>
  </li>
  </ul>
  
  <p>
   To begin drawing the net using the shortcut:
  </p>
  <ul>
  <li class="level1"><div class="li"> Zoom in on the component where the net is to start, so that you can easily grab the pin&rsquo;s attachment point</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer over the pin&rsquo;s connectivity cue</div>
  </li>
  <li class="level1"><div class="li"> Press the &ldquo;n&rdquo; key</div>
  </li>
  </ul>
  
  <p>
   To continue drawing the net segment(s):
  </p>
  <ul>
  <li class="level1"><div class="li"> Drag the mouse pointer in the direction of the end-point</div>
  </li>
  <li class="level1"><div class="li"> For any necessary 90Âº turns, single-click the mouse, and continue dragging the mouse pointer toward the end-point</div>
  </li>
  <li class="level1"><div class="li"> For any necessary non-orthogonal net segments (e.g., 45Âº angle), hold down the CONTROL button, single-click the mouse, and continue dragging the mouse pointer to the end-point</div>
  </li>
  <li class="level1"><div class="li"> When you reach the end-point, press the first mouse button to end the net segment</div>
  </li>
  <li class="level1"><div class="li"> Another net segment will start at the last end-point</div>
  <ul>
  <li class="level2"><div class="li"> If this second pin is to be connected to a third pin, continue as above</div>
  </li>
  <li class="level2"><div class="li"> If this is the end of the connections, press the last mouse button (or ESC) to end the net</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Press the last mouse button or ESC to cancel any net in progress.<br/>
   If the net is cancelled you are automatically placed in <strong>Select Mode</strong>. You must pick <strong>Add | Net</strong> again or type the shortcut to add more nets.<br/>
   You cannot connect a net segment to the middle of a non-orthogonal net.<br/>
   The boxes at the end of the nets are connectivity cues. Red boxes signify a dangling net (not connected to anything).<br/>
   Filled circles are midpoint connections/junctions. These cues are drawn automatically and are an indicator of electrical connectivity.<br/>
   See <a href="docs_20060124_gschem_ug_electrical_connectivity.html" class="wikilink2" title="docs:20060124:gschem_ug:electrical_connectivity">Electrical Connectivity</a> for more information.
  </p>
  
  </div>
  <!-- SECTION [91305-93896] -->
  <h3><a name="bus_u" id="bus_u">Bus (u)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Bus</strong> is basically the same as <strong>Add | Net</strong>, except that it draws buses.<br/>
   Buses are very new and there are many aspects which are not defined yet, so keep that in mind as you uses buses. More to be added here eventually.
  </p>
  
  </div>
  <!-- SECTION [93897-94146] -->
  <h3><a name="attribute..._aa" id="attribute..._aa">Attribute... (aa)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Attribute...</strong> is appropriate when creating or editing symbols, to add a new attribute.<br/>
   <strong>Add | Attribute...</strong> brings up the &ldquo;Single Attribute Editor&rdquo; dialog box. This dialog box is ONLY used to add attributes. It does not display or manipulate already placed attributes.<br/>
   An attribute is nothing more than a text item which is in the form <code>name=value</code> (there cannot be any spaces to the left or right of the name,value pair). It can be either attached to an object, or unattached.<br/>
   To add an unattached attribute (e.g., &ldquo;comment&rdquo;, &ldquo;documentation&rdquo;, etc.) to the symbol:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>Add | Attribute...</strong></div>
  </li>
  <li class="level1"><div class="li"> Select an attribute name off of the pulldown list, or type the attribute name into the name entry</div>
  </li>
  <li class="level1"><div class="li"> Type in a value for the attribute</div>
  </li>
  <li class="level1"><div class="li"> Pick any of the attribute options</div>
  </li>
  <li class="level1"><div class="li"> Click OK, and the attribute will be placed.</div>
  </li>
  </ul>
  
  <p>
   If you want to attach an attribute to an object, then select the desired object first and then <strong>Add | Attribute...</strong> from the pull-down menu. If you click on an object which has attached attributes, the attached attributes should be selected as well.<br/>
   If you select <strong>Add | Attribute...</strong> off of the pull down menus then you do not have much control as to where the attribute gets placed (it gets places either at the lower left hand corner of the object extents or at the origin of any selected object). However, if you use the hot key (i.e., &ldquo;aa&rdquo;) then the current mouse position is used as the anchor point for the attribute item.<br/>
   You cannot place an incomplete attribute (an attribute without a name and value).<br/>
   Please see <a href="docs_20060124_gschem_ug_components_symbols_objects_attributes.html" class="wikilink2" title="docs:20060124:gschem_ug:components_symbols_objects_attributes">Components/Symbols/Objects/Attributes</a> for more info on how to use attributes.
  </p>
  
  </div>
  <!-- SECTION [94147-95859] -->
  <h3><a name="text..._at" id="text..._at">Text... (at)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Text...</strong> displays the &ldquo;Text Entry...&rdquo; dialog box. To place text:
  </p>
  <ul>
  <li class="level1"><div class="li"> Select <strong>Options | Text Size...</strong> and select the size for the text</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Text...</strong></div>
  </li>
  <li class="level1"><div class="li"> Type the text in the entry field (multiple lines may be entered by pressing Enter)</div>
  </li>
  <li class="level1"><div class="li"> Press Apply or type Enter</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse into the main window (an outline of the text should appear and follow the mouse)</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button to anchor the text</div>
  </li>
  <li class="level1"><div class="li"> Close the &ldquo;Text Entry...&rdquo; dialog box</div>
  </li>
  </ul>
  
  <p>
   If you leave the <strong>Add | Text...</strong> dialog box open you can place the same text item again and again by just clicking Apply (or pressing Enter) and moving the mouse into the main window.<br/>
   The following settings in the system-gschemrc file, the user&rsquo;s ~/gschemrc file, or the local &lsquo;pwd&rsquo;/gschemrc file control how text is displayed:</p>
  <dl>
  <dt><span class='term'> text-origin-marker</span></dt>
  <dd>Controls if the text origin markers are displayed.</dd>
  <dt><span class='term'> text-size</span></dt>
  <dd>Sets the default text size.</dd>
  <dt><span class='term'> text-caps-style</span></dt>
  <dd>Sets the default caps style used for the display of text</dd>
  <dt><span class='term'> output-text</span></dt>
  <dd>Controls how text is rendered to postscript</dd>
  </dl>
  <p>Text which is placed will be automatically capitalized. Please see the Resource file section below on how to control this behavior.<br/>
   To cancel a text place press the last mouse button or the ESC key.<br/>
   If you create text in the form name=value, then you are creating attributes. gEDA allows for general attributes to be free floating (or unattached). It is a good idea to change the color of these floating attributes to the current attribute color (which is also called the attached attribute color) to signify that this text item is an attribute.<br/>
   You can rotate the text before you place it by clicking the middle button. For every button click, the text will be rotate 90 degrees.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [95860-97651] -->
  <h3><a name="line_l" id="line_l">Line (l)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Line</strong> draws a single line segment.<br/>
   To draw a line:
  </p>
  <ul>
  <li class="level1"><div class="li"> If you want to snap the line to the grid, set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you don&rsquo;t see &ldquo;Snap Off&rdquo; on the status-bar</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Line</strong></div>
  </li>
  <li class="level1"><div class="li"> If you want to constrain the line to 90Âº movements, hold the CONTROL key down while moving the mouse</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer to the start-point</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse in the intended direction</div>
  </li>
  <li class="level1"><div class="li"> When positioned at the end-point, press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Continue placing lines, until you either press the second mouse button or type the Escape key</div>
  </li>
  </ul>
  
  <p>
     <strong>Add | Line</strong> draws a line in the same fashion as drawing nets with the following exceptions:
  </p>
  <ul>
  <li class="level1"><div class="li"> A line has no electrical significance</div>
  </li>
  <li class="level1"><div class="li"> Only a single line segment can be drawn</div>
  </li>
  <li class="level1"><div class="li"> You keep drawing lines as long as you are in line <strong>Line Mode</strong>.</div>
  </li>
  </ul>
  
  <p>
   To cancel a line in progress, press the last mouse button or type the ESC key.
  </p>
  
  </div>
  <!-- SECTION [97652-98738] -->
  <h3><a name="box_b" id="box_b">Box (b)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Box</strong> draws a box. To draw a box:
  </p>
  <ul>
  <li class="level1"><div class="li"> If you want to snap the box to the grid, set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you donâ??t see â??Snap Offâ?? on the status-bar</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Box</strong></div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer to the start-point</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse in the intended direction</div>
  </li>
  <li class="level1"><div class="li"> When positioned at the end-point, press the first mouse button again</div>
  </li>
  <li class="level1"><div class="li"> Continue placing boxes, until you either press the second mouse button or type the ESC key</div>
  </li>
  </ul>
  
  <p>
   To cancel a box in progress, press the last mouse button or type the ESC key.<br/>
   A box has no electrical significance.
  </p>
  
  </div>
  <!-- SECTION [98739-99491] -->
  <h3><a name="circle_ai" id="circle_ai">Circle (ai)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Circle</strong> creates a circle.<br/>
   To draw a circle:
  </p>
  <ul>
  <li class="level1"><div class="li"> If you want to snap the box to the grid, set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you donâ??t see â??Snap Offâ?? on the status-bar</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Circle</strong></div>
  </li>
  <li class="level1"><div class="li"> Place the mouse pointer at the center of the circle</div>
  </li>
  <li class="level1"><div class="li"> Press the first button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse to see an outline of the circle</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button to finish the circle</div>
  </li>
  <li class="level1"><div class="li"> Continue placing circles, until you either press the second mouse button or type the ESC key</div>
  </li>
  </ul>
  
  <p>
   To draw a circle (typing the shortcut), same as above except that you position the mouse pointer to the center-point of the circle before you type the shortcut.<br/>
   To cancel a circle in progress, press the last mouse button or the ESC key.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [99492-100376] -->
  <h3><a name="arc_ar" id="arc_ar">Arc (ar)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Arc</strong> draws an arc. To draw an arc:
  </p>
  <ul>
  <li class="level1"><div class="li"> If you want to snap the box to the grid, set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you donâ??t see â??Snap Offâ?? on the status-bar</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Arc</strong></div>
  </li>
  <li class="level1"><div class="li"> Place the mouse pointer at the center-point for the arc</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse to the right, to define the radius of the arc</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button again</div>
  </li>
  <li class="level1"><div class="li"> Enter the Start Angle (in degrees) &ndash; 0Âº is the &ldquo;x&rdquo; axis</div>
  </li>
  <li class="level1"><div class="li"> Enter the Degrees of Sweep (for counter-clockwise sweep)</div>
  </li>
  <li class="level1"><div class="li"> Press OK</div>
  </li>
  <li class="level1"><div class="li"> Continue placing arcs, until you either press the second mouse button or type the ESC key</div>
  </li>
  </ul>
  
  <p>
   The Start Angle can be positive or negative. The degrees are specified using the standard Cartesian coordinate system. The degrees of sweep can be positive or negative.<br/>
   To cancel an arc in progress (while rubberband the radius), press the last mouse button or the ESC key or press the Cancel button in the arc dialog box.
  </p>
  
  </div>
  <!-- SECTION [100377-101469] -->
  <h3><a name="pin_ap" id="pin_ap">Pin (ap)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Pin</strong> adds a pin.<br/>
   Though you can <strong>Add | Pin</strong> while entering a schematic, it only makes sense to create pins while creating or editing symbol files.<br/>
   To draw a pin:
  </p>
  <ul>
  <li class="level1"><div class="li"> Set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you donâ??t see â??Snap Offâ?? on the status-bar. The <a href="http://www.geda.seul.org/docs/current/symbols/symbols.pdf"; class="urlextern" title="http://www.geda.seul.org/docs/current/symbols/symbols.pdf";  rel="nofollow">gEDA/gaf Symbol Creation Document</a> specifies grid settings for pin placement in gEDA/gaf compliant symbols files.</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Pin</strong></div>
  </li>
  <li class="level1"><div class="li"> Pins are constrained to 90Âº movements</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer to the start-point</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse in the intended direction. The <a href="http://www.geda.seul.org/docs/current/symbols/symbols.pdf"; class="urlextern" title="http://www.geda.seul.org/docs/current/symbols/symbols.pdf";  rel="nofollow">gEDA/gaf Symbol Creation Document</a> specifies the length of pins in gEDA/gaf compliant symbol files.</div>
  </li>
  <li class="level1"><div class="li"> When positioned at the end-point, press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Continue placing pins, until you either press the second mouse button or type the Escape key</div>
  </li>
  </ul>
  
  <p>
   To cancel a pin in progress, press the last mouse button or the ESC key.
  </p>
  
  </div>
  <!-- SECTION [101470-102657] -->
  <h3><a name="picture..._ag" id="picture..._ag">Picture... (ag)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Add | Picture</strong> places a graphic in the schematic. To draw a picture:
  </p>
  <ul>
  <li class="level1"><div class="li"> If you want to snap the picture to the grid, set the grid spacing by selecting <strong>Options | Snap Grid Spacing...</strong> and entering the grid spacing, and then selecting <strong>Options | Toggle Snap On/Off</strong> until you donâ??t see â??Snap Offâ?? on the status-bar</div>
  </li>
  <li class="level1"><div class="li"> Select <strong>Add | Picture</strong></div>
  </li>
  <li class="level1"><div class="li"> Select the graphic file from the &ldquo;Please select a picture file&rdquo; dialog box</div>
  </li>
  <li class="level1"><div class="li"> Press OK</div>
  </li>
  <li class="level1"><div class="li"> Position the mouse pointer to the start-point</div>
  </li>
  <li class="level1"><div class="li"> Press the first mouse button</div>
  </li>
  <li class="level1"><div class="li"> Move the mouse in the intended direction. The outline of the picture will appear, retaining the aspect ratio of the original picture.</div>
  </li>
  <li class="level1"><div class="li"> When positioned at the end-point, press the first mouse button again.</div>
  </li>
  <li class="level1"><div class="li"> Continue placing pictures, until you either press the second mouse button or type the ESC key</div>
  </li>
  </ul>
  
  <p>
   To cancel a picture in progress, press the last mouse button or type the ESC key.<br/>
   A picture has no electrical significance.
  </p>
  
  </div>
  <!-- SECTION [102658-103653] -->
  <h2><a name="hierarchy" id="hierarchy">Hierarchy</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [103654-103676] -->
  <h3><a name="down_schematic_hd" id="down_schematic_hd">Down Schematic (Hd)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Hierarchy | Down Schematic</strong> shifts the focus from the current schematic to a sub-schematic.<br/>
   Go down into a symbol, opening up any underlying schematics. Basically this will open up an underlying schematic of the selected component if it exists in the source library search path. See the Resource File section on how to define this path.<br/>
   There are currently two ways of specifying that a symbol has an underlying schematic or schematics:
  </p>
  <ol>
  <li class="level1"><div class="li"> The underlying schematic must have the same name as the symbol but have a .sch extension and must follow the _# suffix naming convention. See the Files section below on this convention.</div>
  </li>
  <li class="level1"><div class="li"> Attach an attribute to the symbol called source=filename.sch filename.sch is not a path to the symbol, but rather the basename (last file in the path specifier) of the symbol path. The underlying schematic will still be searched in the source-library path. You can specify multiple source= attributes. The underlying schematics will be opened in the order that the source= attribute is found.</div>
  </li>
  </ol>
  
  <p>
   If there multiple underlying schematics, they will be loaded. Movement between the schematic pages is restricted (to the same level of the same set of underlying schematics) unless the rc keyword enforce-hierarchy is modified to allow for a freer hierarchy traversal mode. See the Resource File section for more info.<br/>
   It is also recommend that you maintain unique names for the various levels (when using the source= attribute) to avoid possible confusion. The hierarchy mechanisms are fairly new so expect some odd behavior (and please report it)
  </p>
  
  </div>
  <!-- SECTION [103677-105289] -->
  <h3><a name="down_symbol_hs" id="down_symbol_hs">Down Symbol (Hs)</a></h3>
  <div class="level3">
  
  <p>
  This option will open up the symbol of the selected component.<br/>
   Once the symbol is open, the user can edit it and save it.<br/>
   At this time, the toplevel schematic will not see the symbol change unless the toplevel schematic is reloaded or File/Revert is executed. This will be fixed eventually.
  </p>
  
  </div>
  <!-- SECTION [105290-105612] -->
  <h3><a name="up_hu" id="up_hu">Up (Hu)</a></h3>
  <div class="level3">
  
  <p>
  This option will move up the hierarchy (if there are pages above the currently displayed page).
  </p>
  
  </div>
  <!-- SECTION [105613-105727] -->
  <h3><a name="documentation_ho" id="documentation_ho">Documentation (Ho)</a></h3>
  <div class="level3">
  
  <p>
  Open any documentation available for the selected symbol/component.<br/>
   The job is handed over to &ldquo;gschemdoc&rdquo;, which makes a best-effort attempt of finding relevant documentation.<br/>
   The documention would normally be in <acronym title="Portable Document Format">PDF</acronym>, <acronym title="HyperText Markup Language">HTML</acronym>, text or image format, but gschemdoc tries to be as transparent as possible on this account.<br/>
   First and foremost, the attribute &ldquo;documentation=&rdquo; is assumed to point to the documentation. This attribute should either be the filename (basename) of the document, or it should be a complete <acronym title="Uniform Resource Locator">URL</acronym>.<br/>
   If it is a filename, and the file is found locally (in /usr/share/gEDA/documentation or otherwise), the relevant viewer will be initiated. Otherwise, a Google search for the document will be initiated.<br/>
   If there is no documentation attribute, the attributes &ldquo;device&rdquo; and possibly &ldquo;value&rdquo; will be consulted in much the same way as for &ldquo;documentation&rdquo;. File searches will be made in forms of filenames like &ldquo;device-value.pdf&rdquo; and &ldquo;device.pdf&rdquo;.<br/>
   Failing that, the file name for the symbol itself will be used as basis for the search.
  </p>
  
  </div>
  <!-- SECTION [105728-106812] -->
  <h2><a name="attributes1" id="attributes1">Attributes</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [106813-106836] -->
  <h3><a name="attach_ta" id="attach_ta">Attach (ta)</a></h3>
  <div class="level3">
  
  <p>
  The Attach command allows you to take a text item (in the proper form; <code>name=value</code>) and attach it to another object.<br/>
   To use Attributes/Attach:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the object which will receive the attributes</div>
  </li>
  <li class="level1"><div class="li"> Select the text object(s) which will be attached to the above object</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Attach</div>
  </li>
  </ol>
  
  <p>
   The order of the sequence of selecting the object and then the text items is important; <strong>gschem</strong> will not allow you to select the text items first and then the object. After going through the above sequence the text item will turn yellow (or the current attached attribute color) signifying that the text item is an attached attribute.<br/>
   You cannot attach a single attribute to several different objects. You cannot attach non-text items as attributes.
  </p>
  
  </div>
  <!-- SECTION [106837-107644] -->
  <h3><a name="detach_td" id="detach_td">Detach (td)</a></h3>
  <div class="level3">
  
  <p>
  Detach allows you to deassociate attributes from objects.<br/>
   To deselect an object of all attributes:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the object of interest</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Detach</div>
  </li>
  </ol>
  
  <p>
   All the attached attributes (even if they are not selected) will be detached from the object. This behavior is probably broken and will eventually be fixed (so that only selected attributes are detached).<br/>
   When you detach attributes then they turn red (or the current detached attribute color). This color changes allows you to spot text which was an attribute and is now dangling (unattached).
  </p>
  
  </div>
  <!-- SECTION [107645-108251] -->
  <h3><a name="show_value_tv" id="show_value_tv">Show Value (tv)</a></h3>
  <div class="level3">
  
  <p>
  These operations allow you to control which part of the attribute string is visible. Usually you are just interested in seeing the <code>value</code> of the attribute, but there are circumstances where seeing the <code>name</code> and <code>value</code> (or maybe just the <code>name</code>) would be useful.<br/>
   To use the options:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the attribute(s) of interest</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Show *</div>
  </li>
  </ol>
  
  <p>
   The text item(s) should immediately change.<br/>
   These operations only work on text items which are in the form <code>name=value</code>
  </p>
  
  </div>
  <!-- SECTION [108252-108790] -->
  <h3><a name="show_name_tn" id="show_name_tn">Show Name (tn)</a></h3>
  <div class="level3">
  
  <p>
  These operations allow you to control which part of the attribute string is visible. Usually you are just interested in seeing the <code>value</code> of the attribute, but there are circumstances where seeing the <code>name</code> and <code>value</code> (or maybe just the <code>name</code>) would be useful.<br/>
   To use the options:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the attribute(s) of interest</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Show *</div>
  </li>
  </ol>
  
  <p>
   The text item(s) should immediately change.<br/>
   These operations only work on text items which are in the form <code>name=value</code>
  </p>
  
  </div>
  <!-- SECTION [108791-109328] -->
  <h3><a name="show_both_tb" id="show_both_tb">Show Both (tb)</a></h3>
  <div class="level3">
  
  <p>
  These operations allow you to control which part of the attribute string is visible. Usually you are just interested in seeing the <code>value</code> of the attribute, but there are circumstances where seeing the <code>name</code> and <code>value</code> (or maybe just the <code>name</code>) would be useful.<br/>
   To use the options:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the attribute(s) of interest</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Show *</div>
  </li>
  </ol>
  
  <p>
   The text item(s) should immediately change.<br/>
   These operations only work on text items which are in the form <code>name=value</code>
  </p>
  
  </div>
  <!-- SECTION [109329-109866] -->
  <h3><a name="toggle_visibility_tt" id="toggle_visibility_tt">Toggle Visibility (tt)</a></h3>
  <div class="level3">
  
  <p>
  This operation allows you to toggle the visibility of attributes.<br/>
   To use this option:
  </p>
  <ol>
  <li class="level1"><div class="li"> Select the text item(s) of interest</div>
  </li>
  <li class="level1"><div class="li"> Pick or type the shortcut for Attributes/Toggle Vis</div>
  </li>
  </ol>
  
  <p>
   The text item(s) should change their visibility immediately.<br/>
   If you make an attached attribute invisible, then you can simply select the parent object and select Toggle Vis and the attribute will be come visible (likewise any visible attributes attached to that object will become invisible).<br/>
   If you make a free floating (unattached) attribute invisible, then the only way to make it visible (and all other invisible attributes) is to use the Edit/Show Hidden Text option.
  </p>
  
  </div>
  <!-- SECTION [109867-110562] -->
  <h3><a name="find_specific_text..._t_shift-f" id="find_specific_text..._t_shift-f">Find Specific Text... (t shift-f)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [110563-110607] -->
  <h3><a name="hide_specific_text..._th" id="hide_specific_text..._th">Hide Specific Text... (th)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [110608-110645] -->
  <h3><a name="show_specific_text..._t_shift-h" id="show_specific_text..._t_shift-h">Show Specific Text... (t shift-h)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [110646-110689] -->
  <h3><a name="autonumber_text..._tu" id="autonumber_text..._tu">Autonumber Text... (tu)</a></h3>
  <div class="level3">
  
  </div>
  <!-- SECTION [110690-110724] -->
  <h2><a name="options" id="options">Options</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [110725-110745] -->
  <h3><a name="text_size..._ot" id="text_size..._ot">Text Size... (ot)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Text Size...</strong> pops up a dialog box which allows you to specify the text size of all text (including attributes placed with the Add/Attribute... dialog box).<br/>
   The text size is in points (1/72&rdquo;). The default text size is 10 point text. The smallest text size is 2 points.
  </p>
  
  </div>
  <!-- SECTION [110746-111058] -->
  <h3><a name="toggle_grid_on_off_og" id="toggle_grid_on_off_og">Toggle Grid On/Off (og)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Toggle Grid On/Off</strong> toggles the visible grid.
  </p>
  
  </div>
  <!-- SECTION [111059-111152] -->
  <h3><a name="toggle_snap_on_off_os" id="toggle_snap_on_off_os">Toggle Snap On/Off (os)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Toggle Snap On/Off</strong> toggles the snap. Be very careful using this. Connections between pins and nets (and nets to nets) depends on being exactly connected. Turning of the grid will almost guarantee that nets/pins do not connect.<br/>
   Before you translate a symbol using Edit/Symbol Translate, make sure the snap is on.<br/>
   When snap mode is off, the text &ldquo;Snap Off&rdquo; will appear in the lower, righthand corner.
  </p>
  
  </div>
  <!-- SECTION [111153-111604] -->
  <h3><a name="snap_grid_spacing..._os" id="snap_grid_spacing..._os">Snap Grid Spacing... (oS)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Snap Grid Spacing...</strong> brings up a dialog box which allows you to change the snap grid spacing (not the grid spacing). The units for this spacing are mils.<br/>
   Before you translate a symbol using Edit/Symbol Translate, make sure this spacing is set to 100.
  </p>
  
  </div>
  <!-- SECTION [111605-111908] -->
  <h3><a name="toggle_outline_box_oa" id="toggle_outline_box_oa">Toggle Outline/Box (oa)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Toggle Outline/Box</strong> toggles between drawing the outline of the current selection or just drawing a box when doing moves/copies/component and text places. The outline mode looks better, but tends to be significantly slower than using the box (bounding box) mode.
  </p>
  
  </div>
  <!-- SECTION [111909-112218] -->
  <h3><a name="toggle_net_rubberband_or" id="toggle_net_rubberband_or">Toggle Net/Rubberband (or)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Toggle Net/Rubberband</strong> .....????
  </p>
  
  </div>
  <!-- SECTION [112219-112302] -->
  <h3><a name="show_log_window_ol" id="show_log_window_ol">Show Log Window (ol)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Show Log Window</strong> displays the log window if it has been closed or disabled from being displayed when you start up <strong>gschem</strong>.
  </p>
  
  </div>
  <!-- SECTION [112303-112473] -->
  <h3><a name="show_coord_window..._oc" id="show_coord_window..._oc">Show Coord Window... (oc)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Options | Show Coord Window...</strong> displays a pop-up window that displays the coordinates of the mouse pointer on the schematic. Useful for accurately placing objects.
  </p>
  
  </div>
  <!-- SECTION [112474-112678] -->
  <h2><a name="help" id="help">Help</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [112679-112696] -->
  <h3><a name="about..._ha" id="about..._ha">About... (ha)</a></h3>
  <div class="level3">
  
  <p>
  Every <acronym title="Graphical User Interface">GUI</acronym> application needs an <strong>Help | About...</strong> feature, to display:
  </p>
  <ul>
  <li class="level1"><div class="li"> The application&rsquo;s name.</div>
  </li>
  <li class="level1"><div class="li"> The version of the software.</div>
  </li>
  <li class="level1"><div class="li"> The author&rsquo;s name(s) and how to contact.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [112697-112899] -->
  <h3><a name="manual..._hm" id="manual..._hm">Manual... (hm)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Help | Manual...</strong> brings up the &ldquo;gEDA/gaf Documention&rdquo; web-page installed on this computer. Very useful for accessing the various documentation available for the gEDA/gaf applications.
  </p>
  
  </div>
  <!-- SECTION [112900-113113] -->
  <h3><a name="hotkeys..._hh" id="hotkeys..._hh">Hotkeys... (hh)</a></h3>
  <div class="level3">
  
  <p>
  <strong>Help | Hotkeys...</strong> lists the current hotkeys (a.k.a., shortcuts, a.k.a., keyboard accellerators).
  </p>
  
  </div>
  <!-- SECTION [113114-113241] -->
  <h3><a name="component..._ho" id="component..._ho">Component... (Ho)</a></h3>
  <div class="level3">
  
  <p>
  If you select a component on the schematic, and select <strong>Help | Component...</strong>, <strong>gschem</strong> uses the gschemdoc script to do its best job finding some documentation appropriate for the component:
  </p>
  <ul>
  <li class="level1"><div class="li"> If the component&rsquo;s symbol included the <code>documentation=documentation_locator</code> attribute, this <acronym title="Uniform Resource Identifier">URI</acronym> is used to retreive the documentation. If the full <acronym title="Uniform Resource Identifier">URI</acronym> is given, the <acronym title="Uniform Resource Identifier">URI</acronym> on the internet is retrieved. If the <acronym title="Uniform Resource Identifier">URI</acronym> is not fully qualified, it is considered to be local to this computer, and is searched for and displayed.</div>
  </li>
  <li class="level1"><div class="li"> If the component&rsquo;s symbol does not include the <code>documentation=documentation_locator</code> attribute, a Google search is performed for <acronym title="Portable Document Format">PDF</acronym> documents, based on the <code>device=</code> attribute, the <code>value=</code> attribute, and the symbol basename.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [113242-114024] -->
  <h1><a name="appendix_a_--_heavy_vs_light_symbol_libraries" id="appendix_a_--_heavy_vs_light_symbol_libraries">Appendix A -- Heavy vs Light Symbol Libraries</a></h1>
  <div class="level1">
  
  <p>
  A short discussion of Light Symbol Libraries as the default for <strong>gschem</strong>, and the option to build your own Heavy Symbol Libraries.
  </p>
  
  </div>
  <!-- SECTION [114025-114218] -->
  <h1><a name="appendix_b_--_printing_schematics_and_symbols" id="appendix_b_--_printing_schematics_and_symbols">Appendix B -- Printing Schematics and Symbols</a></h1>
  <div class="level1">
  
  <p>
  To be supplied...
  </p>
  
  </div>
  <!-- SECTION [114219-114297] -->
  <h1><a name="appendix_c_--_writing_guile_scripts" id="appendix_c_--_writing_guile_scripts">Appendix C -- Writing guile Scripts</a></h1>
  <div class="level1">
  
  <p>
  To be supplied...
  </p>
  
  </div>
  <!-- SECTION [114298-114366] -->
  <h1><a name="appendix_d_--_i_want_to_build_a_printed_circuit_board" id="appendix_d_--_i_want_to_build_a_printed_circuit_board">Appendix D -- I Want To Build A Printed Circuit Board</a></h1>
  <div class="level1">
  
  <p>
  <strong>gschem</strong> is used for two primary design workflows:
  </p>
  <ul>
  <li class="level1"><div class="li"> Circuit design intended for production of Printed Circuit Boards (PCBs).</div>
  </li>
  <li class="level1"><div class="li"> Circuit design intended for simulation.</div>
  </li>
  </ul>
  
  <p>
   The following guidelines will assist you in developing quality designs intended for use by applications that support the creation of Printed Circuit Boards:
  </p>
  <ul>
  <li class="level1"><div class="li"> <span class="hilited">To be supplied...</span></div>
  </li>
  </ul>
  
  <p>
   The following on-line tutorials are an excellent method for the beginner to learn the gEDA Tools Suite design workflow resulting in a PCB:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html";  rel="nofollow">Bill Wilson's gschem warmup</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">Bill Wilson's gsch2pcb tutorial</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [114367-115156] -->
  <h1><a name="appendix_e_--_i_want_to_simulate_my_design" id="appendix_e_--_i_want_to_simulate_my_design">Appendix E -- I Want To Simulate My Design</a></h1>
  <div class="level1">
  
  <p>
  <strong>gschem</strong> is used for two primary design workflows:
  </p>
  <ul>
  <li class="level1"><div class="li"> Circuit design intended for production of Printed Circuit Boards.</div>
  </li>
  <li class="level1"><div class="li"> Circuit design intended for simulation.</div>
  </li>
  </ul>
  
  <p>
   The following guidelines will assist you in developing quality designs intended for simulation:
  </p>
  <ul>
  <li class="level1"><div class="li"> Discuss attributes appropriate for a SPICE model, and how these differ from attributes appropriate for a PCB.</div>
  </li>
  <li class="level1"><div class="li"> <span class="hilited">To be supplied...</span></div>
  </li>
  </ul>
  
  <p>
   The following on-line tutorials are an excellent method for the beginner to learn the gEDA Tools Suite design workflow resulting in a SPICE simulation:
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://www.brorson.com/gEDA/SPICE/t1.html"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/t1.html";  rel="nofollow">&quot;Circuit simulation using gEDA and SPICE -- HOWTO&quot; by Stuart Brorson</a></div>
  </li>
  <li class="level1"><div class="li"> <a href="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf"; class="urlextern" title="http://www-mdp.eng.cam.ac.uk/urop05/files/gedalib/starting_gEDA.pdf";  rel="nofollow">Starting with gEDA at the Cambridge University Engineering Department</a></div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [115157-116036] -->
  <h1><a name="appendix_f_--_change_gschemdoc_user-defined_preferences" id="appendix_f_--_change_gschemdoc_user-defined_preferences">Appendix F -- Change gschemdoc User-Defined Preferences</a></h1>
  <div class="level1">
  
  <p>
  As installed, the <strong>gschemdoc</strong> utility script is used by <strong>gschem</strong> to:
  </p>
  <ul>
  <li class="level1"><div class="li"> Display the &ldquo;gEDA/gaf Documentation&rdquo; (i.e., <strong>Help | Manual...</strong>)</div>
  </li>
  <li class="level1"><div class="li"> Display component documentation (i.e., <strong>Help | Component...</strong>)</div>
  </li>
  </ul>
  
  <p>
   The list of application launchers that <strong>gschemdoc</strong> uses are defined in the {binary-install-path}/bin/gschemdoc file: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">#
  # these may be changed to suit local preferences
  #
  CANDIDATE_BROWSER=&quot;galeon mozilla phoenix netscape netscape-navigator opera firefox konqueror&quot;
  CANDIDATE_PDFREADER=&quot;xpdf acroread ggv gv&quot;
  CANDIDATE_LOCATE=&quot;slocate locate&quot;</font></pre>
  </p>
  
  <p>
  To select a different application launcher, simply edit the {binary-install-path}/bin/gschemdoc file, find the above lines, and move your favorite application to the beginning of the list. For example, to use <strong>firefox</strong> as your preferred browser, move it to the beginning of the <strong>CANDIDATE_BROWSER=</strong> list, to use <strong>acroread</strong> (Adobe&rsquo;s Acrobat Reader) as your preferred <acronym title="Portable Document Format">PDF</acronym> reader, move it to the beginning of the <strong>CANDIDATE_PDFREADER=</strong> list, and to use <strong>locate</strong> as your preferred filesystem search utility, move it to the beginning of the <strong>CANDIDATE_LOCATE=</strong> list.
  </p>
  
  </div>
  <!-- SECTION [116037-117253] -->
  <h1><a name="appendix_g_--_breaking_a_large_symbol_into_smaller_symbols" id="appendix_g_--_breaking_a_large_symbol_into_smaller_symbols">Appendix G -- Breaking a Large Symbol Into Smaller Symbols</a></h1>
  <div class="level1">
  
  <p>
  To be supplied...
  </p>
  
  </div>
  <!-- SECTION [117254-117345] -->
  <h1><a name="appendix_h_--_definition_of_terms" id="appendix_h_--_definition_of_terms">Appendix H -- Definition of Terms</a></h1>
  <div class="level1">
  
  <p>
  Some terms used in the art of schematic capture:</p>
  <dl>
  <dt><span class='term'> <strong>attribute</strong></span></dt>
  <dd>A text item which is in the form <code>name=value</code>. It can be either unattached or attached.</dd>
  <dt><span class='term'> <strong>buffer</strong></span></dt>
  <dd>...</dd>
  <dt><span class='term'> <strong>component</strong></span></dt>
  <dd>Also know as <strong>part</strong>. The equivalent of an [electronics] device, as one may place on a printed circuit board. Components are instances of a <strong>symbol</strong> placed on a schematic.</dd>
  <dt><span class='term'> <strong>device</strong></span></dt>
  <dd>Also known as &ldquo;package&rdquo;. The equivalent of an [electronics] device, as one may place on a printed circuit board.</dd>
  <dt><span class='term'> <strong>dialog box</strong></span></dt>
  <dd>...</dd>
  <dt><span class='term'> <strong>embedded component</strong></span></dt>
  <dd>A component whose definition is saved as part of the schematic&rsquo;s file.</dd>
  <dt><span class='term'> <strong>footprint</strong></span></dt>
  <dd>Also known as a <strong>land pattern</strong>. The surface space occupied by a <strong>component</strong>/<strong>package</strong>/<strong>part</strong>.</dd>
  <dt><span class='term'> <strong>gEDA/gaf</strong></span></dt>
  <dd><strong>gschem</strong> is a component of the gEDA/gaf set of tools, which tend to integrate together in the development and maintenance of schematics and symbols. The term &ldquo;gaf&rdquo; stands for &ldquo;<em class="u">g</em>EDA <em class="u">a</em>nd <em class="u">f</em>riends&rdquo;).</dd>
  <dt><span class='term'> <strong>grip</strong></span></dt>
  <dd>...</dd>
  <dt><span class='term'> <strong>guile</strong></span></dt>
  <dd><a href="http://www.gnu.org/software/guile/"; class="urlextern" title="http://www.gnu.org/software/guile/";  rel="nofollow">GNU Guile</a> is an interpreter for Scheme, a version of Lisp.</dd>
  <dt><span class='term'> <strong>HDL</strong></span></dt>
  <dd>Hardware Description Language (e.g., VHDL, Verilog, etc.). Used to simulate or document a device.</dd>
  <dt><span class='term'> <strong>hierarchical</strong></span></dt>
  <dd>The concept that designs can contain nested levels of schematics, so that all the circuit doesn&rsquo;t need to be placed on a single sheet.</dd>
  <dt><span class='term'> <strong>land pattern</strong></span></dt>
  <dd>Also known as a <strong>footprint</strong>. The surface space occupied by a structure or device.</dd>
  <dt><span class='term'> <strong>library</strong></span></dt>
  <dd>A collection of symbols.</dd>
  <dt><span class='term'> <strong>line</strong></span></dt>
  <dd>A straight drawing element, connecting two points. On the schematic it has no electrical significance. In a symbol, a line is part of the symbol&rsquo;s graphic elements.</dd>
  <dt><span class='term'> <strong>model</strong></span></dt>
  <dd>A description of how a device behaves. Most often this is a SPICE model. The model is defined in <strong>gschem</strong>, but used in subsequent applications such as <strong>ngspice</strong>, <strong>gnucap</strong>, etc.</dd>
  <dt><span class='term'> <strong>net</strong></span></dt>
  <dd>A net connects two or more pins on a schematic, and is made up of segments. The net&rsquo;s equivalent is a &ldquo;wire&rdquo; or &ldquo;trace&rdquo; on the printed circuit board.</dd>
  <dt><span class='term'> <strong>object</strong></span></dt>
  <dd>A line, circle, pin, net, box, bus, text/attribute, or picture.</dd>
  <dt><span class='term'> <strong>package</strong></span></dt>
  <dd>Also known as <strong>device</strong>. The equivalent of an [electronics] device, as one may place on a printed circuit board.</dd>
  <dt><span class='term'> <strong>page</strong></span></dt>
  <dd>Also known as a schematic&rsquo;s <strong>sheet</strong>.</dd>
  <dt><span class='term'> <strong>part</strong></span></dt>
  <dd> Also know as <strong>component</strong>. The equivalent of an [electronics] device, as one may place on a printed circuit board.</dd>
  <dt><span class='term'> <strong>project</strong></span></dt>
  <dd>A collection of schematics, custom symbols, models, documentation, etc.</dd>
  <dt><span class='term'> <strong>segment</strong></span></dt>
  <dd>Part of a net. A segment has two end-points, or &ldquo;grips&rdquo;.</dd>
  <dt><span class='term'> <strong>schematic</strong></span></dt>
  <dd>A <strong>page</strong>/<strong>sheet</strong> with electronics symbols, text, and drawing elements (i.e., lines, circles, boxes, etc.) representing a diagram of an electrical or mechanical system.</dd>
  <dt><span class='term'> <strong>series</strong></span></dt>
  <dd>A collection of schematics which share a common basename (e.g., schematic_1.sch, schematic_2.sch, schematic_3.sch, etc.). The series basename ties schematics together.</dd>
  <dt><span class='term'> <strong>slotted device</strong></span></dt>
  <dd>Also known as a <strong>slotted package</strong>. A physical [electronics] device consisting of multiple identical components (e.g., the 7400 quad NAND device consists of 4 identical NAND gates).</dd>
  <dt><span class='term'> <strong>source</strong></span></dt>
  <dd>A schematic, HDL code, or model which implements, describes, or documents some aspect of the project.</dd>
  <dt><span class='term'> <strong>symbol</strong></span></dt>
  <dd>A collection of <strong>objects</strong>. The objects may have <strong>attributes</strong> attatched (i.e., associated) with them. There may also be <strong>attributes</strong> attached (i.e., associated) to the <strong>symbol</strong> itself (i.e., not specifically associated with an object).</dd>
  <dt><span class='term'> <strong>sheet</strong></span></dt>
  <dd>Also known as a schematic&rsquo;s <strong>page</strong>.</dd>
  <dt><span class='term'> <strong>trace</strong></span></dt>
  <dd>The equivalent of a wire on a printed circuit board.</dd>
  <dt><span class='term'> <strong>window</strong></span></dt>
  <dd>...</dd>
  <dt><span class='term'> <strong>workflow</strong></span></dt>
  <dd>The process of designing. Usually includes continuous review and re-design, until it works. In the gEDA Tools Suite design workflow, multiple applications are used. One application typically is followed by another. The flow of data collected and how this data effects the design is considered the workflow.</dd>
  </dl>
  <p>~~DISCUSSION~~ 
  </p>
  
  </div>
  <!-- SECTION [117346-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_gsymcheck_mp.html
  
  Index: geda_gsymcheck_mp.html
  ===================================================================
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  <h1><a name="gsymcheck_man-page" id="gsymcheck_man-page">gsymcheck man-page</a></h1>
  <div class="level1">
  <pre class="code">gsymcheck(1)			   20031231			  gsymcheck(1)
  
  
  
  NAME
         gsymcheck - gEDA/gaf Symbol Checker
  
  SYNOPSIS
         gnetlist [-h] [-v] [-q] symbol1 [... symbolN]
  
  DESCRIPTION
         gsymcheck  is  a	 symbol	 checker for gEDA.  Eventually there will be a
         list of checks performed on the symbols listed here.
  
  
  OPTIONS
         gsymcheck accepts the following options:
  
         -q      Quiet mode on.  This mode  turns	 off  all  warnings/notes/mes-
  	       sages. (optional)
  
         -v      Verbose	mode  1.   This	 mode  will  show  all	error messages
  	       (optional)
  
         -vv     Verbose mode 2.	This mode will show all error and warning mes-
  	       sages (optional)
  
         -vvv    Verbose	mode  2.   This mode will show all error, warning, and
  	       info messages (optional)
  
         -h      Usage summary / gsymcheck help
  
         symbol1 [... symbolN]
  	       At least one symbol file must be specified.  If	multiple  sym-
  	       bols  are  specified  then  they	 are  sequentially read in and
  	       checked.	 It is important that the schematic(s) follow all  the
  	       options (ie last).
  
  
  EXAMPLES
         Examples to be listed here eventually
  
  
  ENVIRONMENT
         No environment variables are used.
  
  
  AUTHOR
         Ales Hvezda and many others
  
  
  SEE ALSO
         gschem(1), gnetlist(1)
  
  COPYRIGHT
         Copyright Â©  1999-2004 Ales Hvezda
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  
  Version			      December 31st, 2003		  gsymcheck(1)
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_gtkwave_lxt2miner_mp.html
  
  Index: geda_gtkwave_lxt2miner_mp.html
  ===================================================================
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  <h1><a name="data_mining_of_lxt2_files_lxt2miner" id="data_mining_of_lxt2_files_lxt2miner">Data mining of LXT2 files (lxt2miner)</a></h1>
  <div class="level1">
  <pre class="code">LXT2MINER(1)		     Dumpfile Data Mining		  LXT2MINER(1)
  
  
  
  NAME
         lxt2miner - Data mining of LXT2 files
  
  SYNTAX
         lxt2miner [option]... [LXT2FILE]
  
  DESCRIPTION
         Mines  LXT2  files  for specific data values and generates gtkwave save
         files to stdout for future reload.
  
  OPTIONS
         -d,--dumpfile &lt;filename&gt;
  	      Specify LXT2 input dumpfile.
  
         -m,--match &lt;filename&gt;
  	      Specifies &quot;bitwise&quot; match data (binary, real, string)
  
         -x,--hex &lt;value&gt;
  	      Specifies hexadecimal match data that will automatically be con-
  	      verted to binary for searches
  
         -n,--namesonly
  	      Indicates	 that  only  facnames  should  be printed in a gtkwave
  	      savefile compatible format.  By doing this, the file can be used
  	      to specify which traces are to be imported into gtkwave.
  
         -h,--help
  	      Show help screen.
  
  EXAMPLES
         lxt2miner dumpfile.lxt2 --match 20470000 -n
  
         This attempts to match the hex value 20470000 across all facilities and
         when the value is encountered, the facname only is printed to stdout in
         order to generate a gtkwave compatible save file.
  
  LIMITATIONS
         lxt2miner  only prints the first time a value is encountered for a spe-
         cific net.  This is done in order to cut down on	 the  size  of	output
         files  and to aid in following data such as addresses through a simula-
         tion model.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         vztminer(1) vzt2vcd(1) lxt2vcd(1) vcd2lxt2(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.64			  LXT2MINER(1)
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  <h1><a name="coverts_lxt2_files_to_vcd_lxt2vcd" id="coverts_lxt2_files_to_vcd_lxt2vcd">Coverts LXT2 files to VCD (lxt2vcd)</a></h1>
  <div class="level1">
  <pre class="code">LXT2VCD(1)		      Filetype Conversion		    LXT2VCD(1)
  
  
  
  NAME
         lxt2vcd - Coverts LXT2 files to VCD
  
  SYNTAX
         lxt2vcd &lt;filename&gt;
  
  DESCRIPTION
         Converts	 LXT2  files to VCD files on stdout.  Note that &quot;regular&quot; LXT2
         files will convert to VCD files with monotonically increasing time val-
         ues.   LXT2  files which are dumped with the &quot;partial&quot; option (to speed
         up access in wave viewers) will dump with monotonically increasing time
         values  per  2k	block of nets.	This may be fixed in later versions of
         lxt2vcd.
  
  EXAMPLES
         To run this program the standard way type:
  
         lxt2vcd filename.lxt
  	      The VCD conversion is emitted to stdout.
  
  LIMITATIONS
         lxt2vcd does not re-create glitches as  these  are  coalesced  together
         into one value change during the writing of the LXT2 file.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         vcd2lxt2(1) vcd2lxt(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.34			    LXT2VCD(1)</pre>
  
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  <h1><a name="visualization_tool_for_vcd_lxt_and_vzt_files_gtkwave" id="visualization_tool_for_vcd_lxt_and_vzt_files_gtkwave">Visualization tool for VCD, LXT, and VZT files (gtkwave)</a></h1>
  <div class="level1">
  <pre class="code">GTKWAVE(1)		    Simulation Wave Viewer		    GTKWAVE(1)
  
  
  
  NAME
         gtkwave - Visualization tool for VCD, LXT, and VZT files
  
  SYNTAX
         gtkwave [option]... [DUMPFILE] [SAVEFILE] [RCFILE]
  
  
  DESCRIPTION
         Visualization  tool  for	 VCD,  LXT, LXT2, and VZT.  VCD is an industry
         standard simulation dump format. LXT, LXT2, and VZT have been  designed
         specifically for use with gtkwave.  Native dumpers exist in Icarus Ver-
         ilog for the LXT formats so conversion with vcd2lxt(1)  or  vcd2lxt2(1)
         is  not	necessary to take direct advantage of LXT with that simulator.
         AET2 files can also be processed provided that  libae2rw	 is  available
         but this is only of interest to people who use IBM EDA toolsets.
  
  OPTIONS
         -n,--nocli &lt;directory name&gt;
  	      Use file requester for dumpfile name
  
         -f,--dump &lt;filename&gt;
  	      Specify dumpfile name.
  
         -r,--rcfile &lt;filename&gt;
  	      Specify override .gtkwaverc filename.
  
         -i,--indirect &lt;filename&gt;
  	      Specify  indirect facs file name.	 The file contains a series of
  	      regular expressions used to limit what signals can  be  browsed.
  	      Signal  names which match any of the regular expressions will be
  	      viewable.	 Typically, indirect files are used to	reduce	memory
  	      requirements  for	 extremely large models containing millions of
  	      facilities or to strip  out  top-level  hierarchy	 clutter  from
  	      BugSpray	models.	  This feature is only available with the AET2
  	      loader.
  
         -l,--logfile &lt;filename&gt;
  	      Specify simulation logfile name.	Multiple logfiles may be spec-
  	      ified  by	 preceeding  each with the command flag.  By selecting
  	      the numbers in the text widget, the marker will immediately zoom
  	      to the specific time value.
  
         -d,--defaultskip
  	      If  there is not a .gtkwaverc file in the home directory or cur-
  	      rent directory and it is not explicitly specified on the command
  	      line,  when  this option is enabled, do not use an implicit con-
  	      figuration file and instead default  to  the  old	 &quot;whitescreen&quot;
  	      behavior.
  
         -s,--start &lt;time&gt;
  	      Specify start time for LXT2/VZT block skip.
  
         -e,--end &lt;time&gt;
  	      Specify end time for LXT2/VZT block skip.
  
         -c,--cpu &lt;numcpus&gt;
  	      Specify  number  of CPUs available for parallelizable ops (e.g.,
  	      block prefetching on VZT reads).
  
         -v,--vcd
  	      Use stdin as a VCD dumpfile.
  
         -V,--version
  	      Display version banner then exit.
  
         -h,--help
  	      Display help then exit.
  
         -x,--exit
  	      Exit after loading trace (for loader benchmarking).
  
  FILES
         ~/.gtkwaverc
  
  
  EXAMPLES
         To run this program the standard way type:
  	      gtkwave dumpfile.vcd
  
         Alternatively you can run it with a save file as:
  	      gtkwave dumpfile.vcd dumpfile.sav
  
         Command line options are not necessary for representing	the  dumpfile,
         savefile, and rcfile names.  They are merely provided to allow specify-
         ing them out of order.  Note that on non-glibc systems, the  long  com-
         mand  line  options  will not be available and that the short ones will
         have to be used instead.
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         lxt2vcd(1) vcd2lxt(1) vcd2lxt2(1) vzt2vcd(1) vcd2vzt(1)
  
  
  
  Anthony Bybell			    1.3.70			    GTKWAVE(1)</pre>
  
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  <h1><a name="coverts_mvlsim_aet_files_to_lxt_mvl2lxt" id="coverts_mvlsim_aet_files_to_lxt_mvl2lxt">Coverts MVLSIM AET files to LXT (mvl2lxt)</a></h1>
  <div class="level1">
  <pre class="code">MVL2LXT(1)		      Filetype Conversion		    MVL2LXT(1)
  
  
  
  NAME
         mvl2lxt - Coverts MVLSIM AET files to LXT
  
  SYNTAX
         mvl2lxt &lt;filename.aet&gt; &lt;filename.lxt&gt;
  
  DESCRIPTION
         Converts	 AET  files  to LXT.  This is experimental as it is not a com-
         plete implementation and is not intended for general use.
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         tex2vcd(1) mvl2vcd(1) lxt2vcd(1) vcd2lxt2(1) vcd2lxt(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.34			    MVL2LXT(1)</pre>
  
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  <h1><a name="coverts_mvlsim_aet_files_to_vcd_mvl2vcd" id="coverts_mvlsim_aet_files_to_vcd_mvl2vcd">Coverts MVLSIM AET files to VCD (mvl2vcd)</a></h1>
  <div class="level1">
  <pre class="code">MVL2VCD(1)		      Filetype Conversion		    MVL2VCD(1)
  
  
  
  NAME
         mvl2vcd - Coverts MVLSIM AET files to VCD
  
  SYNTAX
         mvl2vcd &lt;filename.aet&gt;
  
  DESCRIPTION
         Converts AET files to VCD on stdout.  This is experimental as it is not
         a complete implementation and is not intended for general use.
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         tex2vcd(1) mvl2lxt(1) lxt2vcd(1) vcd2lxt2(1) vcd2lxt(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.34			    MVL2VCD(1)
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  <h1><a name="coverts_texsim_aet_files_to_vcd_tex2vcd" id="coverts_texsim_aet_files_to_vcd_tex2vcd">Coverts TEXSIM AET files to VCD (tex2vcd)</a></h1>
  <div class="level1">
  <pre class="code">TEX2VCD(1)		      Filetype Conversion		    TEX2VCD(1)
  
  
  
  NAME
         tex2vcd - Coverts TEXSIM AET files to VCD
  
  SYNTAX
         mvl2vcd &lt;filename.aet&gt;
  
  DESCRIPTION
         Converts AET files to VCD on stdout.  This is experimental as it is not
         a complete implementation and is not intended for general use.
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         mvl2vcd(1) mvl2lxt(1) lxt2vcd(1) vcd2lxt2(1) vcd2lxt(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.34			    TEX2VCD(1)</pre>
  
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  <h1><a name="converts_tla_to_vcd_or_lst_files_tla2vcd" id="converts_tla_to_vcd_or_lst_files_tla2vcd">Converts TLA to VCD or LST files (tla2vcd)</a></h1>
  <div class="level1">
  <pre class="code">TLA2VCD(1)	       Tektronix File Format Conversion		    TLA2VCD(1)
  
  
  
  NAME
         tla2vcd - Converts TLA to VCD or LST files
  
  SYNTAX
         tla2vcd [option]... TLAFILE [[TLAFILE]...]
  
  
  DESCRIPTION
         Converts	 TLA files from Tektronix logic analyzers to VCD or LST files.
         Conversion to VCD allows viewing in tools such as  gtkwave(1).
  
  OPTIONS
         -t     Generate text LST file instead of VCD file
  
         -l     List the available channels/groups and exit
  
         -s  &lt;signal_list&gt;
  	      Select signals from regular expression list
  
         -a     All channels
  
         -m     Append MagniVu info (only in listing mode)
  
         -z     Compress output
  
         -v     Verbose
  
  
  AUTHORS
         Emil
  
  SEE ALSO
         lxt2vcd(1) vzt2vcd(1) gtkwave(1)
  
  
  
  Emil				      1.0			    TLA2VCD(1)</pre>
  
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  <h1><a name="converts_vcd_files_to_lxt2_files_vcd2lxt2" id="converts_vcd_files_to_lxt2_files_vcd2lxt2">Converts VCD files to LXT2 files (vcd2lxt2)</a></h1>
  <div class="level1">
  <pre class="code">VCD2LXT2(1)		      Filetype Conversion		   VCD2LXT2(1)
  
  
  
  NAME
         vcd2lxt2 - Converts VCD files to LXT2 files
  
  SYNTAX
         vcd2lxt2 [option]... [VCDFILE] [LXTFILE]
  
  DESCRIPTION
         Converts VCD files to LXT2 files.
  
  OPTIONS
         -v,--vcdname &lt;filename&gt;
  	      Specify VCD input filename.
  
         -l,--lxtname &lt;filename&gt;
  	      Specify LXT2 output filename.
  
         -d,--depth &lt;value&gt;
  	      Specify 0..9 gzip compression depth, default is 4.
  
         -m,--maxgranule &lt;value&gt;
  	      Specify number of granules per section, default is 8.  One gran-
  	      ule is equal to 32 timsteps.
  
         -b,--break &lt;value&gt;
  	      Specify break size (default = 0 = off).  When the break size  is
  	      exceeded, the LXT2 dumper will dump all state information at the
  	      next convenient granule plus dictionary boundary.
  
         -p,--partialmode &lt;mode&gt;
  	      Specify partial zip mode 0 = monolithic, 1 = separation.	 Using
  	      a	 value of 1 expands LXT2 filesize but provides fast access for
  	      very large traces.  Note that the default mode is neither	 mono-
  	      lithic nor separation: partial zip is disabled.
  
         -c,--checkpoint &lt;mode&gt;
  	      Specify  checkpoint  mode.   0  is on which is default, and 1 is
  	      off.  This is disabled when the break size is active.
  
         -h,--help
  	      Show help screen.
  
  
  
         EXAMPLES
  
         Note that you should specify  dumpfile.vcd  directly  or	 use  &quot;-&quot;  for
         stdin.
  
         vcd2lxt dumpfile.vcd dumpfile.lxt --depth 9 --break 1073741824
  	      This  sets the compression level to 9 and sets the break size to
  	      1GB.
  
         vcd2lxt dumpfile.vcd dumpfile.lxt --depth 9 --maxgranule 256
  	      Allows more granules per section which allows for	 greater  com-
  	      pression.
  
  LIMITATIONS
         vcd2lxt2	 does  not store glitches as these are coalesced together into
         one value change during the writing of the LXT2 file.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         lxt2vcd(1) vcd2lxt2(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.42			   VCD2LXT2(1)</pre>
  
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  <h1><a name="converts_vcd_files_to_interlaced_or_linear_lxt_files_vcd2lxt" id="converts_vcd_files_to_interlaced_or_linear_lxt_files_vcd2lxt">Converts VCD files to interlaced or linear LXT files (vcd2lxt)</a></h1>
  <div class="level1">
  <pre class="code">VCD2LXT(1)		      Filetype Conversion		    VCD2LXT(1)
  
  
  
  NAME
         vcd2lxt - Converts VCD files to interlaced or linear LXT files
  
  SYNTAX
         vcd2lxt [VCDFILE] [LXTFILE] [option]...
  
  DESCRIPTION
         Converts	 VCD  files  to interlaced or linear LXT files.	 Noncompressed
         interlaced files will provide the fastest  access,  linear  files  will
         provide the slowest yet have the greatest compression ratios.
  
  OPTIONS
         -stats Prints  out  statistics  on  all nets in VCD file in addition to
  	      performing the conversion.
  
         -clockpack
  	      Apply two-way subtraction algorithm in order  to	identify  nets
  	      whose   value   changes	by  a  constant	 XOR  or  whose	 value
  	      increases/decreases by a constant amount per  constant  unit  of
  	      time.   This  option  can	 reduce	 dumpfile size dramatically as
  	      value changes can be represented	by  an	equation  rather  than
  	      explicitly as a triple of time, net, and value.
  
         -chgpack
  	      Emit data to file after being filtered through zlib (gzip).
  
         -linear
  	      Write  out  LXT  in &quot;linear&quot; format with no backpointers.	 These
  	      are re-generated during initialization  in  gtkwave.   Addition-
  	      ally, use libbz2 (bzip2) as the compression filter.
  
         -dictpack &lt;size&gt;
  	      Store  value  changes  greater  than or equal to size bits as an
  	      index into a dictionary.	Experimentation shows that a value  of
  	      18 is optimal for most cases.
  
  EXAMPLES
         Note  that  you	should	specify	 dumpfile.vcd  directly or use &quot;-&quot; for
         stdin.
  
         vcd2lxt dumpfile.vcd dumpfile.lxt -clockpack -chgpack -dictpack 18
  	      This turns on clock packing, zlib compression, and  enables  the
  	      dictionary  encoding.   Note  that using no options writes out a
  	      normal LXT file.
  
         vcd2lxt dumpfile.vcd dumpfile.lxt -clockpack -linear -dictpack 18
  	      Uses linear mode for even smaller files.
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         lxt2vcd(1) vcd2lxt2(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.34			    VCD2LXT(1)</pre>
  
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  <h1><a name="converts_vcd_files_to_vzt_files_vcd2vzt" id="converts_vcd_files_to_vzt_files_vcd2vzt">Converts VCD files to VZT files (vcd2vzt)</a></h1>
  <div class="level1">
  <pre class="code">VCD2VZT(1)		      Filetype Conversion		    VCD2VZT(1)
  
  
  
  NAME
         vcd2vzt - Converts VCD files to VZT files
  
  SYNTAX
         vcd2vzt [option]... [VCDFILE] [VZTFILE]
  
  DESCRIPTION
         Converts VCD files to VZT files.
  
  OPTIONS
         -v,--vcdname &lt;filename&gt;
  	      Specify VCD input filename.
  
         -l,--vztname &lt;filename&gt;
  	      Specify VZT output filename.
  
         -d,--depth &lt;value&gt;
  	      Specify 0..9 gzip compression depth, default is 4.
  
         -m,--maxgranule &lt;value&gt;
  	      Specify number of granules per section, default is 8.  One gran-
  	      ule is equal to 32 timesteps.
  
         -b,--break &lt;value&gt;
  	      Specify break size (default = 0 = off).  When the break size  is
  	      exceeded,	 the VZT dumper will dump all state information at the
  	      next convenient granule plus dictionary boundary.
  
         -z,--ziptype &lt;value&gt;
  	      Specify zip type (default = 0 gzip, 1 = bzip2).  This allows you
  	      to  override  the	 default  compression  algorithm to use a more
  	      effective one at the expense  of	greater	 runtime.   Note  that
  	      bzip2  does not decompress as fast as gzip so the viewer will be
  	      about two times slower when decompressing blocks.
  
         -t,--twostate
  	      Forces MVL2 twostate mode (default is MVL4).  When enabled,  the
  	      trace will only store 0/1 values for binary facilities.  This is
  	      useful for functional simulation and will speed  up  dumping  as
  	      well as make traces somewhat smaller.
  
         -r, --rle
  	      Uses  an bitwise RLE compression on the value table.  Default is
  	      off.  When enabled, this causes  the  trace  data	 table	to  be
  	      stored  using an alternate representation which can improve com-
  	      pression in many cases.
  
         -h,--help
  	      Show help screen.
  
  
  
         EXAMPLES
  
         Note that you should specify  dumpfile.vcd  directly  or	 use  &quot;-&quot;  for
         stdin.
  
         vcd2vzt dumpfile.vcd dumpfile.lxt --depth 9 --break 1073741824
  	      This  sets the compression level to 9 and sets the break size to
  	      1GB.
  
         vcd2vzt dumpfile.vcd dumpfile.lxt --depth 9 --maxgranule 512
  	      Allows more granules per section which allows for	 greater  com-
  	      pression at the expense of memory usage.
  
  LIMITATIONS
         vcd2vzt	does  not  store glitches as these are coalesced together into
         one value change during the writing of the VZT file.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         vzt2vcd(1) lxt2vcd(1) vcd2lxt2(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.48			    VCD2VZT(1)</pre>
  
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  <h1><a name="coverts_vzt_files_to_vcd_vzt2vcd" id="coverts_vzt_files_to_vcd_vzt2vcd">Coverts VZT files to VCD (vzt2vcd)</a></h1>
  <div class="level1">
  <pre class="code">VZT2VCD(1)		      Filetype Conversion		    VZT2VCD(1)
  
  
  
  NAME
         vzt2vcd - Coverts VZT files to VCD
  
  SYNTAX
         vzt2vcd &lt;filename&gt;
  
  DESCRIPTION
         Converts VZT files to VCD files on stdout.
  
  EXAMPLES
         To run this program the standard way type:
  
         vzt2vcd filename.vzt
  	      The VCD conversion is emitted to stdout.
  
  LIMITATIONS
         vzt2vcd	does  not  re-create  glitches as these are coalesced together
         into one value change during the writing of the VZT file.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         vcd2lxt2(1) vcd2lxt(1) lxt2vcd(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.44			    VZT2VCD(1)</pre>
  
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  <h1><a name="data_mining_of_vzt_files_vztminer" id="data_mining_of_vzt_files_vztminer">Data mining of VZT files (vztminer)</a></h1>
  <div class="level1">
  <pre class="code">VZTMINER(1)		     Dumpfile Data Mining		   VZTMINER(1)
  
  
  
  NAME
         vztminer - Data mining of VZT files
  
  SYNTAX
         vztminer [option]... [VZTFILE]
  
  DESCRIPTION
         Mines  VZT  files  for  specific data values and generates gtkwave save
         files to stdout for future reload.
  
  OPTIONS
         -d,--dumpfile &lt;filename&gt;
  	      Specify VZT input dumpfile.
  
         -m,--match &lt;filename&gt;
  	      Specifies &quot;bitwise&quot; match data (binary, real, string)
  
         -x,--hex &lt;value&gt;
  	      Specifies hexadecimal match data that will automatically be con-
  	      verted to binary for searches
  
         -n,--namesonly
  	      Indicates	 that  only  facnames  should  be printed in a gtkwave
  	      savefile compatible format.  By doing this, the file can be used
  	      to specify which traces are to be imported into gtkwave.
  
         -h,--help
  	      Show help screen.
  
  EXAMPLES
         vztminer dumpfile.vzt --match 20470000 -n
  
         This attempts to match the hex value 20470000 across all facilities and
         when the value is encountered, the facname only is printed to stdout in
         order to generate a gtkwave compatible save file.
  
  LIMITATIONS
         vztminer	 only  prints the first time a value is encountered for a spe-
         cific net.  This is done in order to cut down on	 the  size  of	output
         files  and to aid in following data such as addresses through a simula-
         tion model.
  
  
  AUTHORS
         Anthony Bybell &lt;bybell@xxxxxxxxx&gt;
  
  SEE ALSO
         lxt2miner(1) vzt2vcd(1) lxt2vcd(1) vcd2lxt2(1) gtkwave(1)
  
  
  
  Anthony Bybell			    1.3.64			   VZTMINER(1)</pre>
  
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  <h1><a name="hooks_scheme_extension_howto" id="hooks_scheme_extension_howto">Hooks/Scheme Extension HOWTO</a></h1>
  <div class="level1">
  <pre class="code">gEDA - GPL Electronic Design Automation
  
  HOOKS AND SCHEME EXTENSION IN GSCHEM
  ==================================== 
  
  Copyright (C) 2000 Stefan Petersen
  
  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.
  
  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.
  
  You should have received a copy of the GNU General Public License
  along with this program; if not, write to the Free Software
  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  
  
  Introduction
  ------------
  gschem has a scheme interpreter (called Guile) built in. Though not 
  complete, there are extensions to this interpreter to get access to 
  different parts of the schematic.
  
  There are a couple of other scheme extensions available that will not be 
  described here. They belong mainly to rc-files (resource files in 
  gEDA programs are really scheme scripts) and to the keymapping system 
  (described in separate keymapping documentation).
  
  The rest I will try to describe here. 
  
  
  Scheme functions
  ----------------
  There are two function available for handling attributes in the schematic.
  
  * get-attribute-name-value
  Inparameter  : an attribute
  Outparameter : a pair with the name of the attribute as string in the 
  	       car element and the value of the attribute in the cdr 
  	       element.
  Description  : Simply an accessor to the information hidden in the type
  	       attribute. The functionality of this is placed in libgeda
  	       since the C-type ATTRIBUTE is defined there.
  
  * set-attribute-value!
  Inparameter  : an attribute and a string.
  Outparameter : undefined.
  Description  : Sets a new value to an attribute. The attribute must 
                 be defined, the function can't create a new attribute. 
  	       Defined both in gschem and libgeda, mainly because 
  	       where different variables and information are available.
  
  
  Hooks
  -----
  Hooks are a way to define functions that will be called during different
  part of a programs execution. In gschem there are (currently) three 
  different hooks available:
  * add-component-hook
  * copy-component-hook
  * move-component-hook
  
  As their name indicate, they are called at different occasions. When 
  you add a component add-component-hook is called, etc.
  
  To add a function to be called you simply use the Guile funtion add-hook!.
  An example; to run the function auto-uref when you add a component you
  simply add the following line, preferrably in ${HOME}/.gEDA/gschemrc:
  (add-hook! add-component-hook auto-uref)
  
  The function to be called from a hook (for example auto-uref above) has 
  to accept one parameter, a list of attributes.
  
  A small example that prints all attributes on a component to be placed:
  
  (define (print-all-attributes attribute-list)
    (foreach (lambda (attribute) (display attribute)) attribute-list))
  
  
  How to use this
  ---------------
  The most complete example utilizing all of the above functions are in fact
  the auto-uref scheme script that currently is part of the gschem distribution.
  You can find it &lt;where gschem is installed&gt;/share/gEDA/scheme/auto-uref.scm.
  Uninstalled it's available at gschem/scheme/auto-uref.scm
  
  All components have a reference designator that must be unique so 
  gnetlist can handle it properly. By automatically assigning a number
  to each instance of a component when you place and copy it, you can 
  simplify the naming operation.
  
  All components has, per default, an uref attribute, for example uref=R?. 
  The letter varies with component type. The auto-uref script enumerates 
  uref based on what prefix the component has and assigns a number. 
  
  For example, the first component you place has per default uref=U? gets 
  the attribute uref=U1. Next component with uref=U? gets uref=U2 and so on.
  
  To be able to use the auto-uref script you simply add two lines in
  ${HOME}/.gEDA/gschemrc. They are:
  (load &quot;&lt;where gschem is installed&gt;/share/gEDA/scheme/auto-uref.scm&quot;)
  (add-hook! add-component-hook auto-uref)
  
  If you want auto enumeration to work when you copy the component too, you 
  simply add the following line:
  (add-hook! copy-component-hook auto-uref)
  
  Good luck!
  
  </pre>
  
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  <h1><a name="icarus_attribute_naming_conventions" id="icarus_attribute_naming_conventions">Icarus Attribute Naming Conventions</a></h1>
  <div class="level1">
  <pre class="code">ATTRIBUTE NAMING CONVENTIONS
  
  Attributes that are specific to Icarus Verilog, and are intended to be
  of use to programmers, start with the prefix &quot;ivl_&quot;.
  
  Attributes with the &quot;_ivl_&quot; prefix are set aside for internal
  use. They may be generated internally by the compiler. They need not
  be documented here.
  
  ATTRIBUTES TO CONTROL SYNTHESIS
  
  The following is a summary of Verilog attributes that Icarus Verilog
  understands within Verilog source files to control synthesis
  behavior. This section documents generic synthesis attributes. For
  target specific attributes, see target specific documentation.
  
  These attributes only effect the behavior of the synthesizer. For
  example, the ivl_combinational will not generate an error message
  if the Verilog is being compiled for simulation. (It may generate a
  warning.)
  
  
  * Attributes for &quot;always&quot; and &quot;initial&quot; statements
  
  (* ivl_combinational *)
  
      This attribute tells the compiler that the statement models
      combinational logic. If the compiler finds that it cannot make
      combinational logic out of a marked always statement, it will
      report an error.
  
      This attribute can be used to prevent accidentally inferring
      latches or flip-flops where the user intended combinational
      logic.
  
  (* ivl_synthesis_on *)
  
      This attribute tells the compiler that the marked always statement
      is synthesizable. The compiler will attempt to synthesize the
      code in the marked &quot;always&quot; statement. If it cannot in any way
      synthesize it, then it will report an error.
  
  (* ivl_synthesis_off *)
  
      If this value is attached to an &quot;always&quot; statement, then the
      compiler will *not* synthesize the &quot;always&quot; statement. This can be
      used, for example, to mark embedded test bench code.
  
  
  * Attributes for modules
  
  (* ivl_synthesis_cell *)
  
      If this value is attached to a module during synthesis, that
      module will be considered a target architecture primitive, and
      its interior will not be synthesized further.  The module can
      therefore hold a model for simulation purposes.
  
  
  * Attributes for signals (wire/reg/integer/tri/etc.)
  
  (* PAD = &quot;&lt;pad assignment list&gt;&quot; *)
  
      If this attribute is attached to a signal that happens to be a
      root module port, then targets that support it will use the string
      value as a list of pin assignments for the port/signal. The format
      is a comma separated list of location tokens, with the format of
      the token itself defined by the back-end tools in use.
  
  * Other Attributes
  
  [ none defined yet ]
  
  
  MISC
  
  (* _ivl_schedule_push *)
  
      If this attribute is attached to a thread object (always or
      initial statement) then the vvp code generator will generate code
      that causes the scheduler to push this thread at compile time. The
      compiler may internally add this attribute to always statements if
      it detects that it is combinational. This helps resolve time-0
      races.</pre>
  
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  <h1><a name="icarus_verilog_extensions" id="icarus_verilog_extensions">Icarus Verilog Extensions</a></h1>
  <div class="level1">
  <pre class="code">Icarus Verilog Extensions
  
  Icarus Verilog supports certain extensions to the baseline IEEE1364
  standard. Some of these are picked from extended variants of the
  language, such as SystemVerilog, and some are expressions of internal
  behavior of Icarus Verilog, made available as a tool debugging aid.
  
  * Builtin System Functions
  
  ** Extended Verilog Data Types
  
  This feature is turned off if the generation flag &quot;-g&quot; is set to other
  then the default &quot;2x&quot;.  For example, &quot;iverilog -g2x&quot; enables extended
  data types, and &quot;iverilog -g2&quot; disables them.
  
  Icarus Verilog adds support for extended data types. This extended
  type syntax is based on a proposal by Cadence Design Systems,
  originally as an update to the IEEE1364. That original proposal has
  apparently been absorbed by the IEEE1800 SystemVerilog
  standard. Icarus Verilog currently only takes the new primitive types
  from the proposal.
  
  Extended data types separates the concept of net/variable from the
  data type. Both nets and variables can declared with any data
  type. The primitive types available are:
  
      logic  - The familiar 0, 1, x and z, optionally with strength.
      bool   - Limited to only 0 and 1
      real   - 64bit real values
  
  Nets with logic type may have multiple drivers with strength, and the
  value is resolved the usual way. Only logic values may be driven to
  logic nets, so bool values driven onto logic nets are implicitly
  converted to logic.
  
  Nets with any other type may not have multiple drivers. The compiler
  should detect the multiple drivers and report an error.
  
  - Declarations
  
  The declaration of a net is extended to include the type of the wire,
  with the syntax:
  
      wire &lt;type&gt; &lt;wire-assignment-list&gt;... ;
  
  The &lt;type&gt;, if omitted, is taken to be logic. The &quot;wire&quot; can be any of
  the net keywords. Wires can be logic, bool, real, or vectors of logic
  or bool. Some valid examples:
  
      wire real foo = 1.0;
      tri logic bus[31:0];
      wire bool addr[23:0];
      ... and so on.
  
  The declarations of variables is similar. The &quot;reg&quot; keyword is used to
  specify that this is a variable. Variables can have the same data
  types as nets.
  
  - Ports
  
  Module and task ports in standard verilog are restricted to logic
  types. This extension removes that restriction, allowing any type to
  pass through the port consistent with the continuous assignment
  connectivity that is implied by the type.
  
  - Expressions
  
  Expressions in the face of real values is covered by the baseline
  Verilog standard.
  
  The bool type supports the same operators as the logic type, with the
  obvious differences imposed by the limited domain.
  
  Comparison operators (not case compare) return logic if either of
  their operands is logic. If both are bool or real (including mix of
  bool and real) then the result is bool. This is because comparison of
  bools and reals always return exactly true or false.
  
  Case comparison returns bool. This differs from baseline Verilog,
  which strictly speaking returns a logic, but only 0 or 1 values.
  
  All the arithmetic operators return bool if both of their operands are
  bool or real. Otherwise, they return logic.</pre>
  
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  <h1><a name="icarus_verilog_glossary" id="icarus_verilog_glossary">Icarus Verilog Glossary</a></h1>
  <div class="level1">
  <pre class="code">Throughout Icarus Verilog descriptions and source code, I use a
  variety of terms and acronyms that might be specific to Icarus
  Verilog, have an Icarus Verilog specific meaning, or just aren't
  widely known. So here I define these terms.
  
  
  LRM     - Language Reference Manual
      This is a generic acronym, but in the Verilog world we sometimes
      mean *the* language reference manual, the IEEE1364 standard.
  
  
  PLI     - Programming Language Interface
      This is a C API into Verilog simulators that is defined by the
      IEEE1364. There are two major interfaces, sometimes called PLI 1
      and PLI 2. PLI 2 is also often called VPI.
  
  
  UDP     - User Defined Primitive
      These are objects that Verilog programmers define with the
      &quot;primitive&quot; keyword. They are truth-table based devices. The
      syntax for defining them is described in the LRM.
  
  
  VPI     -
      This is the C API that is defined by the Verilog standard, and
      that Icarus Verilog partially implements. See also PLI.
  
  
  VVM     - Verilog Virtual Machine
      This is the Icarus Verilog runtime that works with the code
      generator that generates C++.
  
  
  VVP     - Verilog Virtual Processor
      This is the Icarus Verilog runtime that reads in custom code in a
      form that I call &quot;VVP Assembly&quot;. See the vvp/ directory for
      documentation on that.
  
  </pre>
  
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  <h1><a name="icarus_verilog_vs._ieee1364" id="icarus_verilog_vs._ieee1364">Icarus Verilog vs. IEEE1364</a></h1>
  <div class="level1">
  <pre class="code">                Icarus Verilog vs. IEEE1364
                  Copyright 2000 Stephen Williams
  
  The IEEE1364 standard is the bible that defines the correctness of the
  Icarus Verilog implementation and behavior of the compiled
  program. The IEEE1364.1 is also referenced for matters of
  synthesis. So the ultimate definition of right and wrong comes from
  those documents.
  
  That does not mean that a Verilog implementation is fully
  constrained. The standard document allows for implementation specific
  behavior that, when properly accounted for, does not effect the
  intended semantics of the specified language. It is therefore possible
  and common to write programs that produce different results when run
  by different Verilog implementations.
  
  
  STANDARDIZATION ISSUES
  
  These are some issues where the IEEE1364 left unclear, unspecified or
  simply wrong. I'll try to be precise as I can, and reference the
  standard as needed. I've made implementation decisions for Icarus
  Verilog, and I will make clear what those decisions are and how they
  affect the language.
  
  * OBJECTS CAN BE DECLARED ANYWHERE IN THE MODULE
  
  Consider this module:
  
      module sample1;
          initial foo = 1;
  	reg foo;
  	wire tmp = bar;
  	initial #1 $display(&quot;foo = %b, bar = %b&quot;, foo, tmp);
      endmodule
  
  Notice that the ``reg foo;'' declaration is placed after the first
  initial statement. It turns out that this is a perfectly legal module
  according to the -1995 and -2000 versions of the standard. The
  statement ``reg foo;'' is a module_item_declaration which is in turn a
  module_item. The BNF in the appendix of IEEE1364-1995 treats all
  module_item statements equally, so no order is imposed.
  
  Furthermore, there is no text (that I can find) elsewhere in the
  standard that imposes any ordering restriction. The sorts of
  restrictions I would look for are &quot;module_item_declarations must
  appear before all other module_items&quot; or &quot;variables must be declared
  textually before they are referenced.&quot; Such statements simply do not
  exist. (Personally, I think it is fine that they don't.)
  
  The closest is the rules for implicit declarations of variables that
  are otherwise undeclared. In the above example, ``bar'' is implicitly
  declared and is therefore a wire. However, although ``initial foo = 1;''
  is written before foo is declared, foo *is* declared within the
  module, and declared legally by the BNF of the standard.
  
  Here is another example:
  
      module sample2;
  	initial x.foo = 1;
          test x;
  	initial #1 $display(&quot;foo = %b&quot;, x.foo);
      endmodule
  
      module test;
          reg foo;
      endmodule;
  
  From this example one can clearly see that foo is once again declared
  after its use in behavioral code. One also sees a forward reference of
  an entire module. Once again, the standard places no restriction on
  the order of module declarations in a source file, so this program is,
  according to the standard, perfectly well formed.
  
  Icarus Verilog interprets both of these examples according to &quot;The
  Standard As I Understand It.&quot; However, commercial tools in general
  break down with these programs. In particular, the first example
  may generate different errors depending on the tool. The most common
  error is to claim that ``foo'' is declared twice, once (implicitly) as
  a wire and once as a reg.
  
  So the question now becomes, &quot;Is the standard broken, or are the tools
  limited?&quot; Coverage of the standard seems to vary widely from tool to
  tool so it is not clear that the standard really is at fault. It is
  clear, however, that somebody goofed somewhere.
  
  My personal opinion is that there is no logical need to require that
  all module_item_declarations precede any other module items. I
  personally would oppose such a restriction. It may make sense to
  require that declarations of variables within a module be preceded by
  their use, although even that is not necessary for the implementation
  of efficient compilers.
  
  However, the existence hierarchical naming syntax as demonstrated in
  sample2 can have implications that affect any declaration order
  rules. When reaching into a module with a hierarchical name, the
  module being referenced is already completely declared (or not
  declared at all, as in sample2) so module_item order is completely
  irrelevant. But a &quot;declare before use&quot; rule would infect module
  ordering, by requiring that modules that are used be first defined.
  
  
  * TASK AND FUNCTION PARAMETERS CANNOT HAVE EXPLICIT TYPES
  
  Consider a function negate that wants to take a signed integer value
  and return its negative:
  
  	function integer negate;
  	    input [15:0] val;
  	    negate = -val;
  	endfunction
  
  This is not quite right, because the input is implicitly a reg type,
  which is unsigned. The result, then, will always be a negative value,
  even if a negative val is passed in.
  
  It is possible to fix up this specific example to work properly with
  the bit pattern of a 16bit number, but that is not the point. What's
  needed is clarification on whether an input can be declared in the
  port declaration as well as in the contained block declaration.
  
  As I understand the situation, this should be allowed:
  
  	function integer negate;
  	    input [15:0] val;
  	    reg signed [15:0] val;
  	    negate = -val;
  	endfunction
  
  In the -1995 standard, the variable is already implicitly a reg if
  declared within a function or task. However, in the -2000 standard
  there is now (as in this example) a reason why one might want to
  actually declare the type explicitly.
  
  I think that a port *cannot* be declared as an integer or time type
  (though the result can) because the range of the port declaration must
  match the range of the integer/time declaration, but the range of
  integers is unspecified. This, by the way, also applies to module
  ports.
  
  With the above in mind, I have decided to *allow* function and task
  ports to be declared with types, as long as the types are variable
  types, such as reg or integer. Without this, there would be no
  portable way to pass integers into functions/tasks. The standard does
  not say it is allowed, but it doesn't *disallow* it, and other
  commercial tools seem to work similarly.
  
  
  * ROUNDING OF TIME
  
  When the `timescale directive is present, the compiler is supposed to
  round fractional times (after scaling) to the nearest integer. The
  confusing bit here is that it is apparently conventional that if the
  `timescale directive is *not* present, times are rounded towards zero
  always.
  
  
  * VALUE OF X IN PRIMITIVE OUTPUTS
  
  The IEEE1364-1995 standard clearly states in Table 8-1 that the x
  symbols is allowed in input columns, but is not allowed in
  outputs. Furthermore, none of the examples have an x in the output of
  a primitive. Table 8-1 in the IEEE1364-2000 also says the same thing.
  
  However, the BNF clearly states that 0, 1, x and X are valid
  output_symbol characters. The standard is self contradictory. So I
  take it that x is allowed, as that is what Verilog-XL does.
  
  
  * REPEAT LOOPS vs. REPEAT EVENT CONTROL
  
  There seems to be ambiguity in how code like this should be parsed:
  
  	repeat (5) @(posedge clk) &lt;statement&gt;;
  
  There are two valid interpretations of this code, from the
  IEEE1364-1995 standard. One looks like this:
  
      procedural_timing_control_statement ::=
            delay_or_event_control  statement_or_null
  
      delay_or_event_control ::=
            event_control
            | repeat ( expression ) event_control
  
  If this interpretation is used, then the statement &lt;statement&gt; should
  be executed after the 5th posedge of clk. However, there is also this
  interpretation:
  
      loop_statement ::=
           repeat ( expression ) statement
  
  If *this* interpretation is used, then &lt;statement&gt; should be executed
  5 times on the posedge of clk. The way the -1995 standard is written,
  these are both equally valid interpretations of the example, yet they
  produce very different results. The standard offers no guidance on how
  to resolve this conflict, and the IEEE1364-2000 DRAFT does not improve
  the situation.
  
  Practice suggests that a repeat followed by an event control should be
  interpreted as a loop head, and this is what Icarus Verilog does, as
  well as all the other major Verilog tools, but the standard does not
  say this.
  
  * UNSIZED NUMERIC CONSTANTS ARE NOT LIMITED TO 32 BITS
  
  The Verilog standard allows Verilog implementations to limit the size
  of unsized constants to a bit width of at least 32. That means that a
  constant 17179869183 (36'h3_ffff_ffff) may overflow some compilers. In
  fact, it is common to limit these values to 32bits. However, a
  compiler may just as easily choose another width limit, for example
  64bits. That value is equally good.
  
  However, it is not *required* that an implementation truncate at 32
  bits, and in fact Icarus Verilog does not truncate at all. It will
  make the unsized constant as big as it needs to be to hold the value
  accurately. This is especially useful in situations like this;
  
  	    reg [width-1:0] foo = 17179869183;
  
  The programmer wants the constant to take on the width of the reg,
  which in this example is parameterized. Since constant sizes cannot be
  parameterized, the programmer ideally gives an unsized constant, which
  the compiler then expands/contracts to match the l-value.
  
  Also, by choosing to not ever truncate, Icarus Verilog can handle code
  written for a 64bit compiler as easily as for a 32bit compiler. In
  particular, any constants that the user does not expect to be
  arbitrarily truncated by his compiler will also not be truncated by
  Icarus Verilog, no matter what that other compiler chooses as a
  truncation point.
  
  
  * UNSIZED EXPRESSIONS AS PARAMETERS TO CONCATENATION {}
  
  The Verilog standard clearly states in 4.1.14:
  
  	&quot;Unsized constant numbers shall not be allowed in
  	concatenations. This is because the size of each
  	operand in the concatenation is needed to calculate
  	the complete size of the concatenation.&quot;
  
  So for example the expression {1'b0, 16} is clearly illegal. It
  also stands to reason that {1'b0, 15+1} is illegal, for exactly the
  same justification. What is the size of the expression (15+1)?
  Furthermore, it is reasonable to expect that (16) and (15+1) are
  exactly the same so far as the compiler is concerned.
  
  Unfortunately, Cadence seems to feel otherwise. In particular, it has
  been reported that although {1'b0, 16} causes an error, {1'b0, 15+1}
  is accepted. Further testing shows that any expression other then a
  simple unsized constant is accepted there, even if all the operands of
  all the operators that make up the expression are unsized integers.
  
  This is a semantic problem. Icarus Verilog doesn't limit the size of
  integer constants. This is valid as stated in 2.5.1 Note 3:
  
  	&quot;The number of bits that make up an unsized number
  	(which is a simple decimal number or a number without
  	the size specification) shall be *at*least* 32.&quot;
  	[emphasis added]
  
  Icarus Verilog will hold any integer constant, so the size will be as
  large as it needs to be, whether that is 64bits, 128bits, or
  more. With this in mind, what is the value of these expressions?
  
  	{'h1_00_00_00_00}
  	{'h1 &lt;&lt; 32}
  	{'h0_00_00_00_01 &lt;&lt; 32}
  	{'h5_00_00_00_00 + 1}
  
  These examples show that the standard is justified in requiring that
  the operands of concatenation have size. The dispute is what it takes
  to cause an expression to have a size, and what that size is.
  Verilog-XL claims that (16) does not have a size, but (15+1) does. The
  size of the expression (15+1) is the size of the adder that is
  created, but how wide is the adder when adding unsized constants?
  
  One might note that the quote from section 4.1.14 says &quot;Unsized
  *constant*numbers* shall not be allowed.&quot; It does not say &quot;Unsized
  expressions...&quot;, so arguably accepting (15+1) or even (16+0) as an
  operand to a concatenation is not a violation of the letter of the
  law. However, the very next sentence of the quote expresses the
  intent, and accepting (15+1) as having a more defined size then (16)
  seems to be a violation of that intent.
  
  Whatever a compiler decides the size is, the user has no way to
  predict it, and the compiler should not have the right to treat (15+1)
  any differently then (16). Therefore, Icarus Verilog takes the
  position that such expressions are *unsized* and are not allowed as
  operands to concatenations. Icarus Verilog will in general assume that
  operations on unsized numbers produce unsized results. There are
  exceptions when the operator itself does define a size, such as the
  comparison operators or the reduction operators. Icarus Verilog will
  generate appropriate error messages.
  
  
  * MODULE INSTANCE WITH WRONG SIZE PORT LIST
  
  A module declaration like this declares a module that takes three ports:
  
  	module three (a, b, c);
  	  input a, b, c;
  	  reg x;
  	endmodule
  
  This is fine and obvious. It is also clear from the standard that
  these are legal instantiations of this module:
  
  	three u1 (x,y,z);
  	three u2 ( ,y, );
  	three u3 ( , , );
  	three u4 (.b(y));
  
  In some of the above examples, there are unconnected ports. In the
  case of u4, the pass by name connects only port b, and leaves a and c
  unconnected. u2 and u4 are the same thing, in fact, but using
  positional or by-name syntax. The next example is a little less
  obvious:
  
  	three u4 ();
  
  The trick here is that strictly speaking, the parser cannot tell
  whether this is a list of no pass by name ports (that is, all
  unconnected) or an empty positional list. If this were an empty
  positional list, then the wrong number of ports is given, but if it is
  an empty by-name list, it is an obviously valid instantiation. So it
  is fine to accept this case as valid.
  
  These are more doubtful:
  
  	three u5(x,y);
  	three u6(,);
  
  These are definitely positional port lists, and they are definitely
  the wrong length. In this case, the standard is not explicit about
  what to do about positional port lists in module instantiations,
  except that the first is connected to the first, second to second,
  etc. It does not say that the list must be the right length, but every
  example of unconnected ports used by-name syntax, and every example of
  ordered list has the right size list.
  
  Icarus Verilog takes the (very weak) hint that ordered lists should be
  the right length, and will therefore flag instances u5 and u6 as
  errors. The IEEE1364 standard should be more specific one way or the
  other.
  
  * UNKNOWN VALUES IN L-VALUE BIT SELECTS
  
  Consider this example:
  
  	reg [7:0] vec;
  	wire [4:0] idx = &lt;expr&gt;;
  	[...]
  	vec[idx] = 1;
  
  So long as the value of idx is a valid bit select address, the
  behavior of this assignment is obvious. However, there is no explicit
  word in the standard as to what happens if the value is out of
  range. The standard clearly states the value of an expression when the
  bit-select or part select is out of range (the value is x) but does
  not address the behavior when the expression is an l-value.
  
  Icarus Verilog will take the position that bit select expressions in
  the l-value will select oblivion if it is out of range. That is, if
  idx has a value that is not a valid bit select of vec, then the
  assignment will have no effect.
  
  
  * SCHEDULING VALUES IN LOGIC
  
  The interaction between blocking assignments in procedural code and
  logic gates in gate-level code and expressions is poorly defined in
  Verilog. Consider this example:
  
     reg a;
     reg b;
     wire q = a &amp; b;
  
     initial begin
        a = 1;
        b = 0;
        #1 b = 1;
        if (q !== 0) begin
  	 $display(&quot;FAILED -- q changed too soon? %b&quot;, q);
  	 $finish;
        end
     end
  
  This is a confusing situation. It is clear from the Verilog standard
  that an assignment to a variable using a blocking assign causes the
  l-value to receive the value before the assignment completes. This
  means that a subsequent read of the assigned variable *must* read back
  what was blocking-assigned.
  
  However, in the example above, the &quot;wire q = a &amp; b&quot; expresses some
  gate logic between a/b and q. The standard does not say whether a read
  out of logic should read the value computed from previous assigns to
  the input from the same thread. Specifically, when &quot;a&quot; and &quot;b&quot; are
  assigned by blocking assignments, will a read of &quot;q&quot; get the computed
  value or the existing value?
  
  In fact, existing commercial tools do it both ways. Some tools print
  the FAILED message in the above example, and some do not. Icarus
  Verilog does not print the FAILED message in the above example,
  because the gate value change is *scheduled* when inputs are assigned,
  but not propagated until the thread gives up the processor.
  
  Icarus Verilog chooses this behavior in order to filter out zero-width
  pulses as early as possible. The implication of this is that a read of
  the output of combinational logic will most likely *not* reflect the
  changes in inputs until the thread that changed the inputs yields
  execution.
  
  
  * BIT AND PART SELECTS OF PARAMETERS
  
  Bit and part selects are supposed to only be supported on vector nets
  and variables (wires, regs, etc.) However, it is common for Verilog
  compilers to also support bit and part select on parameters. Icarus
  Verilog also chooses to support bit and part selects on parameter
  names, but we need to define what that means.
  
  A bit or a part select on a parameter expression returns an unsigned
  value with a defined size. The parameter value is considered be a
  constant vector of bits foo[X:0]. That is, zero based. The bit and
  part selects operate from that assumption.
  
  Verilog 2001 adds syntax to allow the user to explicitly declare the
  parameter range (i.e. parameter [5:0] foo = 9;) so Icarus Verilog will
  (or should) use the explicitly declared vector dimensions to interpret
  bit and part selects.
  
  
  * EDGES OF VECTORS
  
  Consider this example:
  
     reg [ 5:0] clock;
     always @(posedge clock) [do stuff]
  
  The IEEE1364 standard clearly states that the @(posedge clock) looks
  only at the bit clock[0] (the least significant bit) to search for
  edges. It has been pointed out by some that Verilog XL instead
  implements it as &quot;@(posedge |clock)&quot;: it looks for a rise in the
  reduction or of the vector. Cadence Design Systems technical support
  has been rumored to claim that the IEEE1364 specification is wrong,
  but NC-Verilog behaves according to the specification, and thus
  different from XL.
  
  Icarus Verilog, therefore, takes the position that the specification
  is clear and correct, and it behaves as does NC-Verilog in this
  matter.
  
  
  * REAL VARIABLES IN $dumpoff DEAD-ZONES
  
  The IEEE1364 standard clearly states that in VCD files, the $dumpoff
  section checkpoints all the dumped variables as X values. For reg and
  wire bits/vectors, this obviously means 'bx values. Icarus Verilog
  does this, for example:
  
      $dumpoff
      x!
      x&quot;
      $end
  
  Real variables can also be included in VCD dumps, but it is not at
  all obvious what is supposed to be dumped into the $dumpoff-$end
  section of the VCD file. Verilog-XL dumps &quot;r0 !&quot; to set the real
  variables to the dead-zone value of 0.0, whereas other tools, such as
  ModelTech, ignore real variables in this section.
  
  For example (from XL):
  
      $dumpoff
      r0 !
      r0 &quot;
      $end
  
  Icarus Verilog dumps NaN values for real variables in the
  $dumpoff-$end section of the VCD file. The NaN value is the IEEE754
  equivalent of an unknown value, and so better reflects the unknown
  (during the dead zone) status of the variable, like this:
  
      $dumpoff
      rNaN !
      rNaN &quot;
      $end
  
  It turns out that NaN is conventionally accepted by scanf functions,
  and viewers that support real variables support NaN values. So while
  the IEEE1364 doesn't require this behavior, and given the variety that
  already seems to exist amongst VCD viewers in the wild, this behavior
  seems to be acceptable according to the standard, is a better mirror
  of 4-value behavior in the dead zone, and appears more user friendly
  when viewed by reasonable viewers.
  
  
  $Id: geda_icarus_ieee1364.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
  $Log: geda_icarus_ieee1364.html,v $
  Revision 1.1  2006/08/22 02:56:12  ahvezda
  First checkin of the wiki snapshot, prep work for new version of gEDA/gaf
  
  Revision 1.17  2003/07/15 03:49:22  steve
   Spelling fixes.
  
  Revision 1.16  2003/04/14 03:40:21  steve
   Make some effort to preserve bits while
   operating on constant values.
  
  Revision 1.15  2003/02/16 23:39:08  steve
   NaN in dead zones of VCD dumps.
  
  Revision 1.14  2003/02/06 17:51:36  steve
   Edge of vectors notes.
  
  Revision 1.13  2002/08/20 04:11:53  steve
   Support parameters with defined ranges.
  
  Revision 1.12  2002/06/11 03:34:33  steve
   Spelling patch (Larry Doolittle)
  
  Revision 1.11  2002/04/27 02:38:04  steve
   Support selecting bits from parameters.
  
  Revision 1.10  2002/03/31 01:54:13  steve
   Notes about scheduling
  
  Revision 1.9  2002/01/26 02:08:07  steve
   Handle x in l-value of set/x
  
  Revision 1.8  2001/08/01 05:17:31  steve
   Accept empty port lists to module instantiation.
  
  Revision 1.7  2001/02/17 05:27:31  steve
   I allow function ports to have types.
  
  Revision 1.6  2001/02/12 16:48:04  steve
   Rant about bit widths.
  
  Revision 1.5  2001/01/02 17:28:08  steve
   Resolve repeat ambiguity in favor of loop.
  
  Revision 1.4  2001/01/01 19:12:35  steve
   repeat loops ambiguity.
  
  Revision 1.3  2000/12/15 00:21:46  steve
   rounding of time and x in primitives.
  
  Revision 1.2  2000/11/19 22:03:04  steve
   Integer parameter comments.
  
  Revision 1.1  2000/07/23 18:06:31  steve
   Document ieee1364 issues.</pre>
  
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  <h1><a name="icarus_verilog_compiler_man-page" id="icarus_verilog_compiler_man-page">Icarus Verilog compiler man-page</a></h1>
  <div class="level1">
  <pre class="code">iverilog(1)		 $Date: 2006/08/22 02:56:12 $		   iverilog(1)
  
  
  
  NAME
         iverilog - Icarus Verilog compiler
  
  
  SYNOPSIS
         iverilog	 [-ESVv]  [-Bpath] [-ccmdfile] [-g1|-g2|-g2x] [-Dmacro[=defn]]
         [-pflag=value] [-Iincludedir] [-mmodule] [-Mfile]  [-Nfile]  [-ooutput-
         filename]  [-stopmodule]	 [-ttype]  [-Tmin/typ/max]  [-Wclass] [-ypath]
         sourcefile
  
  
  DESCRIPTION
         iverilog is a compiler that translates Verilog source  code  into  exe-
         cutable	programs  for simulation, or other netlist formats for further
         processing. The currently supported targets are vvp for simulation, and
         xnf and fpga for synthesis. Other target types are added as code gener-
         ators are implemented.
  
  
  OPTIONS
         iverilog accepts the following options:
  
         -Bbase  The iverilog program uses external programs  and	 configuration
  	       files  to  preprocess and compile the Verilog source. Normally,
  	       the path used to locate these tools is built into the  iverilog
  	       program.	 However,  the	-B  switch allows the user to select a
  	       different set of programs. The path given  is  used  to	locate
  	       ivlpp, ivl, code generators and the VPI modules.
  
         -cfile  This  flag specifies an input file that contains a list of Ver-
  	       ilog source files. This is similar to the command file of other
  	       Verilog simulators, in that it is a file that contains the file
  	       names instead of taking them on the command line.  See  Command
  	       Files below.
  
         -Dmacro Defines macro macro with the string Ã¢â?¬Ë?1Ã¢â?¬â?¢ as its definition. This
  	       form is normally only used to trigger ifdef conditionals in the
  	       Verilog source.
  
         -Dmacro=defn
  	       Defines macro macro as defn.
  
         -E      Preprocess  the Verilog source, but do not compile it. The out-
  	       put file is the Verilog input, but  with	 file  inclusions  and
  	       macro  references  expanded  and	 removed.  This is useful, for
  	       example, to preprocess Verilog source for use by other  compil-
  	       ers.
  
         -g1|-g2|-g2x
  	       Select  the  Verilog language generation to support in the com-
  	       piler. This selects between IEEE1364-1995(1), IEEE1364-2001(2),
  	       or   Verilog   with  extension(2x).  Normally,  Icarus  Verilog
  	       defaults to the latest known generation of the  language.  This
  	       flag is most useful to restrict the language to a set supported
  	       by tools of specific generations, for compatibility with	 other
  	       tools.
  
         -Iincludedir
  	       Append directory includedir to list of directories searched for
  	       Verilog include files. The -I switch may be used many times  to
  	       specify	several	 directories  to  search,  the directories are
  	       searched in the order they appear on the command line.
  
         -Mpath  Write into the file specified by path a list of files that con-
  	       tribute	to  the compilation of the design. This includes files
  	       that are included by include  directives	 and  files  that  are
  	       automatically loaded by library support. The output is one file
  	       name per line, with no leading or trailing space.
  
         -mmodule
  	       Add this module to the list of VPI modules to be loaded by  the
  	       simulation.  Many  modules  can	be  specified, and all will be
  	       loaded, in the order specified. The system module  is  implicit
  	       and always included.
  
         -Npath  This  is used for debugging the compiler proper. Dump the final
  	       netlist form of the design to the specified file. It  otherwise
  	       does  not  affect  operation  of the compiler. The dump happens
  	       after the design is elaborated and optimized.
  
         -o filename
  	       Place output in the file filename. If no output	file  name  is
  	       specified, iverilog uses the default name a.out.
  
         -pflag=value
  	       Assign  a value to a target specific flag. The -p switch may be
  	       used as often as necessary to specify all  the  desired	flags.
  	       The  flags that are used depend on the target that is selected,
  	       and are described in target specific documentation. Flags  that
  	       are not used are ignored.
  
         -S      Synthesize.  Normally,  if  the	target	can  accept behavioral
  	       descriptions the compiler will leave  processes	in  behavioral
  	       form.  The  -S  switch causes the compiler to perform synthesis
  	       even if it is not necessary for the target. If the target  type
  	       is  a  netlist  format, the -S switch is unnecessary and has no
  	       effect.
  
         -s topmodule
  	       Specify the top level module to elaborate. Icarus Verilog  will
  	       by  default  choose  modules  that  are not instantiated in any
  	       other modules, but sometimes that is not sufficient, or instan-
  	       tiates too many modules. If the user specifies one or more root
  	       modules with -s flags, then they will be used as	 root  modules
  	       instead.
  
         -Tmin|typ|max
  	       Use   this  switch  to  select  min,  typ  or  max  times  from
  	       min:typ:max expressions. Normally, the compiler will simply use
  	       the  typ value from these expressions (with a warning) but this
  	       switch will tell the compiler explicitly which  value  to  use.
  	       This  will  suppress  the warning that the compiler is making a
  	       choice.
  
         -ttarget
  	       Use this switch to specify the target output  format.  See  the
  	       TARGETS section below for a list of valid output formats.
  
         -v      Turn  on	 verbose  messages.  This will print the command lines
  	       that are executed to perform the actual compilation, along with
  	       version information from the various components, as well as the
  	       version of the product as a whole.  You will  notice  that  the
  	       command	lines include a reference to a key temporary file that
  	       passes information to the compiler proper.  To keep  that  file
  	       from  being  deleted  at the end of the process, provide a file
  	       name of your own in the environment variable  IVERILOG_ICONFIG.
  
         -V      Print the version of the compiler, and exit.
  
         -Wclass Turn  on	 different  classes of warnings. See the WARNING TYPES
  	       section below for descriptions of the different warning groups.
  	       If  multiple -W switches are used, the warning set is the union
  	       of all the requested classes.
  
         -ylibdir
  	       Append the directory to the library module  search  path.  When
  	       the  compiler  finds  an	 undefined  module,  it looks in these
  	       directories for files with the right name.
  
  
  MODULE LIBRARIES
         The Icarus Verilog compiler supports module  libraries  as  directories
         that  contain  Verilog  source files.  During elaboration, the compiler
         notices the instantiation of undefined module types. If the user speci-
         fies library search directories, the compiler will search the directory
         for files with the name of the missing module type. If it finds such  a
         file,  it loads it as a Verilog source file, they tries again to elabo-
         rate the module.
  
         Library module files should contain only a single module, but  this  is
         not  a  requirement. Library modules may reference other modules in the
         library or in the main design.
  
  
  TARGETS
         The Icarus Verilog compiler supports a variety of targets, for  differ-
         ent purposes, and the -t switch is used to select the desired target.
  
  
         null    The  null  target  causes no code to be generated. It is useful
  	       for checking the syntax of the Verilog source.
  
         vvp     This is the default. The vvp target generates code for the  vvp
  	       runtime.	 The  output  is a complete program that simulates the
  	       design but must be run by the vvp command.
  
         xnf     This is the Xilinx Netlist Format used by many tools for	 plac-
  	       ing devices in FPGAs or other programmable devices. This target
  	       is obsolete, use the fpga target instead.
  
         fpga    This is a synthesis target that	supports  a  variety  of  fpga
  	       devices,	 mostly by EDIF format output. The Icarus Verilog fpga
  	       code generator can generate complete  designs  or  EDIF	macros
  	       that  can  in  turn  be	imported  into larger designs by other
  	       tools. The fpga target implies the synthesis -S flag.
  
  
  WARNING TYPES
         These are the types of warnings that can be selected by the -W  switch.
         All the warning types (other then all) can also be prefixed with no- to
         turn off that warning. This is most useful after a  -Wall  argument  to
         suppress isolated warning types.
  
  
         all     This enables all supported warning categories.
  
  
         implicit
  	       This  enables  warnings	for creation of implicit declarations.
  	       For example, if a scalar wire X is used but not declared in the
  	       Verilog source, this will print a warning at its first use.
  
  
         portbind
  	       This  enables  warnings for ports of module instantiations that
  	       are not connected but probably should be. Dangling input ports,
  	       for example, will generate a warning.
  
  
         timescale
  	       This  enables  warnings	for  inconsistent use of the timescale
  	       directive. It detects if some modules have no timescale, or  if
  	       modules inherit timescale from another file. Both probably mean
  	       that timescales are inconsistent, and simulation timing can  be
  	       confusing and dependent on compilation order.
  
  
  SYSTEM FUNCTION TABLE FILES
         If the source file name as a .sft suffix, then it is taken to be a sys-
         tem function table file. A  System  function  table  file  is  used  to
         describe to the compiler the return types for system functions. This is
         necessary because the compiler  needs  this  information	 to  elaborate
         expressions  that  contain  these  system functions, but cannot run the
         sizetf functions since it has no run-time.
  
         The format of the table is ASCII, one function per  line.  Empty	 lines
         are  ignored,  and  lines that start with the Ã¢â?¬â?¢#Ã¢â?¬â?¢ character are comment
         lines. Each non-comment line starts with the function  name,  then  the
         vpi type (i.e. vpiSysFuncReal). The following types are supported:
  
  
         vpiSysFuncReal
  	       The function returns a real/realtime value.
  
  
         vpiSysFuncInt
  	       The function returns an integer.
  
  
         vpiSysFuncSized &lt;wid&gt; &lt;signed|unsigned&gt;
  	       The  function  returns  a  vector  with the given width, and is
  	       signed or unsigned according to the flag.
  
  
  COMMAND FILES
         The command file allows the user to place source file names and certain
         command	line  switches	into  a text file instead of on a long command
         line. Command files can include C or C++ style comments, as well	 as  #
         comments, if the # starts the line.
  
  
         file name
  	       A  simple  file	name or file path is taken to be the name of a
  	       Verilog source file. The path starts with the first  non-white-
  	       space character. Variables are substitued in file names.
  
  
         -y libdir
  	       A  -y  token  prefixes a library directory in the command file,
  	       exactly like it does on the command line. The parameter to  the
  	       -y flag may be on the same line or the next non-comment line.
  
  	       Variables in the libdir are substituted.
  
  
         +incdir+includedir
  	       The +incdir+ token in command files gives directories to search
  	       for include files in much the same way that -I  flags  work  on
  	       the  command  line. The difference is that multiple +includedir
  	       directories are valid parameters to a  single  +incdir+	token,
  	       although you may also have multiple +incdir+ lines.
  
  	       Variables in the includedir are substituted.
  
  
         +libext+ext
  	       The +libext token in command files fives file extensions to try
  	       when looking for a library file. This is useful in  conjunction
  	       with  -y flags to list suffixes to try in each directory before
  	       moving on to the next library directory.
  
  
         +libdir+dir
  	       This is another way to specify library directories. See the  -y
  	       flag.
  
  
         +libdir-nocase+dir
  	       This  is	 like the +libdir statement, but file names inside the
  	       directories declared here are  case  insensitive.  The  missing
  	       module  name  in a lookup need not match the file name case, as
  	       long as the letters are correct.	 For  example,	&quot;foo&quot;  matches
  	       &quot;Foo.v&quot; but not &quot;bar.v&quot;.
  
  
         +define+NAME=value
  	       The  +define+ token is the same as the -D option on the command
  	       line. The value part of the token is optional.
  
  
         +toupper-filename
  	       This token causes file names after this in the command file  to
  	       be  translated to uppercase. This helps with situations where a
  	       directory has passed through a DOS machine, and in the  process
  	       the file names become munged.
  
  
         +tolower-filename
  	       This  is similar to the +toupper-filename hack described above.
  
  
  VARIABLES IN COMMAND FILES
         In certain cases, iverilog supports variables in command	 files.	 These
         are  strings of the form &quot;$(varname)&quot;, where varname is the name of the
         environment variable to read. The entire string is  replaced  with  the
         contents	 of  that  variable. Variables are only substitued in contexts
         that explicitly support them, including file and directory strings.
  
         Variable values come from the operating	system	environment,  and  not
         from preprocessor defines elsewhere in the file or the command line.
  
  
  EXAMPLES
         These  examples	assume	that  you  have	 a  Verilog source file called
         hello.v in the current directory
  
         To compile hello.v to an executable file called a.out:
  
  	    iverilog hello.v
  
         To compile hello.v to an executable file called hello:
  
  	    iverilog -o hello hello.v
  
         To compile and run explicitly using the vvp runtime:
  
  	    iverilog -ohello.vvp -tvvp hello.v
  
         To compile hello.v to a file in XNF-format called hello.xnf
  
  	    iverilog -txnf -ohello.xnf hello.v
  
  
  
  AUTHOR
         Steve Williams (steve@xxxxxxxxxx)
  
  
  SEE ALSO
         vvp(1), &lt;http://www.icarus.com/eda/verilog/&gt;
  
  
  COPYRIGHT
         Copyright Ã?Â©  2002 Stephen Williams
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  Version			 $Date: 2006/08/22 02:56:12 $		   iverilog(1)</pre>
  
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  <h1><a name="executable_instruction_opcodes" id="executable_instruction_opcodes">Executable Instruction Opcodes</a></h1>
  <div class="level1">
  <pre class="code">/*
   * Copyright (c) 2001-2003 Stephen Williams (steve@xxxxxxxxxx)
   *
   *  $Id: geda_icarus_opcodes.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
   */
  
  
  
  EXECUTABLE INSTRUCTION OPCODES
  
  Instruction opcodes all start with a % character and have 0 or more
  operands. In no case are there more then 3 operands. This chapter
  describes the specific behavior of each opcode, in enough detail
  (I hope) that its complete effect can be predicted.
  
  General principles of Arithmetic:
  
  The binary arithmetic instruction in general take three parameters,
  the left operand, the right operand, and the base. The left operand is
  replaced with the result, which is the same width as the left and
  right operands.
  
  
  * %add &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction adds the right vector into the left vector, the
  vectors having the width &lt;wid&gt;. If any of the bits of either vector
  are x or z, the result is x. Otherwise, the result is the arithmetic
  sum.
  
  See also the %sub instruction.
  
  
  * %add/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  
  This is the real valued version of the %add instruction. The arguments
  are word indices of the operands. The right operand is added into the
  left operand.
  
  See also the %sub/wr instruction.
  
  
  * %addi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
  
  This instruction adds the immediate value (no x or z bits) into the
  left vector. The imm value is limited to 16 significant bits, but it
  is zero extended to match any width.
  
  * %and &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  Perform the bitwise AND of the two vectors, and store the result in
  the left vector. Each bit is calculated independent of other bits. AND
  means the following:
  
  	0 and ? --&gt; 0
  	? and 0 --&gt; 0
  	1 and 1 --&gt; 1
  	otherwise   x
  
  * %assign/m &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE)
  
  This instruction does a non-blocking assignment to a bit in a memory
  from the specified thread register &lt;bit&gt;.  The memory bit is addressed
  by index register 3.  Bit address zero is the LSB of the first memory
  word.
  
  * %assign/mv &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  
  the %assign/mv instruction assigns a vector value to a word in the
  labeled memory. The &lt;delay&gt; is the delay in simulation time to the
  assignment (0 for non-blocking assignment) and the &lt;bit&gt; is the base
  of the vector to write.
  
  The width of the word is retrieved from index register 0.
  
  The address of the word in the memory is from index register 3. The
  address is canonical form.
  
  * %assign/v0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  * %assign/v0/d &lt;var-label&gt;, &lt;delayx&gt;, &lt;bit&gt;
  
  The %assign/v0 instruction is a vector version of non-blocking
  assignment. The &lt;delay&gt; is the number of clock ticks in the future
  where the assignment should be schedule, and the &lt;bit&gt; is the base of
  the vector to be assigned to the destination. The vector width is in
  index register 0.
  
  The %assign/v0/d variation puts the delay instead into an integer
  register that is given by the &lt;delayx&gt; value. This should not be 0, of
  course, because integer 0 is taken with the vector width.
  
  The &lt;var-label&gt; references a .var object that can receive non-blocking
  assignments. For blocking assignments, see %set/v.
  
  * %assign/v0x1 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  
  This is similar to the %assign/v0 instruction, but adds the index-1
  index register with the canonical index of the destination where the
  vector is to be written. This allows for part writes into the vector.
  
  * %assign/wr &lt;vpi-label&gt;, &lt;delay&gt;, &lt;index&gt;
  
  This instruction causes a non-blocking assign of the indexed value to
  the real object addressed by the &lt;vpi-label&gt; label.
  
  * %assign/x0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE -- See %assign/v0x)
  
  This does a non-blocking assignment to a functor, similar to the
  %assign instruction. The &lt;var-label&gt; identifies the base functor of
  the affected variable, and the &lt;delay&gt; gives the delay when the
  assignment takes place. The delay may be 0. The actual functor used is
  calculated by using &lt;var-label&gt; as a base, and indexing with the
  index[0] index register. This supports indexed assignment.
  
  The &lt;bit&gt; is the address of the thread register that contains the bit
  value to assign.
  
  
  * %blend &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction blends the bits of a vector into the destination in a
  manner like the expression (x ? &lt;a&gt; : &lt;b&gt;). The truth table is:
  
  	1  1 --&gt; 1
  	0  0 --&gt; 0
  	z  z --&gt; z
  	x  x --&gt; x
  	.... --&gt; x
  
  In other words, if the bits are identical, then take that
  value. Otherwise, the value is x.
  
  * %breakpoint
  
  This instruction unconditionally breaks the simulator into the
  interactive debugger. The idea is to stop the simulator here and give
  the user a chance to display the state of the simulation using
  debugger commands.
  
  This may not work on all platforms. If run-time debugging is compiled
  out, then this function is a no-op.
  
  * %cassign/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  Perform a continuous assign of a constant value to the target
  variable. This is similar to %set, but it uses the cassign port
  (port-1) of the signal functor instead of the normal assign, so the
  signal responds differently. See &quot;VARIABLE STATEMENTS&quot; in the
  README.txt file.
  
  
  * %cmp/u &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  * %cmp/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  These instructions perform a generic comparison of two vectors of equal
  size. The &lt;bit-l&gt; and &lt;bit-r&gt; numbers address the least-significant
  bit of each vector, and &lt;wid&gt; is the width. If either operand is 0,
  1, 2 or 3 then it is taken to be a constant replicated to the selected
  width.
  
  The results of the comparison go into bits 4, 5, 6 and 7:
  
  	4: eq  (equal)
  	5: lt  (less than)
  	6: eeq (case equal)
  
  The eeq bit is set to 1 if all the bits in the vectors are exactly the
  same, or 0 otherwise. The eq bit is true if the values are logically
  the same. That is, x and z are considered equal. In other words the eq
  bit is the same as ``=='' and the eeq bit ``===''.
  
  The lt bit is 1 if the left vector is less then the right vector, or 0
  if greater then or equal to the right vector. It is the equivalent of
  the Verilog &lt; operator. Combinations of these three bits can be used
  to implement all the Verilog comparison operators.
  
  The %cmp/u and %cmp/s differ only in the handling of the lt bit. The
  %cmp/u does an unsigned compare, whereas the %cmp/s does a signed
  compare. In either case, if either operand contains x or z, then lt
  bit gets the x value.
  
  
  * %cmp/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  
  [compare real values.]
  
  * %cmp/ws &lt;bit-l&gt;, &lt;bit-r&gt;
  * %cmp/wu &lt;bit-l&gt;, &lt;bit-r&gt;
  
  [compare signed/unsigned integer words.]
  
  * %cmp/z &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  * %cmp/x &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  These instructions are for implementing the casez and casex
  comparisons. These work similar to the %cmp/u instructions, except
  only an eq bit is calculated. These comparisons both treat z values in
  the left or right operand as don't care positions. The %cmp/x
  instruction will also treat x values in either operand as don't care.
  
  Only bit 4 is set by these instructions.
  
  
  * %cvt/ir &lt;bit-l&gt;, &lt;bit-r&gt;
  * %cvt/ri &lt;bit-l&gt;, &lt;bit-r&gt;
  * %cvt/vr &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  Copy a word from r to l, converting it from real to integer (ir) or
  integer to real (ri) in the process. The source and destination may
  be the same word address, leading to a convert in place.
  
  The %cvt/vr opcode converts a real word &lt;bit-r&gt; to a thread vector
  starting at &lt;bit-l&gt; and with the width &lt;wid&gt;. Non-integer precision is
  lost in the conversion.
  
  * %deassign &lt;var-label&gt;
  
  Deactivate and disconnect a procedural continuous assignment to a
  variable. The &lt;var-label&gt; identifies the affected variable.
  
  * %delay &lt;delay&gt;
  
  This opcode pauses the thread, and causes it to be rescheduled for a
  time in the future. The &lt;amount&gt; is the number of the ticks in the
  future to reschedule, and is &gt;= 0. If the %delay is zero, then the
  thread yields the processor for another thread, but will be resumed in
  the current time step.
  
  * %delayx &lt;idx&gt;
  
  This is similar to the %delay opcode, except that the parameter
  selects an index register, which contains the actual delay. This
  supports run-time calculated delays.
  
  * %disable &lt;scope-label&gt;
  
  This instruction terminates threads that are part of a specific
  scope. The label identifies the scope in question, and the threads are
  the threads that are currently within that scope.
  
  
  * %div &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  * %div/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction arithmetically divides the &lt;bit-l&gt; vector by the
  &lt;bit-r&gt; vector, and leaves the result in the &lt;bit-l&gt; vector. IF any of
  the bits in either vector are x or z, the entire result is x.
  
  The %div/s instruction is the same as %div, but does signed division.
  
  
  * %div/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  
  This opcode divides the left operand by the right operand. If the
  right operand is 0, then the result is NaN.
  
  
  * %force/v &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  Force a constant value to the target variable. This is similar to %set
  and %cassign/v, but it uses the force port (port-2) of the signal
  functor instead of the normal assign port (port-0), so the signal
  responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
  in the README.txt file.
  
  * %force/x0 &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  Force a constant value to part target variable. This is similar to
  %set/x instruction, but it uses the force port (port-2) of the signal
  functor instead of the normal assign port (port-0), so the signal
  responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
  in the README.txt file.
  
  * %fork &lt;code-label&gt;, &lt;scope-label&gt;
  
  This instruction is similar to %jmp, except that it creates a new
  thread to start executing at the specified address. The new thread is
  created and pushed onto the child stack.  It is also marked runnable,
  but is not necessarily started until the current thread yields.
  
  The %fork instruction has no effect other then to push a child thread.
  
  See also %join.
  
  
  * %inv &lt;bit&gt;, &lt;wid&gt;
  
  Perform a bitwise invert of the vector starting at &lt;bit&gt;. The result
  replaces the input. Invert means the following, independently for each
  bit:
  
  	0  --&gt; 1
  	1  --&gt; 0
  	x  --&gt; x
  	z  --&gt; x
  
  
  * %ix/get &lt;idx&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  This instruction loads a thread vector starting at &lt;bit&gt;, size &lt;wid&gt;,
  into the index register &lt;idx&gt;. The &lt;bit&gt; is the lsb of the value in
  thread bit space, and &lt;wid&gt; is the width of the vector.
  
  The function converts the 4-value bits into a binary number, without
  sign extension. If any of the bits of the vector is x or z, then the
  index register gets the value 0.
  
  The function also writes into bit 4 a 1 if any of the bits of the
  input vector are x or z. This is a flag that the 0 value written into
  the index register is really the result of calculating from unknown
  bits.
  
  	4: unknown value
  	5: (reserved)
  	6: (reserved)
  
  
  * %ix/load &lt;idx&gt;, &lt;value&gt;
  
  This instruction loads an immediate value into the addressed index
  register. The index register holds numeric values, so the &lt;value&gt; is a
  number. The idx value selects the index register, and may be 0, 1, 2
  or 3. This is different from %ix/get, which loads the index register
  from a value in the thread bit vector.
  
  
  * %ix/add &lt;idx&gt;, &lt;value&gt;
  * %ix/sub &lt;idx&gt;, &lt;value&gt;
  * %ix/mul &lt;idx&gt;, &lt;value&gt;
  
  This instruction adds, subtracts, or multiplies an immediate value to
  the addressed index register. The index register holds numeric values,
  so the &lt;value&gt; is a number. The &lt;idx&gt; value selects the index register,
  and may be 0, 1, 2 or 3.
  
  
  * %jmp &lt;code-label&gt;
  
  The %jmp instruction performs an unconditional branch to a given
  location. The parameter is the label of the destination instruction.
  
  * %jmp/[01xz] &lt;code-label&gt;, &lt;bit&gt;
  
  This is a conditional version of the %jmp instruction. In this case,
  a single bit (addressed by &lt;bit&gt;) is tested. If it is one of the
  values in the part after the /, the jump is taken. For example:
  
  	%jmp/xz T_label, 8;
  
  will jump to T_label if bit 8 is x or z.
  
  * %join
  
  This is the partner to %fork. This instruction causes the thread to
  wait for the top thread in the child stack to terminate, then
  continues. It has no effect in the current thread other then to wait
  until the top child is cleared.
  
  It is an error to execute %join if there are no children in the child
  stack. Every %join in the thread must have a matching %fork that
  spawned off a child thread.
  
  If the matching child instruction is still running, a %join suspends
  the calling thread until the child ends. If the child is already
  ended, then the %join does not block or yield the thread.
  
  * %load/m &lt;bit&gt;, &lt;memory-label&gt; (OBSOLETE)
  
  This instruction loads a value from a memory bit into the specified
  thread register bit. The memory bit is addressed by index register 3.
  Bit address zero is the LSB of the first memory word.  This
  instruction loads only a single bit.
  
  * %load/mv &lt;bit&gt;, &lt;memory-label&gt;, &lt;wid&gt;
  
  this instruction loads a word from the specified memory. The word
  address is in index register 3. The width should match the width of
  the memory word.
  
  * %load/nx &lt;bit&gt;, &lt;vpi-label&gt;, &lt;idx&gt;
  
  This instruction load a value from a .net object bit. Since .net
  objects don't really exist (they are only named indirection into the
  netlist) this instruction indexes into the .net list of bits.
  
  * %load/v &lt;bit&gt;, &lt;functor-label&gt;, &lt;wid&gt;
  
  This instruction loads a vector value from the given functor node into
  the specified thread register bit. The functor-label can refer to a
  .net, a .var or a .functor with a vector output. The entire vector,
  from the least significant up to &lt;wid&gt; bits, is loaded starting at
  thread bit &lt;bit&gt;. It is an error for the width to not match the vector
  width at the functor.
  
  * %load/wr &lt;bit&gt;, &lt;vpi-label&gt;
  
  This instruction reads a real value from the vpi-like object to a word
  register.
  
  * %load/x &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
  * %load/x.p &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
  
  This is an indexed load. It uses the contents of the specified index
  register to select a bit from a vector functor at &lt;functor-label&gt;. The
  bit is pulled from the indexed bit of the addressed functor and loaded
  into the destination thread bit. If the indexed value is beyond the
  width of the vector, then the result is X.
  
  The %load/x.p is the same, but when the operation is done, it
  increments the specified index register. This provides a basic
  auto-increment feature.
  
  * %loadi/wr &lt;bit&gt;, &lt;mant&gt;, &lt;exp&gt;
  
  This opcode loads an immediate value, floating point, into the word
  register selected by &lt;bit&gt;. The mantissa is an unsigned integer value,
  up to 32 bits, that multiplied by 2**(&lt;exp&gt;-0x1000) to make a real
  value. The sign bit is OR-ed into the &lt;exp&gt; value at bit 0x2000, and
  is removed from the &lt;exp&gt; before calculating the real value.
  
  
  * %mod   &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  * %mod/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction calculates the modulus %r of the left operand, and
  replaces the left operand with the result. The &lt;wid&gt; gives the width
  of the left and the right vectors, and the left vector is completely
  replaced with the result.
  
  The /s form does signed %.
  
  * %mov &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  This instruction copies a vector from one place in register space to
  another. The destination and source vectors are assumed to be the same
  width and non-overlapping. The &lt;dst&gt; may not be 0-3, but if the &lt;src&gt;
  is one of the 4 constant bits, the effect is to replicate the value
  into the destination vector. This is useful for filling a vector.
  
  
  * %mul &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction multiplies the left vector by the right vector, the
  vectors having the width &lt;wid&gt;. If any of the bits of either vector
  are x or z, the result is x. Otherwise, the result is the arithmetic
  product.
  
  
  * %mul/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  
  This opcode multiplies two real words together. The result replaces
  the left operand.
  
  
  * %muli &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
  
  This instruction is the same as %mul, but the second operand is an
  immediate value that is padded to the width of the result.
  
  
  * %nand &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  Perform the bitwise NAND of the two vectors, and store the result in
  the left vector. Each bit is calculated independent of other bits. NAND
  means the following:
  
  	0 and ? --&gt; 1
  	? and 0 --&gt; 1
  	1 and 1 --&gt; 0
  	otherwise   x
  
  
  * %nor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  Perform the bitwise nor of the vectors. Each bit in the &lt;dst&gt; is
  combined with the corresponding bit in the source, according to the
  truth table:
  
  	1 nor ? --&gt; 0
  	? nor 1 --&gt; 0
  	0 nor 0 --&gt; 1
  	otherwise  x
  
  
  * %nor/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  The %nor/r instruction is a reduction nor. That is, the &lt;src&gt; is a
  vector with width, but the result is a single bit. The &lt;src&gt; vector is
  not affected by the operation unless the &lt;dst&gt; bit is within the
  vector. The result is calculated before the &lt;dst&gt; bit is written, so
  it is valid to place the &lt;dst&gt; within the &lt;src&gt;.
  
  The actual operation performed is the inverted or of all the bits in
  the vector.
  
  
  * %or &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  Perform the bitwise or of the vectors. Each bit in the &lt;dst&gt; is
  combined with the corresponding bit in the source, according to the
  truth table:
  
  	1 or ? --&gt; 1
  	? or 1 --&gt; 1
  	0 or 0 --&gt; 0
  	otherwise  x
  
  
  * %or/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  This is a reduction version of the %or opcode. The &lt;src&gt; is a vector,
  and the &lt;dst&gt; is a writable scalar. The &lt;dst&gt; gets the value of the
  or of all the bits of the src vector.
  
  
  * %release/net &lt;functor-label&gt;
  * %release/reg &lt;functor-label&gt;
  
  Release the force on the signal that is represented by the functor
  &lt;functor-label&gt;.  The force was previously activated with a %force/v
  statement.  If no force was active on this functor the statement does
  nothing. The %release/net sends to the labeled functor the release
  command with net semantics: the unforced value is propagated to the
  output of the signal after the release is complete. The %release/reg
  sends the release command with reg semantics: the signal holds its
  forced value until another value propagates through.
  
  * %set/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  This sets a vector to a variable, and is used to implement blocking
  assignments. The &lt;var-label&gt; identifies the variable to receive the
  new value. Once the set completes, the value is immediately available
  to be read out of the variable. The &lt;bit&gt; is the address of the thread
  register that contains the LSB of the vector, and the &lt;wid&gt; is the
  size of the vector. The width must exactly match the width of the
  signal.
  
  * %set/mv &lt;memory-label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  This sets a thread vector to a memory word. The &lt;memory-label&gt;
  addresses a memory device, and the &lt;bit&gt;,&lt;wid&gt; describe a vector to be
  written. Index register 3 contains the address of the word within the
  memory. The address (in canonical form) is precalculated and loaded
  into index register 3.
  
  
  * %set/wr &lt;vpi-label&gt;, &lt;bit&gt;
  
  This instruction writes a real word to the specified VPI-like object.
  
  * %set/x0 &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
  
  This sets the part of a signal vector, the address calculated by
  using the index register 0 to index the base within the vector of
  &lt;var-label&gt;. The destination must be a signal of some sort. Otherwise,
  the instruction will fail.
  
  The addressing is canonical (0-based) so the compiler must figure out
  non-zero offsets, if any. The width is the width of the part being
  written. The other bits of the vector are not touched.
  
  The index may be signed, and if less then 0, the beginning bits are
  not assigned. Also, if the bits go beyond the end of the signal, those
  bits are not written anywhere.
  
  
  * %shiftl/i0 &lt;bit&gt;, &lt;wid&gt;
  
  This instruction shifts the vector left (towards more significant
  bits) by the amount in index register 0. The &lt;bit&gt; is the address of
  the lsb of the vector, and &lt;wid&gt; the width of the vector. The shift is
  done in place. Zero values are shifted in.
  
  * %shiftr/i0 &lt;bit&gt;, &lt;wid&gt;
  * %shiftr/s/i0 &lt;bit&gt;, &lt;wid&gt;
  
  This instruction shifts the vector right (towards the less significant
  bits) by the amount in the index register 0. The &lt;bit&gt; is the address
  of the lsb of the vector, and &lt;wid&gt; is the width of the vector. The
  shift is done in place.
  
  %shiftr/i0 is an unsigned down shift, so zeros are shifted into the
  top bits. %shiftr/s/i0 is a signed shift, so the value is sign-extended.
  
  * %sub &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  
  This instruction arithmetically subtracts the right vector out of the
  left vector. It accomplishes this by adding to the left vector 1 plus
  the 1s complement of the right vector. The carry value is dropped, and
  the result, placed in &lt;bit-l&gt;, is the subtraction of &lt;bit-r&gt; from the
  input &lt;bit-l&gt;. Both vectors have the same width. If any bits in either
  operand are x, then the entire result is x.
  
  See also the %add instruction.
  
  * %subi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
  
  This instruction arithmetically subtracts the immediate value from the
  left vector. The &lt;imm&gt; value is a 16bit unsigned value zero-extended to
  the &lt;wid&gt; of the left vector. The result replaces the left vector.
  
  See also the %addi instruction.
  
  
  * %sub/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  
  This instruction operates on real values in word registers. The right
  indexed value is subtracted from the left indexed value, and the
  result placed in the left index.
  
  
  * %vpi_call &lt;name&gt; [, ...]
  
  This instruction makes a call to a system task that was declared using
  VPI. The operands are compiled down to a vpiHandle for the call. The
  instruction contains only the vpiHandle for the call. See the vpi.txt
  file for more on system task/function calls.
  
  
  * %vpi_func &lt;name&gt;, &lt;dst&gt;, &lt;wid&gt; [, ...]
  
  This instruction is similar to %vpi_call, except that it is for
  calling system functions. The difference here is the &lt;dst&gt; and &lt;wid&gt;
  parameters that specify where the return value is to go. The normal
  means that the VPI code uses to write the return value causes those
  bits to go here.
  
  
  * %wait &lt;functor-label&gt;
  
  When a thread executes this instruction, it places itself in the
  sensitive list for the addressed functor. The functor holds all the
  threads that await the functor. When the defined sort of event occurs
  on the functor, a thread schedule event is created for all the threads
  in its list and the list is cleared.
  
  * %xnor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  This does a bitwise exclusive nor (~^) of the &lt;src&gt; and &lt;dst&gt; vector,
  and leaves the result in the &lt;dst&gt; vector. xnor is this:
  
  	0 xnor 0 --&gt; 1
  	0 xnor 1 --&gt; 0
  	1 xnor 0 --&gt; 0
  	1 xnor 1 --&gt; 1
  	otherwise    x
  
  
  * %xor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
  
  This does a bitwise exclusive or (^) of the &lt;src&gt; and &lt;dst&gt; vector,
  and leaves the result in the &lt;dst&gt; vector. xor is this:
  
  	0 xnor 0 --&gt; 0
  	0 xnor 1 --&gt; 1
  	1 xnor 0 --&gt; 1
  	1 xnor 1 --&gt; 0
  	otherwise    x
  
  
  /*
   * Copyright (c) 2001-2003 Stephen Williams (steve@xxxxxxxxxx)
   *
   *    This source code is free software; you can redistribute it
   *    and/or modify it in source code form under the terms of the GNU
   *    General Public License as published by the Free Software
   *    Foundation; either version 2 of the License, or (at your option)
   *    any later version.
   *
   *    This program is distributed in the hope that it will be useful,
   *    but WITHOUT ANY WARRANTY; without even the implied warranty of
   *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *    GNU General Public License for more details.
   *
   *    You should have received a copy of the GNU General Public License
   *    along with this program; if not, write to the Free Software
   *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
   */</pre>
  
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  <h1><a name="getting_started_with_icarus_verilog" id="getting_started_with_icarus_verilog">Getting Started with Icarus Verilog</a></h1>
  <div class="level1">
  <pre class="code">* Getting Started with Icarus Verilog
  
  Icarus Verilog is a Verilog compiler. It is suitable for use as a
  simulator, and, to some degree, synthesizer. Icarus Verilog runs under
  Linux and a variety of UNIX systems, as well as Windows as a command
  line tool, so the instructions are generally applicable to all
  environments. Note that this is only a quick start. For more detailed
  documentation, see the manual page for the iverilog command.
  
  
  * Hello, World!
  
  The first thing you want to do as a user is learn how to compile and
  execute even the most trivial design. For the purposes of simulation,
  we use as our example *the* most trivial simulation:
  
    module main;
  
    initial
      begin
        $display(&quot;Hello, World&quot;);
        $finish ;
      end
  
    endmodule
  
  By a text editor (or copy hello.vl from the Icarus Verilog examples
  directory) arrange for this program to be in a text file, &quot;hello.vl&quot;.
  Next, compile this program with a command like this:
  
  	% iverilog -o hello hello.vl
  
  The results of this compile are placed into the file &quot;hello&quot;, as the
  &quot;-o&quot; flag tells the compiler where to place the compiled result. Next,
  execute the compiled program like so:
  
  	% vvp hello
  	Hello, World
  
  And there it is, the program has been executed. So what happened? The
  first step, the &quot;iverilog&quot; command, read and interpreted the source
  file, then generated a compiled result. The compiled form may be
  selected by command line switches, but the default form is the VVP
  format, which is actually run by the &quot;vvp&quot; command.
  
  The &quot;iverilog&quot; and &quot;vvp&quot; commands are the only commands that users
  use to invoke Icarus Verilog. What the compiler actually does is
  controlled by command line switches. In our little example, we asked
  the compiler to compile the source program to the default vvp form,
  which is in turn executed by the vvp program.
  
  
  * Windows Install
  
  The easiest way to install under Windows is to get a precompiled
  installer for the version you wish to install. Icarus Verilog is
  distributed for Windows users as a self-installing .exe. Just execute
  the installer and follow the instructions. During the install, take
  note of the directory where the program is installed: for example,
  C:\iverilog is a good place to install.
  
  Once the binary is installed, you need to add the bin directory to
  your execution path. The executables you need are in C:\iverilog\bin,
  where the &quot;C:\iverilog&quot; part is actually the root of where you
  installed the package. The programs are in the bin subdirectory. Put
  this directory in your PATH environment variable, and the above
  commands become accessible to you at the command line prompt, or even
  in batch files.
  
  
  * Linux Install
  
  Under Linux, the install is even easier. For RedHat and Mandrake based
  systems, there is the appropriate RPM file. Just install the package
  with the &quot;rpm -U &lt;file&gt;&quot; command. Debian users should get Icarus
  Verilog packages from the main Debian software site.
  
  
  * Install From Source
  
  In this case, see README.txt and other documentation that comes with
  the source.</pre>
  
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  <h1><a name="the_icarus_verilog_compilation_system" id="the_icarus_verilog_compilation_system">The Icarus Verilog Compilation System</a></h1>
  <div class="level1">
  <pre class="code">		THE ICARUS VERILOG COMPILATION SYSTEM
  		Copyright 2000-2004 Stephen Williams
  
  
  1.0 What is ICARUS Verilog?
  
  Icarus Verilog is intended to compile ALL of the Verilog HDL as
  described in the IEEE-1364 standard. Of course, it's not quite there
  yet. It does currently handle a mix of structural and behavioral
  constructs. For a view of the current state of Icarus Verilog, see its
  home page at &lt;http://www.icarus.com/eda/verilog&gt;.
  
  Icarus Verilog is not aimed at being a simulator in the traditional
  sense, but a compiler that generates code employed by back-end
  tools. These back-end tools currently include a simulator engine
  called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF FPGA
  netlist generator. In the future, backends are expected for EDIF/LPM,
  structural Verilog, VHDL, etc.
  
      For instructions on how to run Icarus Verilog,
      see the ``iverilog'' man page.
  
  
  2.0 Building/Installing Icarus Verilog From Source
  
  If you are starting from source, the build process is designed to be
  as simple as practical. Someone basically familiar with the target
  system and C/C++ compilation should be able to build the source
  distribution with little effort. Some actual programming skills are
  not required, but helpful in case of problems.
  
  If you are building for Windows, see the mingw.txt file.
  
  2.1 Compile Time Prerequisites
  
  You need the following software to compile Icarus Verilog from source
  on a UNIX-like system:
  
  	- GNU Make
  	  The Makefiles use some GNU extensions, so a basic POSIX
  	  make will not work. Linux systems typically come with a
  	  satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD)
  	  typically have GNU make as the gmake program.
  
  	- ISO C++ Compiler
  	  The ivl and ivlpp programs are written in C++ and make use
  	  of templates and some of the standard C++ library. egcs and
  	  recent gcc compilers with the associated libstdc++ are known
  	  to work. MSVC++ 5 and 6 are known to definitely *not* work.
  
  	- bison and flex
  
  	- gperf 2.7
  	  The lexical analyzer doesn't recognize keywords directly,
  	  but instead matches symbols and looks them up in a hash
  	  table in order to get the proper lexical code. The gperf
  	  program generates the lookup table.
  
  	  A version problem with this program is the most common cause
  	  of difficulty. See the Icarus Verilog FAQ.
  
  	- readline 4.2
  	  On Linux systems, this usually means the readline-devel
  	  rpm. In any case, it is the development headers of readline
  	  that are needed.
  
  	- termcap
  	  The readline library in turn uses termcap.
  
  If you are building from CVS, you will also need software to generate
  the configure scripts.
  
  	- autoconf 2.53
  	  This generates configure scripts from configure.in. The 2.53
  	  or later versions are known to work, autoconf 2.13 is
  	  reported to *not* work.
  
  2.2 Compilation
  
  Unpack the tar-ball and cd into the verilog-######### directory
  (presumably that is how you got to this README) and compile the source
  with the commands:
  
    ./configure
    make
  
  Normally, this command automatically figures out everything it needs
  to know. It generally works pretty well. There are a few flags to the
  configure script that modify its behavior:
  
  	--without-ipal
  	    This turns off support for Icarus PAL, whether ipal
  	    libraries are installed or not.
  
  	--prefix=&lt;root&gt;
  	    The default is /usr/local, which causes the tool suite to
  	    be compiled for install in /usr/local/bin,
  	    /usr/local/share/ivl, etc.
  
  	    I recommend that if you are configuring for precompiled
  	    binaries, use --prefix=/usr.  On Solaris systems, it is
  	    common to use --prefix=/opt.  You can configure for a non-root
  	    install with --prefix=$HOME.
  
  	--enable-vvp32 (experimental)
  	    If compiling on AMD64 systems, this enables the
  	    compilation of 32bit compatible vvp (vvp32) and the vpi
  	    modules that match.
  
  2.2.1 Special AMD64 Instructions
  
  (The Icarus Verilog RPM for x86_64 is build using these instructions.)
  
  If you are building for Linux/AMD64 (a.k.a x86_64) then to get the
  most out of your install, first make sure you have both 64bit and
  32bit development libraries installed. Then configure with this
  somewhat more complicated command:
  
    ./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32
  
  This reflects the convention on AMD64 systems that 64bit libraries go
  into lib64 directories. The &quot;--enable-vvp32&quot; also turns on 32bit
  compatibility files. A 32bit version of vvp (vvp32) will be created,
  as well as 32bit versions of the development libraries and bundled VPI
  libraries.
  
  2.3 (Optional) Testing
  
  To run a simple test before installation, execute
  
    make check
  
  The commands printed by this run might help you in running Icarus
  Verilog on your own Verilog sources before the package is installed
  by root.
  
  2.4 Installation
  
  Now install the files in an appropriate place. (The makefiles by
  default install in /usr/local unless you specify a different prefix
  with the --prefix=&lt;path&gt; flag to the configure command.) You may need
  to do this as root to gain access to installation directories.
  
    make install
  
  2.5 Uninstallation
  
  The generated Makefiles also include the uninstall target. This should
  remove all the files that ``make install'' creates.
  
  3.0 How Icarus Verilog Works
  
  This tool includes a parser which reads in Verilog (plus extensions)
  and generates an internal netlist. The netlist is passed to various
  processing steps that transform the design to more optimal/practical
  forms, then is passed to a code generator for final output. The
  processing steps and the code generator are selected by command line
  switches.
  
  3.1 Preprocessing
  
  There is a separate program, ivlpp, that does the preprocessing. This
  program implements the `include and `define directives producing
  output that is equivalent but without the directives. The output is a
  single file with line number directives, so that the actual compiler
  only sees a single input file. See ivlpp/ivlpp.txt for details.
  
  3.2 Parse
  
  The Verilog compiler starts by parsing the Verilog source file. The
  output of the parse is a list of Module objects in &quot;pform&quot;. The pform
  (see pform.h) is mostly a direct reflection of the compilation
  step. There may be dangling references, and it is not yet clear which
  module is the root.
  
  One can see a human readable version of the final pform by using the
  ``-P &lt;path&gt;'' flag to the compiler. This will cause iverilog to dump
  the pform into the file named &lt;path&gt;.
  
  3.3 Elaboration
  
  This phase takes the pform and generates a netlist. The driver selects
  (by user request or lucky guess) the root module to elaborate,
  resolves references and expands the instantiations to form the design
  netlist. (See netlist.txt.) Final semantic checks are performed during
  elaboration, and some simple optimizations are performed. The netlist
  includes all the behavioral descriptions, as well as gates and wires.
  
  The elaborate() function performs the elaboration.
  
  One can see a human readable version of the final, elaborated and
  optimized netlist by using the ``-N &lt;path&gt;'' flag to the compiler. If
  elaboration succeeds, the final netlist (i.e., after optimizations but
  before code generation) will be dumped into the file named &lt;path&gt;.
  
  Elaboration is actually performed in two steps: scopes and parameters
  first, followed by the structural and behavioral elaboration.
  
  3.3.1 Scope Elaboration
  
  This pass scans through the pform looking for scopes and parameters. A
  tree of NetScope objects is built up and placed in the Design object,
  with the root module represented by the root NetScope object. The
  elab_scope.cc and elab_pexpr.cc files contain most of the code for
  handling this phase.
  
  The tail of the elaborate_scope behavior (after the pform is
  traversed) includes a scan of the NetScope tree to locate defparam
  assignments that were collected during scope elaboration. This is when
  the defparam overrides are applied to the parameters.
  
  3.3.2 Netlist Elaboration
  
  After the scopes and parameters are generated and the NetScope tree
  fully formed, the elaboration runs through the pform again, this time
  generating the structural and behavioral netlist. Parameters are
  elaborated and evaluated by now so all the constants of code
  generation are now known locally, so the netlist can be generated by
  simply passing through the pform.
  
  3.4 Optimization
  
  This is actually a collection of processing steps that perform
  optimizations that do not depend on the target technology. Examples of
  some useful transformations are
  
  	- eliminate null effect circuitry
  	- combinational reduction
  	- constant propagation
  
  The actual functions performed are specified on the ivl command line by
  the -F flags (see below).
  
  3.5 Code Generation
  
  This step takes the design netlist and uses it to drive the code
  generator (see target.h). This may require transforming the
  design to suit the technology.
  
  The emit() method of the Design class performs this step. It runs
  through the design elements, calling target functions as need arises
  to generate actual output.
  
  The user selects the target code generator with the -t flag on the
  command line.
  
  3.6 ATTRIBUTES
  
      NOTE: The $attribute syntax will soon be deprecated in favor of the
      Verilog-2001 attribute syntax, which is cleaner and standardized.
  
  The parser accepts, as an extension to Verilog, the $attribute module
  item. The syntax of the $attribute item is:
  
  	$attribute (&lt;identifier&gt;, &lt;key&gt;, &lt;value&gt;);
  
  The $attribute keyword looks like a system task invocation. The
  difference here is that the parameters are more restricted then those
  of a system task. The &lt;identifier&gt; must be an identifier. This will be
  the item to get an attribute. The &lt;key&gt; and &lt;value&gt; are strings, not
  expressions, that give the key and the value of the attribute to be
  attached to the identified object.
  
  Attributes are [&lt;key&gt; &lt;value&gt;] pairs and are used to communicate with
  the various processing steps. See the documentation for the processing
  step for a list of the pertinent attributes.
  
  Attributes can also be applied to gate types. When this is done, the
  attribute is given to every instantiation of the primitive. The syntax
  for the attribute statement is the same, except that the &lt;identifier&gt;
  names a primitive earlier in the compilation unit and the statement is
  placed in global scope, instead of within a module. The semicolon is
  not part of a type attribute.
  
  Note that attributes are also occasionally used for communication
  between processing steps. Processing steps that are aware of others
  may place attributes on netlist objects to communicate information to
  later steps.
  
  Icarus Verilog also accepts the Verilog 2001 syntax for
  attributes. They have the same general meaning as with the $attribute
  syntax, but they are attached to objects by position instead of by
  name. Also, the key is a Verilog identifier instead of a string.
  
  4.0 Running iverilog
  
  The preferred way to invoke the compiler is with the iverilog(1)
  command. This program invokes the preprocessor (ivlpp) and the
  compiler (ivl) with the proper command line options to get the job
  done in a friendly way. See the iverilog(1) man page for usage details.
  
  
  4.1 EXAMPLES
  
  Example: Compiling &quot;hello.vl&quot;
  
  ------------------------ hello.vl ----------------------------
  module main();
  
  initial
    begin
      $display(&quot;Hi there&quot;);
      $finish ;
    end
  
  endmodule
  
  --------------------------------------------------------------
  
  Ensure that &quot;iverilog&quot; is on your search path, and the vpi library
  is available.
  
  To compile the program:
  
    iverilog hello.vl
  
  (The above presumes that /usr/local/include and /usr/local/lib are
  part of the compiler search path, which is usually the case for gcc.)
  
  To run the program:
  
    ./a.out
  
  You can use the &quot;-o&quot; switch to name the output command to be generated
  by the compiler. See the iverilog(1) man page.
  
  5.0 Unsupported Constructs
  
  Icarus Verilog is in development - as such it still only supports a
  (growing) subset of Verilog.  Below is a description of some of the
  currently unsupported Verilog features. This list is not exhaustive,
  and does not account for errors in the compiler. See the Icarus
  Verilog web page for the current state of support for Verilog, and in
  particular, browse the bug report database for reported unsupported
  constructs.
  
    - System functions are supported, but the return value is a little
      tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page.
  
    - Specify blocks are parsed but ignored in general.
  
    - trireg is not supported. tri0 and tri1 are supported.
  
    - tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
      and rtranif0 are not supported.
  
    - Net delays, of the form &quot;wire #N foo;&quot; do not work. Delays in
      every other context do work properly, including the V2001 form
      &quot;wire #5 foo = bar;&quot;
  
    - Event controls inside non-blocking assignments are not supported.
      i.e.: a &lt;= @(posedge clk) b;
  
    - Macro arguments are not supported. `define macros are supported,
      but they cannot take arguments.
  
  5.1 Nonstandard Constructs or Behaviors
  
  Icarus Verilog includes some features that are not part of the
  IEEE1364 standard, but have well defined meaning, and also sometimes
  gives nonstandard (but extended) meanings to some features of the
  language that are defined. See the &quot;extensions.txt&quot; documentation for
  more details.
  
      $is_signed(&lt;expr&gt;)
  	This system function returns 1 if the expression contained is
  	signed, or 0 otherwise. This is mostly of use for compiler
  	regression tests.
  
      $sizeof(&lt;expr&gt;)
      $bits(&lt;expr&gt;)
  	The $bits system function returns the size in bits of the
  	expression that is its argument. The result of this
  	function is undefined if the argument doesn't have a
  	self-determined size.
  
  	The $sizeof function is deprecated in favor of $bits, which is
  	the same thing, but included in the SystemVerilog definition.
  
      $simtime
  	The $simtime system function returns as a 64bit value the
  	simulation time, unscaled by the time units of local
  	scope. This is different from the $time and $stime functions
  	which return the scaled times. This function is added for
  	regression testing of the compiler and run time, but can be
  	used by applications who really want the simulation time.
  
  	Note that the simulation time can be confusing if there are
  	lots of different `timescales within a design. It is not in
  	general possible to predict what the simulation precision will
  	turn out to be.
  
      $mti_random()
      $mti_dist_uniform
  	These functions are similar to the IEEE1364 standard $random
  	functions, but they use the Mersenne Twister (MT19937)
  	algorithm. This is considered an excellent random number
  	generator, but does not generate the same sequence as the
  	standardized $random.
  
      Builtin system functions
  
  	Certain of the system functions have well defined meanings, so
  	can theoretically be evaluated at compile time, instead of
  	using runtime VPI code. Doing so means that VPI cannot
  	override the definitions of functions handled in this
  	manner. On the other hand, this makes them synthesizable, and
  	also allows for more aggressive constant propagation. The
  	functions handled in this manner are:
  
  		$bits
  		$signed
  		$sizeof
  		$unsigned
  
  	Implementations of these system functions in VPI modules will
  	be ignored.
  
      Preprocessing Library Modules
  
  	Icarus Verilog does preprocess modules that are loaded from
  	libraries via the -y mechanism. However, the only macros
  	defined during compilation of that file are those that it
  	defines itself (or includes) or that are defined on the
  	command line or command file.
  
  	Specifically, macros defined in the non-library source files
  	are not remembered when the library module is loaded. This is
  	intentional. If it were otherwise, then compilation results
  	might vary depending on the order that libraries are loaded,
  	and that is too unpredictable.
  
  	It is said that some commercial compilers do allow macro
  	definitions to span library modules. That's just plain weird.
  
      Width in %t Time Formats
  
  	Standard Verilog does not allow width fields in the %t formats
  	of display strings. For example, this is illegal:
  
  		$display(&quot;Time is %0t&quot;, %time);
  
  	Standard Verilog instead relies on the $timeformat to
  	completely specify the format.
  
  	Icarus Verilog allows the programmer to specify the field
  	width. The &quot;%t&quot; format in Icarus Verilog works exactly as it
  	does in standard Verilog. However, if the programmer chooses
  	to specify a minimum width (i.e., &quot;%5t&quot;), then for that display
  	Icarus Verilog will override the $timeformat minimum width and
  	use the explicit minimum width.
  
      vpiScope iterator on vpiScope objects.
  
  	In the VPI, the normal way to iterate over vpiScope objects
  	contained within a vpiScope object, is the vpiInternalScope
  	iterator. Icarus Verilog adds support for the vpiScope
  	iterator of a vpiScope object, that iterates over *everything*
  	the is contained in the current scope. This is useful in cases
  	where one wants to iterate over all the objects in a scope
  	without iterating over all the contained types explicitly.
  
      time 0 race resolution.
  
  	Combinational logic is routinely modeled using always
  	blocks. However, this can lead to race conditions if the
  	inputs to the combinational block are initialized in initial
  	statements. Icarus Verilog slightly modifies time 0 scheduling
  	by arranging for always statements with ANYEDGE sensitivity
  	lists to be scheduled before any other threads. This causes
  	combinational always blocks to be triggered when the values in
  	the sensitivity list are initialized by initial threads.
  
      Nets with Types
  
  	Icarus Verilog support an extension syntax that allows nets
  	and regs to be explicitly typed. The currently supported types
  	are logic, bool and real. This implies that &quot;logic&quot; and &quot;bool&quot;
  	are new keywords. Typical syntax is:
  
  	wire real foo = 1.0;
  	reg logic bar, bat;
  
  	... and so forth. The syntax can be turned off by using the
  	-g2 flag to iverilog, and turned on explicitly with the -g2x
  	flag to iverilog.
  
  6.0 CREDITS
  
  Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
  Copyright Stephen Williams. The proper notices are in the head of each
  file. However, I have early on received aid in the form of fixes,
  Verilog guidance, and especially testing from many people. Testers in
  particular include a larger community of people interested in a GPL
  Verilog for Linux.</pre>
  
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  <h1><a name="compile_front_end_for_vpi_modules_man-page" id="compile_front_end_for_vpi_modules_man-page">Compile front end for VPI modules man-page</a></h1>
  <div class="level1">
  <pre class="code">iverilog-vpi(1)		 $Date: 2006/08/22 02:56:12 $	       iverilog-vpi(1)
  
  
  
  NAME
         iverilog-vpi - Compile front end for VPI modules
  
  
  SYNOPSIS
         iverilog-vpi [--name=name] sourcefile...
  
  
  DESCRIPTION
         iverilog-vpi  is	 a tool to simplify the compilation of VPI modules for
         use with Icarus Verilog. It takes on the command line a list  of	 C  or
         C++  source files, and generates as output a linked VPI module. See the
         vvp(1) man page for a description of how the linked module is loaded by
         a simulation.
  
         The  output  is	named after the first source file. For example, if the
         first source file is named foo.c, the output becomes foo.vpi.
  
  
  OPTIONS
         iverilog-vpi accepts the following options:
  
         -llibrary
  	       Include the named library in the link of the VPI	 module.  This
  	       allows VPI modules to further reference external libraries.
  
  
         --name=name
  	       Normally,  the  output VPI module will be named after the first
  	       source file passed to the command.  This	 flag  sets  the  name
  	       (without the .vpi suffix) of the output vpi module.
  
  
         --install-dir
  	       This flag causes the program to print the install directory for
  	       VPI modules, then exit. It is a convenience  for	 makefiles  or
  	       automated plug-in installers.
  
  
  PC-ONLY OPTIONS
         The  PC	port of iverilog-vpi includes two special flags needed to sup-
         port the more intractable development environment. These flags help the
         program locate parts that it needs.
  
  
         -mingw=path
  	       Tell the program the root of the Mingw compiler tool suite. The
  	       vvp runtime is compiled with this compiler,  and	 this  is  the
  	       compiler	 that  iverilog-vpi  expects  to  use  to compile your
  	       source code. This is normally not needed, and if you do use it,
  	       it  is only needed once. The compiler will save the path in the
  	       registry for use later.
  
  
         -ivl=path
  	       Set for the use during compilation the root if the Icarus  Ver-
  	       ilog install. This is the place where you installed Icarus Ver-
  	       ilog when you ran the installer. This flag is also only	needed
  	       once, and the path is stored in the registry for future use.
  
  
  UNIX-ONLY OPTIONS
         The UNIX version of iverilog-vpi includes additional flags to let Make-
         file gurus peek at the  configuration  of  the  iverilog	 installation.
         This  way,  Makefiles  can  be  written	that handle complex VPI builds
         natively, and without hard-coding values that depend on the system  and
         installation.   If  used	 at  all,  these options must be used one at a
         time, and without any other options or directives.
  
  
         --cflags
  	       Print the compiler flags (CFLAGS or CXXFLAGS) needed to compile
  	       source code destined for a VPI module.
  
  
         --ldflags
  	       Print the linker flags (LDFLAGS) needed to link a VPI module.
  
  
         --ldlibs
  	       Print the libraries (LDLIBS) needed to link a VPI module.
  
  
         -m32    On  64bit systems that support it (and support vvp32) this flag
  	       requests a 32bit	 vpi  binary  instead  of  the	default	 64bit
  	       binary.
  
  
         Example GNU makefile that takes advantage of these flags:
  
  	   CFLAGS = -Wall -O $(CFLAGS_$@)
  	   VPI_CFLAGS := $(shell iverilog-vpi --cflags)
  	   CFLAGS_messagev.o = $(VPI_CFLAGS)
  	   CFLAGS_fifo.o = $(VPI_CFLAGS)
  	   messagev.o fifo.o: transport.h
  	   messagev.vpi: messagev.o fifo.o
  		iverilog-vpi $^
  
  
  AUTHOR
         Steve Williams (steve@xxxxxxxxxx)
  
  
  SEE ALSO
         iverilog(1),	   vvp(1),	 &lt;http://www.icarus.com/eda/verilog/&gt;,
         &lt;http://www.mingw.org&gt;,
  
  
  COPYRIGHT
         Copyright Ã?Â©  2002 Stephen Williams
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  Version			 $Date: 2006/08/22 02:56:12 $	       iverilog-vpi(1)</pre>
  
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  <h1><a name="vpi_within_vvp" id="vpi_within_vvp">VPI_within_VVP</a></h1>
  <div class="level1">
  <pre class="code">/*
   * Copyright (c) 2001 Stephen Williams (steve@xxxxxxxxxx)
   *
   *  $Id: geda_icarus_vpi_within_vvp.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
   */
  
  
  VPI WITHIN VVP
  
  System tasks and functions in Verilog are implemented in Icarus
  Verilog by C routines written with VPI. This implies that the vvp
  engine must provide at least a subset of the Verilog VPI
  interface. The minimalist concepts of vvp, however, make the method
  less then obvious.
  
  Within a Verilog design, there is a more or less fixed web of
  vpiHandles that is the design database as is available to VPI
  functions. The Verilog standard defines quite a lot of types, but the
  vvp only implements the ones it needs. The VPI web is added into the
  design using special pseudo-ops that create the needed objects.
  
  
  LOADING VPI MODULES
  
  The vvp runtime loads VPI modules at runtime before the parser reads
  in the source files. This gives the modules a chance to register tasks
  and functions before the source is compiled. This allows the compiler
  to resolve references to system tasks and system functions to a
  vpiHandle at compile time. References to missing tasks/function can
  thus be caught before the simulation is run.
  
       NOTE: This also, miraculously, allows for some minimal support of
       the compiletf call. From the perspective of VPI code, compilation
       of the VVP source is not unlike compilation of the original
       Verilog.
  
  The handle that the vvp threads have to the VPI are the vpiHandles of
  the system tasks and functions. The %vpi_call instruction, once compiled,
  carries the vpiHandle of the system task.
  
  
  SYSTEM TASK CALLS
  
  A system task call invokes a VPI routine, and makes available to that
  routine the arguments to the system task. The called routine gets
  access to the system task call by calling back the VPI requesting the
  handle. It uses the handle, in turn, to get hold of the operands for
  the task.
  
  All that vvp needs to know about a system task call is the handle of
  the system task definitions (created by the vpi_register_systf
  function) and the arguments of the actual call. The arguments are
  tricky because the list has no bound, even though each particular call
  in the Verilog source has a specific set of parameters.
  
  Since each call takes a fixed number of parameters, the input source
  can include in the statement the list of arguments. The argument list
  will not fit in a single generated instruction, but a vpiHandle that
  refers to a vpiSysTfCall does. Therefore, the compiler can take the
  long argument list and form a vpiSysTaskCall object. The generated
  instruction then only needs to be a %vpi_call with the single parameter
  that is the vpiHandle for the call.
  
  
  SYSTEM FUNCTION CALLS
  
  System function calls are similar to system tasks. The only
  differences are that all the arguments are input only, and there is a
  single magic output that is the return value. The same %vpi_call can
  even be used to call a function.
  
  System functions, like system tasks, can only be called from thread
  code. However, they can appear in expressions, even when that
  expression is entirely structural. The desired effect is achieved by
  writing a wrapper thread that calls the function when inputs change,
  and that writes the output into the containing expression.
  
  
  SYSTEM TASK/FUNCTION ARGUMENTS
  
  The arguments to each system task or call are not stored in the
  instruction op-code, but in the vpiSysTfCall object that the compiler
  creates and that the %vpi_call instruction ultimately refers to. All
  the arguments must be some sort of object that can be represented by a
  vpiHandle at compile time.
  
  Arguments are handled at compile time by the parser, which uses the
  argument_list rule to build a list of vpiHandle objects. Each argument
  in the argument_list invokes whatever function is appropriate for the
  token in order to make a vpiHandle object for the argument_list. When
  all this is done, an array of vpiHandles is passed to code to create a
  vpiSysTfCall object that has all that is needed to make the call.
  
  
  SCOPES
  
  VPI can access scopes as objects of type vpiScope. Scopes have names
  and can also contain other sub-scopes, all of which the VPI function
  can access by the vpiInternalScope reference. Therefore, the run-time
  needs to form a tree of scopes into which other scoped VPI objects are
  placed.
  
  A scope is created with a .scope directive, like so:
  
  	&lt;label&gt; .scope &quot;name&quot; [, &lt;parent&gt;];
  		.timescale &lt;units&gt;;
  
  The scope takes a string name as the first parameter. If there is an
  additional parameter, it is a label of the directive for the parent
  scope. Scopes that have no parent are root scopes. It is an error to
  declare a scope with the same name more then once in a parent scope.
  
  The name string given when creating the scope is the basename for the
  scope. The vvp automatically constructs full names from the scope
  hierarchy, and runtime VPI code can access that full name with the
  vpiFullname reference.
  
  The .timescale directive changes the scope units from the simulation
  precision to the specified precision. The .timescale directive affects
  the current scope.
  
  Objects that place themselves in a scope place themselves in the
  current scope. The current scope is the one that was last mentioned by
  a .scope directive. If the wrong scope is current, the label on a
  scope directive can be used to resume a scope. The syntax works like
  this:
  
  		.scope &lt;symbol&gt;;
  
  In this case, the &lt;symbol&gt; is the label of a previous scope directive,
  and is used to identify the scope to be resumed. A scope resume
  directive cannot have a label.
  
  
  VARIABLES
  
  Reg vectors (scalars are vectors of length 1) are created by .var
  statements in the source. The .var statement includes the declared
  name of the variable, and the indices of the MSB and LSB of the
  vector. The vpiHandle is then created with this information, and the
  vpi_ipoint_t pointer to the LSB functor of the variable. VPI programs
  access the vector through the vpiHandle and related functions. The VPI
  code gets access to the declared indices.
  
  The VPI interface to variable (vpiReg objects) uses the MSB and LSB
  values that the user defined to describe the dimensions of the
  object.
  
  /*
   * Copyright (c) 2001 Stephen Williams (steve@xxxxxxxxxx)
   *
   *    This source code is free software; you can redistribute it
   *    and/or modify it in source code form under the terms of the GNU
   *    General Public License as published by the Free Software
   *    Foundation; either version 2 of the License, or (at your option)
   *    any later version.
   *
   *    This program is distributed in the hope that it will be useful,
   *    but WITHOUT ANY WARRANTY; without even the implied warranty of
   *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *    GNU General Public License for more details.
   *
   *    You should have received a copy of the GNU General Public License
   *    along with this program; if not, write to the Free Software
   *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
   */</pre>
  
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  <h1><a name="icarus_verilog_vvp_runtime_engine_man-page" id="icarus_verilog_vvp_runtime_engine_man-page">Icarus Verilog vvp runtime engine man-page</a></h1>
  <div class="level1">
  <pre class="code">vvp(1)			 $Date: 2006/08/22 02:56:12 $			vvp(1)
  
  
  
  NAME
         vvp - Icarus Verilog vvp runtime engine
  
  
  SYNOPSIS
         vvp  [-sv] [-Mpath] [-mmodule] [-llogfile] inputfile [extended-args...]
  
  
  DESCRIPTION
         vvp is the run time engine that executes the default compiled form gen-
         erated  by  Icarus Verilog. The output from the iverilog command is not
         by itself executable on any  platform.  Instead,	 the  vvp  program  is
         invoked to execute the generated output file.
  
  
  OPTIONS
         vvp accepts the following options:
  
         -llogfile
  	       This  flag  specifies  a	 logfile where all MCI &lt;stdlog&gt; output
  	       goes.  Specify logfile as Ã¢â?¬â?¢-Ã¢â?¬â?¢ to send log output	 to  &lt;stderr&gt;.
  	       $display	 and  friends  send  their output both to &lt;stdout&gt; and
  	       &lt;stdlog&gt;.
  
         -Mpath  This flag adds a directory to the path list used to locate  VPI
  	       modules.	 The  default path includes only the install directory
  	       for the system.vpi module, but this flag can add other directo-
  	       ries.  Multiple paths are allowed, and modules will be searched
  	       in order.
  
         -mmodule
  	       Tell the vvp run time to load the named module before executing
  	       the simulation. The system.vpi module is loaded by default, but
  	       additional  modules,  including	modules	 that	you   compiled
  	       locally, can be specified with this flag. Any number of modules
  	       can be loaded, and they will be linked in the  order  they  are
  	       listed on the command line.
  
  	       Normally,  you  only  need  to  specify the name of the module,
  	       without any directory path or .vpi suffix and the  search  path
  	       is scanned to find the module. However, if the name includes at
  	       least one directory character, then  the	 search	 path  is  not
  	       scanned and the name is assumed to be a complete file name.
  
         -s      Stop.  This will cause the simulation to stop in the beginning,
  	       before any events are scheduled. This  allows  the  interactive
  	       user to get hold of the simulation just before it starts.
  
         -v      Turn on verbose messages. This will cause information about run
  	       time progress to be printed to standard out.
  
  
  EXTENDED ARGUMENTS
         The vvp options described above must come before the design file	 name.
         After the design file name, however, there may be any number of unspec-
         ified arguments. These arguments are not interpreted  by	 vvp  but  are
         instead	passed	on  to	the executed design, and are available via the
         $test$plusargs and $value$plusargs system functions.
  
         Arguments that do not start with the plus(+) character are  not	avail-
         able  to	 the $plusargs system tasks, but can still be accessed via PLI
         code via the vpi_get_vlog_info function. This means  that  vpi  modules
         may  use arguments that do not start with + and be assured that they do
         not interfere with user defined plus-args.
  
         There are a few extended arguments that are interpreted by the standard
         system.vpi module, which implements the standard system tasks and so is
         always included. These arguments are described here.
  
         -vcd|-vcd-none
  	       This extended argument sets the wave dump format to  VCD.  This
  	       is  the	default in the absence of any IVERILOG_DUMPER environ-
  	       ment variable. The VCD dump files are large and ponderous,  but
  	       are  also maximally compatible with third party tools that read
  	       waveform dumps.
  
         The -vcd-none variant actually suppresses all waveform output. This can
         make long simulations run faster.
  
  
         -lxt|-lxt-speed|-lxt-space|-lxt-none
  	       These  extended arguments set the wave dump format to lxt, pos-
  	       sibly with format optimizations. The -lxt-space flag  sets  the
  	       output format to lxt with full compression enabled. The result-
  	       ing files are quite small. The -lxt-speed chooses the lxt  com-
  	       pression	 mode  that  leads  to the best execution time and the
  	       fastest read time, at the expense of some file size.
  
         The -lxt-none variant actually suppresses all waveform output. This can
         make long simulations run faster.
  
  
         -lxt2   The  LXT2 format is slower then LXT (faster then VCD) but takes
  	       less space, and is written out  incrementally.  Thus,  you  can
  	       view lxt2 files while a simulation is still running (or paused)
  	       or if your simulation crashes or is killed, you	still  have  a
  	       useful dump.
  
  
  ENVIRONMENT
         The  vvp	 command  also accepts some environment variables that control
         its behavior. These can be used to make semi-permanent changes.
  
  
         IVERILOG_DUMPER=lxt|lxt2|vcd|none
  	       This selects the output format for the  waveform	 output.  Nor-
  	       mally,  waveforms  are  dumped in vcd format, but this variable
  	       can be used to select lxt format, which is  far	more  compact,
  	       though limited to gtkwave or compatible viewers. It can also be
  	       used to suppress VCD output, a time-saver for regression tests.
  
  
  INTERACTIVE MODE
         The simulation engine supports an interactive mode. The user may inter-
         rupt the simulation (typically by typing Ctrl-C) to get to the interac-
         tive  prompt. From that prompt, the help command prints a brief summary
         of the available commands.
  
         The interactive mode may also be entered by a call to the $stop	system
         task  from  within  the simulation, or by a call to the vpi_control VPI
         function with the vpiStop control argument.  These  means  of  entering
         interactive mode are equivalent.
  
  
  AUTHOR
         Steve Williams (steve@xxxxxxxxxx)
  
  
  SEE ALSO
         iverilog(1), iverilog-vpi(1), &lt;http://www.icarus.com/eda/verilog/&gt;
  
  
  COPYRIGHT
         Copyright Ã?Â©  2001-2003 Stephen Williams
  
         This document can be freely redistributed according to the terms of the
         GNU General Public License version 2.0
  
  
  
  Version			 $Date: 2006/08/22 02:56:12 $			vvp(1)</pre>
  
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  <h1><a name="vvp_simulation_engine" id="vvp_simulation_engine">VVP Simulation Engine</a></h1>
  <div class="level1">
  <pre class="code">/*
   * Copyright (c) 2001 Stephen Williams (steve@xxxxxxxxxx)
   *
   *  $Id: geda_icarus_vvp_simulation.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
   */
  
  VVP SIMULATION ENGINE
  
  The VVP simulator takes as input source code not unlike assembly
  language for a conventional processor. It is intended to be machine
  generated code emitted by other tools, including the Icarus Verilog
  compiler, so the syntax, though readable, is not necessarily
  convenient for humans.
  
  
  GENERAL FORMAT
  
  The source file is a collection of statements. Each statement may have
  a label, an opcode, and operands that depend on the opcode. For some
  opcodes, the label is optional (or meaningless) and for others it is
  required.
  
  Every statement is terminated by a semicolon. The semicolon is also
  the start of a comment line, so you can put comment text after the
  semicolon that terminates a statement. Like so:
  
  	Label .functor and, 0x5a, x, y  ; This is a comment.
  
  The semicolon is required, whether the comment is there or not.
  
  Statements may span multiple lines, as long as there is no text (other
  then the first character of a label) in the first column of the
  continuation line.
  
  HEADER SYNTAX
  
  Before any other non-commentary code starts, the source may contain
  some header statements. These are used for passing parameters or
  global details from the compiler to the vvp run-time. In all cases,
  the header statement starts with a left-justified keyword.
  
  * :module &quot;name&quot; ;
  
  This header statement names a vpi module that vvp should load before
  the rest of the program is compiled. The compiler looks in the
  standard VPI_MODULE_PATH for files named &quot;name.vpi&quot;, and tries to
  dynamic load them.
  
  * :vpi_time_precision [+|-]&lt;value&gt;;
  
  This header statement specifies the time precision of a single tick of
  the simulation clock. This is mostly used for display (and VPI)
  purposes, because the engine itself does not care about units. The
  compiler scales time values ahead of time.
  
  The value is the size of a simulation tick in seconds, and is
  expressed as a power of 10. For example, +0 is 1 second, and -9 is 1
  nanosecond. If the record is left out, then the precision is taken to
  be +0.
  
  LABELS AND SYMBOLS
  
  Labels and symbols consist of the characters:
  
  	a-z
  	A-Z
  	0-9
  	.$_&lt;&gt;
  
  Labels and symbols may not start with a digit or a '.', so that they
  are easily distinguished from keywords and numbers. A Label is a
  symbol that starts a statement. If a label is present in a statement,
  it must start in the first text column. This is how the lexical
  analyzer distinguishes a label from a symbol. If a symbol is present
  in a statement, it is in the operand. Opcodes of statements must be a
  keyword.
  
  Symbols are references to labels. It is not necessary for a label to
  be declared before its use in a symbol, but it must be declared
  eventually. When symbols refer to functors, the symbol represents the
  vvp_ipoint_t pointer to the output. (Inputs cannot, and need not, be
  references symbolically.)
  
  If the functor is part of a vector, then the symbol is the
  vvp_ipoint_t for the first functor. The [] operator can then be used
  to reference a functor other then the first in the vector.
  
  There are some special symbols that in certain contexts have special
  meanings. As inputs to functors, the symbols &quot;C&lt;0&gt;&quot;, &quot;C&lt;1&gt;&quot;, &quot;C&lt;x&gt;&quot;
  and &quot;C&lt;z&gt;&quot; represent a constant driver of the given value.
  
  
  SCOPE STATEMENTS:
  
  
  PARAMETER STATEMENTS:
  
  Parameters are named constants within a scope. These parameters have a
  type and value, and also a label so that they can be referenced as VPI
  objects.
  
  The syntax of a parameter is:
  
  	&lt;label&gt; .param &lt;name&gt;, &lt;type&gt;, &lt;value&gt;;
  
  The &lt;name&gt; is a string that names the parameter. The name is placed in
  the current scope as a vpiParameter object. The &lt;type&gt; is one of the
  following:
  
  	real          -- The parameter has a real value
  	string        -- The parameter has a string value
  	[&lt;msb&gt;,&lt;lsb&gt;,&lt;s&gt;]
  		      -- The parameter is a vector, with specified
  		         indices. The &lt;s&gt; is s or u for signed or
  			 unsigned.
  
  The value, then, is appropriate for the data type. For example:
  
  	P_123 .param &quot;hello&quot;, string, &quot;Hello, World.&quot;;
  
  
  FUNCTOR STATEMENTS:
  
  A functor statement is a statement that uses the ``.functor''
  opcode. Functors are the basic structural units of a simulation, and
  include a type (in the form of a truth table) and up to four inputs. A
  label is required for functors.
  
  The general syntax of a functor is:
  
  	&lt;label&gt; .functor &lt;type&gt; [ (&lt;delay&gt;) ], symbol_list ;
  
  The symbol list is 4 names of labels of other functors. These connect
  inputs of the functor of the statement to the output of other
  functors. If the input is unconnected, use a C&lt;?&gt; symbol instead. The
  type selects the truth lookup table to use for the functor
  implementation. Most of the core gate types have built in tables.
  
  The initial values of all the inputs and the output is x. Any other
  value is passed around as run-time behavior. If the inputs have C&lt;?&gt;
  symbols, then the inputs are initialized to the specified bit value,
  and if this causes the output to be something other then x, a
  propagation event is created to be executed at the start of run time.
  
  The strengths of inputs are ignored by functors, and the output has
  fixed drive0 and drive1 strengths. So strength information is
  typically lost as it passes through functors.
  
  Almost all of the structural aspects of a simulation can be
  represented by functors, which perform the very basic task of
  combining up to four inputs down to one output.
  
  - MUXZ
  
       Q | A  B  S  n/a
       --+-------------
       A | *  *  0
       B | *  *  1
  
  
  DFF STATEMENTS:
  
  The Verilog language itself does not have a DFF primitive, but post
  synthesis readily creates DFF devices that are best simulated with a
  common device. Thus, there is the DFF statement to create DFF devices:
  
          &lt;label&gt; .dff &lt;d&gt;, &lt;clk&gt;, &lt;ce&gt;, &lt;async-input&gt;;
  
  The generated functor is generally synchronous on the &lt;clk&gt; rising
  edge of &lt;clk&gt;, with the &lt;ce&gt; enable active high. The &lt;clk&gt; and &lt;ce&gt;
  are single bit vectors (or scalars) on ports 1 and 2. Port-0 is any
  type of datum at all. The device will transfer the input to the output
  when it is loaded by a clock. The &lt;async-input&gt; is a special
  asynchronous input that is immediately stored and transferred to the
  output when data arrives here. This is useful for implementing
  asynchronous set/clear functions.
  
  UDP STATEMENTS:
  
  A UDP statement either defines a User Defined Primitive, or
  instantiates a previously defined UDP by creating a UDP functor.  A
  UDP functor has as many inputs as the UDP definition requires.
  
  UDPs come in sequential and combinatorial flavors.  Sequential UDPs
  carry an output state and can respond to edges at the inputs.  The
  output of combinatorial UDPs is a function of its current inputs
  only.
  
  The function of a UDP is defined via a table.  The rows of the table
  are strings which describe input states or edges, and the new output
  state.	Combinatorial UDPs require one character for each input, and
  one character at the end for the output state.	Sequential UDPs need
  an additional char for the current state, which is the first char of
  the row.
  
  Any input transition or the new state must match at most one row (or
  all matches must provide the same output state).  If no row matches,
  the output becomes 1'bx.
  
  The output state can be specified as &quot;0&quot;, &quot;1&quot;, or &quot;x&quot;.	Sequential
  UDPs may also have &quot;-&quot;: no change.
  
  An input or current output state can be
  
  	&quot;1&quot;: 1
  	&quot;0&quot;: 0
  	&quot;x&quot;: x
  	&quot;b&quot;: 1, 0
  	&quot;h&quot;: 1, x
  	&quot;l&quot;: 0, x
  	&quot;?&quot;: 1, 0, x
  
  For Sequential UDPs, at most one input state specification may be
  replaced by an edge specification.  Valid edges are:
  
  	&quot;*&quot;: (??)	&quot;_&quot;: (?0)	&quot;+&quot;: (?1)	&quot;%&quot;: (?x)
  	&quot;P&quot;: (0?)			&quot;r&quot;: (01)	&quot;Q&quot;: (0x)
  	&quot;N&quot;: (1?)	&quot;f&quot;: (10)			&quot;M&quot;: (1x)
  	&quot;B&quot;: (x?)	&quot;F&quot;: (x0)	&quot;R&quot;: (x1)
  
  	&quot;n&quot;: (1?) | (?0)
  	&quot;p&quot;: (0?) | (?1)
  
  A combinatorial UDP is defined like this:
  
  	&lt;type&gt; .udp/comb &quot;&lt;name&gt;&quot;, &lt;number&gt;, &quot;&lt;row0&gt;&quot;, &quot;&lt;row1&gt;&quot;, ... ;
  
  &lt;type&gt; is a label that identifies the UDP.  &lt;number&gt; is the number of
  inputs.	 &quot;&lt;name&gt;&quot; is there for public identification.  Sequential UDPs
  need an additional initialization value:
  
  	&lt;type&gt; .udp/sequ &quot;&lt;name&gt;&quot;, &lt;number&gt;, &lt;init&gt;, &quot;&lt;row0&gt;&quot;, &quot;&lt;row1&gt;&quot;, ... ;
  
  &lt;init&gt; is the initial value for all instances of the UDP.  We do not
  provide initial values for individual instances.  &lt;init&gt; must be a
  number 0, 1, or 2 (for 1'bx).
  
  A UDP functor instance is created so:
  
  	&lt;label&gt; .udp  &lt;type&gt;, &lt;symbol_list&gt; ;
  
  Where &lt;label&gt; identifies the functor, &lt;type&gt; is the label of a UDP
  defined earlier, and &lt;symbol_list&gt; is a list of symbols, one for each
  input of the UDP.
  
  
  VARIABLE STATEMENTS:
  
  A variable is a bit vector that can be written by behavioral code (so
  has no structural input) and propagates its output to a functor. The
  general syntax of a variable is:
  
  	&lt;label&gt; .var   &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;;
  	&lt;label&gt; .var/s &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;;
  	&lt;label&gt; .var/real &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;;
  
  The &quot;name&quot; is the declared base name of the original variable, for the
  sake of VPI code that might access it. The variable is placed in the
  current scope. The variable also has a width, defined by the indices
  for the most significant and lest significant bits. If the indices are
  equal (normally 0) the vector has width of one. If the width is greater
  then one, a contiguous array of functors is created and the value of
  the label is the address of the least significant bit.
  
  A variable does not take inputs, since its value is set behaviorally
  by assignment events. It does have output, though, and its output is
  propagated into the net of functors in the usual way.
  
  A variable gets its value by assignments from procedural code: %set
  and %assign. These instructions write values to the port-0 input. From
  there, the value is held.
  
  Behavioral code can also invoke %cassign/v statements that work like
  %set/v, but instead write to port-1 of the variable node. Writes to
  port-1 of a variable activate continuous assign mode, where the values
  written to port-0 are ignored. The continuous assign mode remains
  active until a long(1) is written to port-3 (a command port).
  
  Behavioral code may also invoke %force/v statements that write to port-2
  to invoke force mode. This overrides continuous assign mode until a
  long(2) is written to port-3 to disable force mode.
  
  NET STATEMENTS:
  
  A net is similar to a variable, except that a thread cannot write to
  it (unless it uses a force) and it is given a different VPI type
  code. The syntax of a .net statement is also similar to but not
  exactly the same as the .var statement:
  
  	&lt;label&gt; .net      &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  	&lt;label&gt; .net/s    &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  	&lt;label&gt; .net8     &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  	&lt;label&gt; .net8/s   &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  	&lt;label&gt; .net/real &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  	&lt;label&gt; .alias    &quot;name&quot;, &lt;msb&gt;, &lt;lsb&gt;, &lt;symbol&gt;;
  
  
  Like a .var statement, the .net statement creates a VPI object with
  the basename and dimensions given as parameters. The symbol is a
  functor that feeds into the vector of the net, and the vpiHandle
  holds references to that functor.
  
  The input of a .net is replicated to its output. In this sense, it
  acts like a diode. The purpose of this node is to hold various VPI
  and event trappings. The .net and .net8 nodes are vector types. They
  both may represent wires, but the .net8 nodes preserve strength values
  that arrive through them, while .net nodes reduce strength values to
  4-value logic. The .net8 nodes should only be used when strength
  information really is possible.
  
  The &lt;label&gt; is required and is used to locate the net object that is
  represents. This label does not map to a functor, so only references
  that know they want to access .nets are able to locate the symbol. In
  particular, this includes behavioral %load and %wait instructions. The
  references to net and reg objects are done through the .net label
  instead of a general functor symbol. The instruction stores the
  functor pointer, though.
  
  The .alias statements do not create new nodes, but instead create net
  names that are aliases of an existing node. This handles special cases
  where a net has different names, possibly in different scopes.
  
  MEMORY STATEMENTS:
  
  Memories are arrays of words, each word a vvp_vector4_t vector of the
  same width. The memory is canonically addressed as a 1-dimensional
  array of words, although indices are stored with the memory for
  calculating a canonical address from a multi-dimensional address.
  
  Three types of memory statement perform (1) creation of a memory, (2)
  connecting a read port to an existing memory, and (3) initializing the
  memory's contents.
  
         &lt;label&gt; .mem &quot;name&quot;, &lt;msb&gt;,&lt;lsb&gt;, &lt;last&gt;,&lt;first&gt; ... ;
  
  The pair of numbers &lt;msb&gt;,&lt;lsb&gt; defines the word width.  The pair
  &lt;last&gt;,&lt;first&gt; defines the address range.  Multiple address ranges are
  allowed for multidimensional indexing. This statement creates the
  memory array and makes it available to procedural code.
  
  Procedural access to the memory references the memory as single array
  of words, with the base address==0, and the last address the size (in
  words) of the memory -1. It is up to the compiler to convert Verilog
  index sets to a canonical address. The multi-dimensional index set is
  available for VPI use.
  
  Structural read access is implemented in terms of address and data
  ports.  The addresses applied to the address port are expected to be
  in canonical form.
  
  A read port is a functor that takes a single input, the read address,
  and outputs the word value at the given (canonical) address.
  
  	&lt;label&gt; .mem/port &lt;memid&gt;, &lt;address&gt; ;
  
  &lt;label&gt; identifies the vector of output functors, to allow connections
  to the data output.  &lt;memid&gt; is the label of the memory.
  
  Any address input change, or any change in the addressed memory
  contents, is immediately propagated to the port output.
  
  A write port is a superset of a read port.  It is a 4-input functor
  that accepts the word address, an event input, a write enable input,
  and the data input.
  
  	&lt;label&gt; .mem/port &lt;memid&gt;, &lt;address&gt;, &lt;event&gt;, &lt;we&gt;, &lt;data&gt; ;
  
  &lt;event&gt; is an event functor that triggers a write, if the &lt;we&gt; input
  is true.  &lt;data&gt; is the input that connect to the data input
  port.  For asynchronous transparent write operation, connect
  &lt;event&gt; to C4&lt;z&gt;, the RAM will transparently follow any changes on
  address and data lines, while &lt;we&gt; is true.
  
  There is no Verilog construct that calls for a structural write port
  to a memory, but synthesis may ask for lpm_ram_d[pq] objects.
  
  To initialize a memory, use:
  
     .mem/init &lt;memid&gt; &lt;start&gt;, val , val ... ;
  
  &lt;memid&gt; is the label of the memory, and the &lt;start&gt; is the start
  address (canonical) of the first word to be initialized. The start
  address allows multiple statements be used to initialize words of a
  memory.
  
  The values are one per word.
  
  Procedural access to the memory employs an index register to address a
  bit location in the memory, via the commands:
  
  	%load/m   &lt;bit&gt;, &lt;memid&gt; ;
  	%set/m    &lt;memid&gt;, &lt;bit&gt; ;
  	%assign/m &lt;memid&gt;, &lt;delay&gt;, &lt;bit&gt; ;
  
  The memory bit is addressed by index register 3.  The value of
  register 3 is the index in the memory's bit space, where each data
  word occupies a multiple of four bits.
  
  
  EVENT STATEMENTS
  
  Threads need to interact with the functors of a netlist synchronously,
  as well as asynchronously. There are cases where the web of functors
  needs to wake up a waiting thread. The web of functors signals threads
  through .event objects, that are declared like so:
  
  	&lt;label&gt; .event &lt;type&gt;, &lt;symbols_list&gt;;
  	&lt;label&gt; .event &quot;name&quot;;
  
  
  This event statement declares an object that a %wait instruction
  can take as an operand. When a thread executes a %wait, it puts
  itself in the notification list of the event and suspends. The
  &lt;symbols_list&gt; is a set of inputs that can trigger the event.
  
  The &lt;type&gt; describes the conditions needed to trigger the event. It
  may be posedge, negedge or edge. If the type is instead a &quot;name&quot;
  string, then this is a named event which receives events by the %set
  instruction instead of from the output of a functor.
  
  If the event has inputs (a requirement unless it is a named event)
  then it has up to 4 symbols that address functors. The event then
  detects the appropriate edge on any of the inputs and signals when the
  event is true. Normally (in Verilog) a posedge or negedge event only
  watches a single bit, so the generated code would only include a
  single symbol for the addressed bit. However, if there are several
  events of the same edge in an event OR expression, the compiler may
  combine up to 4 into a single event.
  
  If many more events need to be combined together (for example due to
  an event or expression in the Verilog) then this form can be used:
  
  	&lt;label&gt; .event/or &lt;symbols_list&gt;;
  
  In this case, the symbols list all the events that are to be combined
  to trigger this event. Only one of the input events needs to trigger
  to make this one go.
  
  
  RESOLVER STATEMENTS:
  
  Resolver statements are strength-aware functors with 4 inputs, but
  their job typically is to calculate a resolved output using strength
  resolution. The type of the functor is used to select a specific
  resolution function.
  
  	&lt;label&gt; .resolv tri,  &lt;symbols_list&gt;;
  	&lt;label&gt; .resolv tri0, &lt;symbols_list&gt;;
  	&lt;label&gt; .resolv tri1, &lt;symbols_list&gt;;
  
  The output from the resolver is vvp_vector8_t value. That is, the
  result is a vector with strength included.
  
  
  PART SELECT STATEMENTS:
  
  Part select statements are functors with three inputs. They take in at
  port-0 a vector, and output a selected (likely smaller) part of that
  vector. The other inputs specify what those parts are, as a canonical
  bit number, and a width. Normally, those bits are constant values.
  
  	&lt;label&gt; .part &lt;symbol&gt;, &lt;base&gt;, &lt;wid&gt;;
  	&lt;label&gt; .part/pv &lt;symbol&gt;, &lt;base&gt;, &lt;wid&gt;, &lt;vector_wid&gt;;
  	&lt;label&gt; .part/v &lt;symbol&gt;, &lt;symbol&gt;, &lt;wid&gt;;
  
  The input is typically a .reg or .net, but can be any vector node in
  the netlist.
  
  The .part/pv variation is the inverse of the .part version, in that
  the output is actually written to a *part* of the output. The node
  uses special part-select-write functions to propagate a part of a
  network. The &lt;vector_wid&gt; is the total width of the destination net
  that part is written to. Destination nodes use this value to check
  further output widths.
  
  The .part/v variation takes a vector (or long) input on port-1 as the
  base of the part select. Thus, the part select can move around.
  
  PART CONCATENATION STATEMENTS:
  
  The opposite of the part select statement is the part concatenation
  statement. The .concat statement is a functor node that takes at input
  vector values and produces a single vector output that is the
  concatenation of all the inputs.
  
          &lt;label&gt; .concat [W X Y Z], &lt;symbols_list&gt; ;
  
  The &quot;[&quot; and &quot;]&quot; tokens surround a set of 4 numbers that are the
  expected widths of all the inputs. These widths are needed to figure
  the positions of the input vectors in the generated output, and are
  listed in order LSB to MSB. The inputs themselves are also listed LSB
  to MSB, with the LSB vector input coming through port-0 of the real
  functor.
  
  The initial output value is (W+X+Y+Z) bits of 'bx. As input values are
  propagated, the bits are placed in the correct place in the output
  vector value, and a new output value is propagated.
  
  
  REPEAT VECTOR STATEMENTS:
  
  The repeat vector statement is similar to the concatenation statement,
  expect that the input is repeated a constant number of times. The
  format of the repeat vector statement is:
  
          &lt;label&gt; .repeat &lt;wid&gt;, &lt;rept count&gt;, &lt;symbol&gt; ;
  
  In this statement, the &lt;wid&gt; is a decimal number that is the width of
  the *output* vector. The &lt;rept count&gt; is the number of time the input
  vector value is repeated to make the output width. The input width is
  implicit from these numbers. The &lt;symbol&gt; is then the input source.
  
  REDUCTION LOGIC
  
  The reduction logic statements take in a single vector, and propagate
  a single bit.
  
          &lt;label&gt; .reduce/and  &lt;symbol&gt; ;
          &lt;label&gt; .reduce/or   &lt;symbol&gt; ;
          &lt;label&gt; .reduce/xor  &lt;symbol&gt; ;
          &lt;label&gt; .reduce/nand &lt;symbol&gt; ;
          &lt;label&gt; .reduce/nor  &lt;symbol&gt; ;
          &lt;label&gt; .reduce/xnor &lt;symbol&gt; ;
  
  the device has a single input, which is a vector of any width. The
  device performs the logic on all the bits of the vector (a la Verilog)
  and produces and propagates a single bit width vector.
  
  EXPANSION LOGIC
  
  Sign extension nodes are the opposite of reduction logic, in that they
  take a narrow vector, or single bit, and pad it out to a wider
  vector.
  
          &lt;label&gt; .expand/s &lt;wid&gt;, &lt;symbol&gt; ;
  
  The .expand/s node takes an input symbol and sign-extends it to the
  given width.
  
  FORCE STATEMENTS (old method - remove me):
  
  A force statement creates functors that represent a Verilog force
  statement.
  
  	&lt;label&gt;	.force &lt;signal&gt;, &lt;symbol_list&gt;;
  
  The symbol &lt;signal&gt; represents the signal which is to be forced.  The
  &lt;symbol_list&gt; specifies the bits of the expression that is to be
  forced on the &lt;signal&gt;.  The &lt;label&gt; identifies the force functors.
  There will be as many force functors as there are symbols in the
  &lt;symbol_list&gt;.
  
  To activate and deactivate a force on a single bit, use:
  
  	%force	&lt;label&gt;, &lt;width&gt;;
  	%release &lt;signal&gt;;
  
  &lt;label&gt;/&lt;width&gt; is the label/width of a vector of force functors.
  &lt;signal&gt; is the label of the functor that drives the signal that is
  being forced.
  
  FORCE STATEMENTS (new method - implement me):
  
  A %force instruction, as described in the .var section, forces a
  constant value onto a .var or .net, and the matching %release releases
  that value. However, there are times when the value of a functor
  (i.e. another .net) needs to be forced onto a .var or .net. For this
  task, the %force/link instruction exists:
  
  	%force/link &lt;dst&gt;, &lt;src&gt; ;
  	%release/link &lt;dst&gt; ;
  
  This causes the output of the node &lt;src&gt; to be linked to the force
  input of the &lt;dst&gt; .var/.net node. When linked, the output functor
  will automatically drive values to the force port of the destination
  node. The matching %release/link instruction removes the link (a
  %release is still needed) to the destination. The %release/link
  releases the last %force/link, no matter where the link is from. A new
  %force/link will remove a previous link.
  
  The instructions:
  
  	%cassign/link &lt;dst&gt;, &lt;src&gt; ;
  	%deassign/link &lt;dst&gt; ;
  
  are the same concept, but for the continuous assign port.
  
  STRUCTURAL ARITHMETIC STATEMENTS:
  
  The various Verilog arithmetic operators (+-*/%) are available to
  structural contexts as two-input functors that take in vectors. All of
  these operators take two inputs and generate a fixed width output. The
  input vectors will be padded if needed to get the desired output width.
  
  	&lt;label&gt; .arith/sub  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .arith/sum  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .arith/mult &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .arith/div  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .arith/mod  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  
  In all cases, there are no width limits, so long as the width is
  fixed.
  
  NOTE: The .arith/mult inputs are not necessarily the width of the
  output. I have not decided how to handle this.
  
  These devices support .s and .r suffixes. The .s means the node is a
  signed vector device, the .r a real valued device.
  
  STRUCTURAL COMPARE STATEMENTS:
  
  The arithmetic statements handle various arithmetic operators that
  have wide outputs, but the comparators have single bit output, so they
  are implemented a bit differently. The syntax, however, is very
  similar:
  
  	&lt;label&gt; .cmp/eeq &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/nee &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/eq  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/ne  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/ge  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/gt  &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/ge.s &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  	&lt;label&gt; .cmp/gt.s &lt;wid&gt;, &lt;A&gt;, &lt;B&gt;;
  
  Whereas the arithmetic statements generate an output the width of
  &lt;wid&gt;, the comparisons produce a single bit vector result. The plain
  versions do unsigned comparison, but the &quot;.s&quot; versions to signed
  comparisons. (Equality doesn't need to care about sign.)
  
  
  STRUCTURAL SHIFTER STATEMENTS:
  
  Variable shifts in structural context are implemented with .shift
  statements:
  
  	&lt;label&gt; .shift/l &lt;wid&gt;, &lt;data symbol&gt;, &lt;shift symbol&gt;;
  	&lt;label&gt; .shift/r &lt;wid&gt;, &lt;data symbol&gt;, &lt;shift symbol&gt;;
  
  The shifter has a width that defines the vector width of the output, a
  &lt;data symbol&gt; that is the input data to be shifted and a &lt;shift-symbol&gt;
  that is the amount to shift. The vectors that come from port 0 are the
  data to be shifted and must have exactly the width of the output. The
  input to port 1 is the amount to shift.
  
  
  STRUCTURAL FUNCTION CALLS:
  
  The .ufunc statement defines a call to a user defined function.
  
  	&lt;label&gt; .ufunc &lt;flabel&gt;, &lt;wid&gt;, &lt;isymbols&gt; ( &lt;psymbols&gt; ) &lt;rsymbol&gt; ;
  
  The &lt;flabel&gt; is the code label for the first instruction of the
  function implementation. This is code that the simulator will branch
  to.
  
  The &lt;wid&gt; is the width of the output vector in bits.
  
  The &lt;isymbols&gt; is a list of net symbols for each of the inputs to the
  function. These are points in the net, and the ufunc device watches
  these nets for input changes.
  
  The &lt;psymbols&gt; list is exactly the same size as the &lt;isymbols&gt;
  list. The &lt;psymbols&gt; are variables that represent the input ports for
  the function. The ufunc performs an assignment to these variables
  before calling the function.
  
  Finally, the &lt;rsymbol&gt; is the variable within the function where the
  result will be found when the function code ends. This value is picked
  up and propagated to the output of the functor.
  
  THREAD STATEMENTS:
  
  Thread statements create the initial threads for a simulation. These
  represent the initial and always blocks, and possibly other causes to
  create threads at startup.
  
  	.thread &lt;symbol&gt; [, &lt;flag&gt;]
  
  This statement creates a thread with a starting address at the
  instruction given by &lt;symbol&gt;. When the simulation starts, a thread is
  created for the .thread statement, and it starts at the &lt;symbol&gt;
  addressed instruction.
  
  The &lt;flag&gt; modifies the creation/execution behavior of the
  thread. Supported flags are:
  
  	$push -- Cause the thread to be pushed in the scheduler. This
  		 only effects startup (time 0) by arranging for pushed
  		 threads to be started before non-pushed threads. This
  		 is useful for resolving time-0 races.
  
  * Threads in general
  
  Thread statements create the initial threads of a design. These
  include the ``initial'' and ``always'' statements of the original
  Verilog, and possibly some other synthetic threads for various
  purposes. It is also possible to create transient threads from
  behavioral code. These are needed to support such constructs as
  fork/join, named blocks and task activation.
  
  A transient thread is created with a %fork instruction. When a
  transient thread is created this way, the operand to the %fork gives
  the starting address, and the new thread is said to be a child of the
  forking thread. The children of a thread are pushed onto a stack of
  children. A thread can have only one direct child.
  
  A transient thread is reaped with a %join instruction. %join waits for
  the top thread in the stack of children to complete, then
  continues. It is an error to %join when there are no children.
  
  As you can see, the transient thread in VVP is a cross between a
  conventional thread and a function call. In fact, there is no %call
  instruction in vvp, the job is accomplished with %fork/%join in the
  caller and %end in the callee. The %fork, then is simply a
  generalization of a function call, where the caller does not
  necessarily wait for the callee.
  
  For all the behavior of threads and thread parentage to work
  correctly, all %fork statements must have a corresponding %join in the
  parent, and %end in the child. Without this proper matching, the
  hierarchical relationships can get confused. The behavior of erroneous
  code is undefined.
  
  * Thread Context
  
  The context of a thread is all the local data that only that thread
  can address. The local data is broken into two addresses spaces: bit
  memory and word memory.
  
  The bit memory is a region of 4-value bits (0,1,x,z) that can be
  addressed in strips of arbitrary length. For example, an 8-bit value
  can be in locations 8 through and including 15. The bits at address 0,
  1, 2 and 3 are special constant values. Reads from those locations
  make vectors of 0, 1, x or z values, so these can be used to
  manufacture complex values elsewhere.
  
  The word memory is a region of tagged words. The value in each word
  may be native long or real. These words have a distinct address space
  from the bits.
  
  * Threads and scopes
  
  The Verilog ``disable'' statement deserves some special mention
  because of how it interacts with threads. In particular, threads
  throughout the design can affect (end) other threads in the design
  using the disable statement.
  
  In Verilog, the operand to the disable statement is the name of a
  scope. The behavior of the disable is to cause all threads executing
  in the scope to end. Termination of a thread includes all the children
  of the thread. In vvp, all threads are in a scope, so this is how the
  disable gains access to the desired thread.
  
  It is obvious how initial/always thread join a scope. They become part
  of the scope simply by being declared after a .scope declaration. (See
  vvp.txt for .scope declarations.) The .thread statement placed in the
  assembly source after a .scope statement causes the thread to join the
  named scope.
  
  Transient threads join a scope that is the operand to the %fork
  instruction. The scope is referenced by name, and the thread created
  by the fork atomically joins that scope. Once the transient thread
  joins the scope, it stays there until it ends. Threads never change
  scopes, not even transient threads.
  
  TRUTH TABLES
  
  The logic that a functor represents is expressed as a truth table. The
  functor has four inputs and one output. Each input and output has one
  of four possible values (0, 1, x and z) so two bits are needed to
  represent them. So the input of the functor is 8 bits, and the output
  2 bits. A complete lookup table for generating the 2-bit output from
  an 8-bit input is 512 bits. That can be packed into 64 bytes. This is
  small enough that the table should take less space then the code to
  implement the logic.
  
  To implement the truth table, we need to assign 2-bit encodings for
  the 4-value signals. I choose, pseudo-randomly, the following
  encoding:
  
  	1'b0  : 00
  	1'b1  : 01
  	1'bx  : 10
  	1'bz  : 11
  
  The table is an array of 64 bytes, each byte holding 4 2-bit
  outputs. Construct a 6-bit byte address with inputs 1, 2 and 3 like
  so:
  	 332211
  
  The input 0 2-bits can then be used to select which of the 4 2-bit
  pairs in the 8-bit byte are the output:
  
  	MSB -&gt; zzxx1100 &lt;- LSB
  
  A complete truth table, then is described as 64 8-bit bytes.
  
  The vvp engine includes truth tables for the primitive gate types, so
  none needs to be given by the programmer. It is sufficient to name the
  type to get that truth table.
  
  
  EXECUTABLE INSTRUCTIONS
  
  Threads run executable code, much like a processor executes machine
  code. VVP has a variety of opcodes for executable instructions. All of
  those instructions start with '%' and go into a single address
  space. Labels attached to executable instructions get assigned the
  address of the instruction, and can be the target of %jmp instructions
  and starting points for threads.
  
  The opcodes.txt file has a more detailed description of all the
  various instructions.
  
  
  THE RELATIONSHIP BETWEEN FUNCTORS, THREADS AND EVENTS
  
  Given the above summary of the major components of vvp, some
  description of their relationship is warranted. Functors provide a
  structural description of the design (so far as it can be described
  structurally) and these functors run independently of the threads. In
  particular, when an input to a functor is set, it calculates a new
  output value; and if that output is different from the existing
  output, a propagation event is created. Functor output is calculated
  by truth table lookup, without the aid of threads.
  
  Propagation events are one of three kinds of events in vvp. They are
  scheduled to execute at some time, and they simply point to the functor
  that is to have its output propagated. When the event expires, the
  output of the referenced functor is propagated to all the inputs that
  it is connected to, and those functors in turn create new events if
  needed.
  
  Assignment events (the second of three types of events) are created
  by non-blocking assignments in behavioral code. When the ``&lt;='' is
  executed (a %assign in vvp) an assign event is created, which includes
  the vvp_ipoint_t pointer to the functor input to receive the value,
  as well as the value. These are distinct from propagation events because:
  
  	a) There is no functor that has as its output the value to be
  	   assigned (this is how values get into the functor net in
  	   the first place), and
  
  	b) This allows for behavioral code to create waveforms of
  	   arbitrary length that feed into a variable. Verilog allows
  	   this of non-blocking assignments, but not of gate outputs.
  
  The last type of event is the thread schedule event. This event simply
  points to a thread to be executed. Threads are made up of a virtual
  processor with a program counter and some private storage. Threads
  can execute %assign instructions to create assignment events, and can
  execute %set instructions to do blocking assignments. Threads can also
  use %load to read the output of functors.
  
  The core event scheduler takes these three kinds of events and calls
  the right kind of code to cause things to happen in the design. If the
  event is a propagate or assignment event, the network of functors is
  tickled; if the event is a thread schedule, then a thread is run. The
  implementation of the event queue is not important, but currently is
  implemented as a ``skip list''. That is, it is a sorted singly linked
  list with skip pointers that skip over delta-time events.
  
  The functor net and the threads are distinct. They communicate through
  thread instructions %set, %assign, %waitfor and %load. So far as a thread
  is concerned, the functor net is a blob of structure that it pokes and
  prods via certain functor access instructions.
  
  
  VVP COMPILATION AND EXECUTION
  
  The vvp program operates in a few steps:
  
  	1) Initialization
  		Data structures are cleared to empty, and tables are
  		readied for compilation.
  
  	2) Compilation
  		The input file is read and compiled. Symbol tables are
  		build up as needed, objects are allocated and linked
  		together.
  
  	3) Cleanup
  		Symbol tables and other resources used only for
  		compilation are released to reduce the memory
  		footprint.
  
  	4) Simulation
  		Event simulation is run.
  
  
  The initialization step is performed by the compile_init() function in
  compile.cc. This function in turn calls all the *_init() functions in
  other parts of the source that need initialization for compile. All
  the various sub-init functions are called &lt;foo&gt;_init().
  
  Compilation is controlled by the parser, it parse.y. As the parser
  reads and parses input, the compilation proceeds in the rules by
  calling various compile_* functions. All these functions live in the
  compile.cc file. Compilation calls other sections of the code as
  needed.
  
  When the parser completes compilation, compile_cleanup() is called to
  finish the compilation process. Unresolved references are completed,
  then all the symbol tables and other compile-time-only resources are
  released. Once compile_cleanup() returns, there is no more use for the
  parser for the function in compile.cc.
  
  After cleanup, the simulation is started. This is done by executing
  the schedule_simulate() function. This does any final setup and starts
  the simulation running and the event queue running.
  
  
  HOW TO GET FROM THERE TO HERE
  
  The vvp simulation engine is designed to be able to take as input a
  compiled form of Verilog. That implies that there is a compiler that
  compiles Verilog into a form that the vvp engine can read.
  
  
  * Boolean logic gates
  
  Gates like AND, OR and NAND are implemented simply and obviously by
  functor statements. Any logic up to 4 inputs can be implemented with a
  single functor. For example:
  
  	and gate (out, i1, i2, i3);
  
  becomes:
  
  	gate	.functor and, i1, i2, i3;
  
  Notice the first parameter of the .functor is the type. The type
  includes a truth table that describes the output with a given
  input. If the gate is wider then four inputs, then cascade
  functors. For example:
  
  	and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);
  
  becomes:
  
  	gate.0	.functor and, i1, i2, i3, i4;
  	gate.1	.functor and, i5, i6, i7, i8;
  	gate	.functor and, gate.0, gate.1;
  
  
  * reg and other variables
  
  Reg and integer are cases of what Verilog calls ``variables.''
  Variables are, simply put, things that behavioral code can assign
  to. These are not the same as ``nets,'' which include wires and the
  like.
  
  Each bit of a variable is created by a ``.var'' statement. For example:
  
  	reg a;
  
  becomes:
  
  	a	.var &quot;a&quot;, 0, 0;
  
  
  * named events
  
  Events in general are implemented as functors, but named events in
  particular have no inputs and only the event output. The way to
  generate code for these is like so:
  
  	a  .event &quot;name&quot;;
  
  This creates a functor and makes it into a mode-2 functor. Then the
  trigger statement, &quot;-&gt; a&quot;, cause a ``%set a, 0;'' statement be
  generated. This is sufficient to trigger the event.
  
  /*
   * Copyright (c) 2001 Stephen Williams (steve@xxxxxxxxxx)
   *
   *    This source code is free software; you can redistribute it
   *    and/or modify it in source code form under the terms of the GNU
   *    General Public License as published by the Free Software
   *    Foundation; either version 2 of the License, or (at your option)
   *    any later version.
   *
   *    This program is distributed in the hope that it will be useful,
   *    but WITHOUT ANY WARRANTY; without even the implied warranty of
   *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *    GNU General Public License for more details.
   *
   *    You should have received a copy of the GNU General Public License
   *    along with this program; if not, write to the Free Software
   *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
   */</pre>
  
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  <h1><a name="xilinx_hints" id="xilinx_hints">Xilinx Hints</a></h1>
  <div class="level1">
  <pre class="code">For those of you who wish to use Icarus Verilog, in combination with
  the Xilinx back end (Foundation or Alliance), it can be done.  I have
  run some admittedly simple (2300 equivalent gates) designs through this
  setup, targeting a Spartan XCS10.
  
  Verilog:
  
     Older versions of Icarus Verilog (like 19990814) couldn't synthesize
     logic buried in procedural (flip-flop) assignment.  Newer versions
     (like 20000120) don't have this limitation.
  
     Procedural assignments have to be given one at a time, to be
     &quot;found&quot; by xnfsyn.  Say
         always @ (posedge Clk) Y = newY;
         always @ (posedge Clk) Z = newZ;
     rather than
         always @ (posedge Clk) begin
             Y = newY;
             Z = newZ;
         end
  
     Steve's xnf.txt covers most buffer and pin constructs, but I had reason
     to use a global clock net not connected to an input pin.  The standard
     Verilog for a buffer, combined with a declaration to turn that into a
     BUFG, is:
         buf BUFG( your_output_here, your_input_here );
         $attribute(BUFG,&quot;XNF-LCA&quot;,&quot;BUFG:O,I&quot;)
  
     I use post-processing on my .xnf files to add &quot;FAST&quot; attributes to
     output pins.
  
  Running ivl:
  
     The -F switches are important.  The following order seems to robustly
     generate valid XNF files, and is used by &quot;verilog -X&quot;:
        -Fsynth -Fnodangle -Fxnfio
  
  Generating .pcf files:
  
     The ngdbuild step seems to lose pin placement information that ivl
     puts in the XNF file.  Use xnf2pcf to extract this information to
     a .pcf file, which the Xilinx place-and-route software _will_ pay
     attention to.  Steve says he now makes that information available
     in an NCF file, with -fncf=&lt;path&gt;, but I haven't tested that.
  
  Running the Xilinx back end:
  
     You can presumably use the GUI, but that doesn't fit in Makefiles :-).
     Here is the command sequence in pseudo-shell-script:
        ngdbuild -p $part $1.xnf $1.ngd
        map -p $part -o map.ncd $1.ngd
        xnf2pcf &lt;$1.xnf &gt;$1.pcf    # see above
        par -w -ol 2 -d 0 map.ncd $1.ncd $1.pcf
        bitgen_flags = -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP \
                       -g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no \
                       -g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 \
                       -g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable
        bitgen $1.ncd -l -w $bitgen_flags
  
     The Xilinx software has diarrhea of the temp files (14, not including
     .xnf, .pcf, .ngd, .ncd, and .bit), so this sequence is best done in a
     dedicated directory.  Note in particular that map.ncd is a generic name.
  
     I had reason to run this remotely (and transparently within a Makefile)
     via ssh.  I use the gmake rule
  %.bit : %.xnf
          ssh -x -a -o 'BatchMode yes' ${ALLIANCE_HOST} \
                 remote_alliance ${REMOTE_DIR} $(basename $@) 2&gt;&amp;1 &lt; $&lt;
  	scp ${ALLIANCE_HOST}:${REMOTE_DIR}/$@ .
      and the remote_alliance script (on ${ALLIANCE_HOST})
  /bin/csh
  cd $1
  cat &gt;! $2.xnf
  xnf2pcf &lt;$2.xnf &gt;! $2.pcf
  ./backend $2
  
     There is now a &quot;Xilinx on Linux HOWTO&quot; at
           http://www.polybus.com/xilinx_on_linux.html
     I haven't tried this yet, it looks interesting.
  
  Downloading:
  
     I use the XESS (http://www.xess.com/) XSP-10 development board, which
     uses the PC parallel (printer) port for downloading and interaction
     with the host.  They made an old version of their download program
     public domain, posted it at
        http://www.xess.com/FPGA/xstools.zip ,
     and now there is a Linux port at
        ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz .
  
  The above hints are based on my experience with Foundation 1.5 on NT
  (gack) and Alliance 2.1i on Solaris.  Your mileage may vary.  Good luck!
  
       - Larry Doolittle   &lt;LRDoolittle@xxxxxxx&gt;   August 19, 1999
                                          updated February 1, 2000
  </pre>
  
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  <h1><a name="xilinx_netlist_format" id="xilinx_netlist_format">Xilinx Netlist Format</a></h1>
  <div class="level1">
  <pre class="code">WHAT IS XNF
  
  XNF is the Xilinx Netlist Format. This is somewhat specific to the
  Xilinx tool chain, but it is sufficiently ubiquitous that it's still
  worth it. This format can be fed to place and route tools and
  simulators. Since some third party simulators accept XNF, the format
  may be useful even independent of Xilinx parts.
  
  Icarus Verilog supports XNF as specified by the Xilinx Netlist Format
  Specification, Version 6.1.
  
  GENERATE XNF OUTPUT -- THE SHORT STORY
  
  The easiest way to compile for XNF output is with the &quot;verilog&quot;
  command (man verilog) and the -X switch:
  
  	% iverilog -fpart=4010e -fncf=prog.ncf -txnf prog.v
  
  This generates from the prog.v Verilog source file the prog.xnf output
  and the prog.ncf netlist constraints file. The verilog program
  arranges to call the preprocessor and the ivl compiler with all the
  correct switches for generating XNF.
  
  GENERATING XNF MACROS
  
  Icarus Verilog can be used to generate XNF implementations of devices
  that are written in Verilog and used by schematic editors such as
  OrCAD. The trick here is that the code generator automatically notices
  ports to the root module and generates the PIN= attributes needed so
  that external tools can link to the generated XNF.
  
  Icarus Verilog chooses a name for the pin. The name it chooses is the
  port name of the module. If the port is a vector, a pin is generated
  for all the bits of the vector with the bit number appended. For
  example:
  
  	module foo(in);
  	input [3:0] in;
  
  causes the single bit ports ``in0'' through ``in3'' be
  generated. Internally, the XNF file uses the bussed names instead of
  the pin name.
  
  The implication of this is that there is a chance of name collision
  with the generated XNF macro if the port names are chosen badly. It is
  best to not end a port name with decimal digits, as that can cause
  trouble at link time. Also, XNF is not case sensitive and that should
  be accounted for as well.
  
  XNF PADS IN VERILOG SOURCE
  
  You can assign wires to pads using the Icarus Verilog $attribute
  extension. Attach to a scalar signal (wire or register) the PAD
  attribute with the value that specifies the direction and pin
  number. For example:
  
  	wire foo, bar, bid;
  	$attribute(foo, &quot;PAD&quot;, &quot;i1&quot;); // Input pad on pin 1
  	$attribute(bar, &quot;PAD&quot;, &quot;o2&quot;); // Output pad on pin 2
  	$attribute(bid, &quot;PAD&quot;, &quot;b3&quot;); // Bi-directional pad on pin 3
  
  The XNFIO function uses these attributes to locate signals that are
  connected to pads, and generates XNF I/O block devices to connect to
  the pad to do the FPGA pin buffering that is needed. So the Verilog
  programmer need not in general specify the IBUF/OBUF buffers.
  
  If the programmer does connect buffers to pads, the compiler will
  notice them and convert them to I/OBUFs automatically. For example:
  
  	buf b1 (sig, foo);
  
  connects to pad foo, so will be converted into an XNF IBUF
  device. Also:
  
  	bufif1 bt (bar, value, en);
  
  connects to pad bar so will automatically be converted into an OBUFT
  device. Icarus Verilog understands OBUF, IBUF and OBUFT (with optionally
  inverted enable) devices and will convert Verilog devices from the
  source, or generate missing devices.
  
  In addition, the Verilog programmer may explicitly declare a device as
  an I/OBUF by attaching an attribute to the device, like so:
  
  	buf b1 (sig, foo);
  	$attribute(b1, &quot;XNF-LCA&quot;, &quot;OBUF:O,I&quot;);
  
  This latter feature is not entirely recommended as it expects that the
  programmer really knows how the pins of the XNF device are to be
  connected. It also bypasses the efforts of the compiler, so is not
  checked for correctness.
  
  XNF STORAGE ELEMENTS
  
  Storage elements in XNF include flip-flops, latches and CLB
  rams. These devices are generated from the LPM equivalents that the
  -Fsynth functor synthesizes from behavioral descriptions.
  
  Flip-flops, or more specifically DFF devices, are generated to
  implement behavioral code like this:
  
  	reg Q;
  	always @(posedge clk) Q &lt;= &lt;expr&gt;;
  
  The edge can be positive or negative, and the expression can be any
  synthesizable expression. Furthermore, the register &quot;Q&quot; can have
  width, which will cause the appropriate number of flip-flops to be
  created. A clock enable expression can also be added like so:
  
  	reg Q;
  	always @(posedge clk) if (&lt;ce&gt;) Q &lt;= &lt;expr&gt;;
  
  The &lt;ce&gt; expression can be any synthesizable expression.
  
  With or without the CE, the generated DFF devices are written into the
  XNF output one bit at a time, with the clock input inverted if necessary.
  
  Xilinx parts also support CLB circuitry as synchronous RAMS. These
  devices are created from Verilog memories if the properties are
  right. The behavioral description that the -Fsynth functor matches to
  get a synchronous RAM looks very similar to that for a DFF:
  
  	reg [15:0] M;
  	always @(posedge clk) if (&lt;we&gt;) M[&lt;addr&gt;] &lt;= &lt;expr&gt;;
  
  Note that in this case the l-value of the assignment is an addressed
  memory. This statement models writes into the memory. Reads from the
  device can be modeled with ordinary structural code, i.e.:
  
  	assign foo &lt;= M[&lt;addr&gt;];
  
  For the memory to be synthesizable in the XNF target, the address
  lines for writes and reads must be connected. This corresponds to the
  limitations of the real hardware.
  
  OTHER XNF SPECIAL DEVICES
  
  There are certain special devices in XNF that Verilog does not
  naturally represent, although there are similar more generic Verilog
  devices. The most obvious and useful example is the clock driver,
  otherwise known as the global buffer BUFG. As with pads, Icarus
  Verilog uses the $attribute extension to allow you to specify special
  devices.
  
  The $attribute statement can be applied to devices much the same way
  one applies them to wires. For example, to turn a buffer into a clock
  buffer:
  
  	wire iclk, clk;
  	buf BUFG (clk, iclk);
  	$attribute(iclk, &quot;PAD&quot;, &quot;i1&quot;);
  	$attribute(BUFG, &quot;XNF-LCA&quot;, &quot;BUFG:O,I&quot;);
  
  The above statements cause the buffer BUFG to be emitted in the XNF
  output as a BUFG device with the first signal called &quot;O&quot; and the
  second called &quot;I&quot;. The rest of this example connects the input of the
  BUFG to a signal from the input pin #1 and connects the output to the
  internal wire &quot;clk&quot;. Incidentally, this example will cause an IBUF to
  be generated to connect the iclk signal to input pin #1.
  
  SUMMARY OF IVL SUPPORT FOR XNF
  
  Icarus Verilog has a code generator and synthesis functions that
  support generation of XNF netlists. The XNF modules also allow the
  programmer to use $attributes to control certain aspects of code
  generation.
  
  XNF code generation is enabled with the ``-t xnf'' flag on the command
  line. The code generator needs to know the type of part to generate
  code for, so the ``-fpart=&lt;type&gt;'' flag is also needed. For example,
  to generate code for the 4010E the command line might start out as:
  
  	 ivl -txnf -fpart=4010e -Fsynth -Fnodangle -Fxnfio [...]
  
  Icarus Verilog includes the functions ``synth'' and ``xnfio'' to
  perform transformations and optimizations on the design before code is
  generated. The ``synth'' function matches certain behavioral constructs
  to structural components, and the xnfio function generates pads and
  fills the IOBs.
  
  SUPPORTED FLAGS
  
      -fpart=&lt;part&gt;
          Specify the type of part to target. This string is written
          literally into the PART, record of the XNF, and may also be
          used to control synthesis and placement.
  
      -fncf=&lt;path&gt;
          Cause the code generator to write into &lt;path&gt; the netlist
          constraints needed for controlling placement and timing. This
          switch is required if pin assignments are assigned in the
          Verilog source.
  
  THE SYNTH FUNCTION
  
  This function does synthesis transformations on the entered design,
  making it possible to generate XNF netlist components from certain
  behavioral constructs. This is needed in Verilog for example to model
  some of the synchronous components of the XNF library.
  
  It is a bit much to expect a Verilog compiler in general to generate
  components from arbitrary behavioral descriptions, so the synth
  function works by matching statements that have some documented
  structure, and substituting them for the equivalent XNF component. A
  fully synthesize-able design, then, is one where the behavioral
  statements can all be matched and substituted by the synth function.
  
  THE XNFIO FUNCTION
  
  The &quot;xnfio&quot; function transforms the netlist where the IOBs are
  concerned. The signals with PAD attributes are checked, and
  surrounding circuitry generated to conform to the logic available in
  the IOB.
  
  If the pad is an OPAD, the function will look for an existing buf or
  not gate connected to the PAD signal. If the gate is appropriately
  connected, the buf or not gate will be turned into an OBUF. This pulls
  the buf or inverter into the IOB, freeing a CLB and providing the
  required pin circuitry.
  
  If the pad is an IPAD, the function will look for a buf, and convert
  that to an IBUF. Since Xilinx IOBs cannot invert the output from an
  IBUF, NOT gates cannot be absorbed as in the OPAD case.
  
  
  /*
   * Copyright (c) 1998-1999 Stephen Williams (steve@xxxxxxxxxx)
   *
   *    This source code is free software; you can redistribute it
   *    and/or modify it in source code form under the terms of the GNU
   *    General Public License as published by the Free Software
   *    Foundation; either version 2 of the License, or (at your option)
   *    any later version.
   *
   *    This program is distributed in the hope that it will be useful,
   *    but WITHOUT ANY WARRANTY; without even the implied warranty of
   *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   *    GNU General Public License for more details.
   *
   *    You should have received a copy of the GNU General Public License
   *    along with this program; if not, write to the Free Software
   *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
   */
  
  
   $Log: geda_icarus_xnf.html,v $
   Revision 1.1  2006/08/22 02:56:12  ahvezda
   First checkin of the wiki snapshot, prep work for new version of gEDA/gaf
  
   Revision 1.16  2003/07/15 03:49:22  steve
    Spelling fixes.
  
   Revision 1.15  2003/01/30 16:23:08  steve
    Spelling fixes.
  
   Revision 1.14  2000/08/01 21:32:40  steve
    Use the iverilog command in documentation.
  
   Revision 1.13  2000/08/01 02:48:42  steve
    Support &lt;= in synthesis of DFF and ram devices.
  
   Revision 1.12  2000/07/25 22:49:32  steve
    memory is not a data type in verilog.
  
   Revision 1.11  2000/04/23 23:03:13  steve
    automatically generate macro interface code.
  
   Revision 1.10  1999/12/05 19:30:43  steve
    Generate XNF RAMS from synthesized memories.
  
   Revision 1.9  1999/11/18 03:52:20  steve
    Turn NetTmp objects into normal local NetNet objects,
    and add the nodangle functor to clean up the local
    symbols generated by elaboration and other steps.
  
   Revision 1.8  1999/11/06 04:51:42  steve
    Support writing some XNF things into an NCF file.
  
   Revision 1.7  1999/11/03 05:18:18  steve
    XNF synthesis now uses the synth functor.
  
   Revision 1.6  1999/11/02 01:43:55  steve
    Fix iobuf and iobufif handling.
  
   Revision 1.5  1999/10/09 17:52:27  steve
    support XNF OBUFT devices.
  
   Revision 1.4  1999/08/14 22:48:21  steve
    Mention the sigfold function.
  
   Revision 1.3  1999/07/22 02:05:20  steve
    is_constant method for PEConcat.
  
   Revision 1.2  1999/07/18 21:17:51  steve
    Add support for CE input to XNF DFF, and do
    complete cleanup of replaced design nodes.
  
   Revision 1.1  1999/05/01 02:57:11  steve
    XNF target documentation.</pre>
  
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  <h1><a name="fpga_loadable_code_generator_for_icarus_verilog" id="fpga_loadable_code_generator_for_icarus_verilog">FPGA Loadable Code Generator for Icarus Verilog</a></h1>
  <div class="level1">
  <pre class="code">FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
  
    Copyright 2001 Stephen Williams
    $Id: geda_igarus_fpga_lcg.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
  
  The FPGA code generator supports a variety of FPGA devices, writing
  XNF or EDIF depending on the target. You can select the architecture
  of the device, and the detailed part name. The architecture is used to
  select library primitives, and the detailed part name is written into
  the generated file for the use of downstream tools.
  
  INVOKING THE FPGA TARGET
  
  The code generator is invoked with the -tfpga flag to iverilog. It
  understands the part= and the arch= parameters, which can be set with
  the -p flag of iverilog:
  
  	iverilog -parch=virtex -ppart=v50-pq240-6 -tfpga foo.vl
  
  This example selects the Virtex architecture, and give the detailed
  part number as v50-pq240-6. The output is written into a.out unless a
  different output file is specified with the -o flag.
  
  The following is a list of architecture types that this code generator
  supports.
  
  * arch=lpm
  
  This is a device independent format, where the gates are device types
  as defined by the LPM 2 1 0 specification. Some backend tools may take
  this format, or users may write interface libraries to connect these
  netlists to the device in question.
  
  * arch=generic-edif (obsolete)
  
  This is generic EDIF code. It doesn't necessarily work because the
  external library is not available to the code generator. But, what it
  does is generate generic style gates that a portability library can
  map to target gates if desired.
  
  * arch=generic-xnf (obsolete)
  
  If this is selected, then the output is formatted as an XNF file,
  suitable for most any type of device. The devices that it emits
  are generic devices from the unified library. Some devices are macros,
  you may need to further resolve the generated XNF to get working
  code for your part.
  
  * arch=virtex
  
  If this is selected, then the output is formatted as an EDIF 200 file,
  suitable for Virtex class devices. This is supposed to know that you
  are targeting a Virtex part, so can generate primitives instead of
  using external macros. It includes the VIRTEX internal library, and
  should work properly for any Virtex part.
  
  * arch=virtex2
  
  If this is selected, then the output is EDIF 2 0 0 suitable for
  Virtex-II and Virtex-II Pro devices. It uses the VIRTEX2 library, but
  is very similar to the Virtex target.
  
  XNF ROOT PORTS
  
    NOTE: As parts are moved over to EDIF format, XNF support will be
    phased out. Current Xilinx implementation tools will accept EDIF
    format files even for the older parts, and non-Xilinx implementation
    tools accept nothing else.
  
  When the output format is XNF, the code generator will generate &quot;SIG&quot;
  records for the signals that are ports of the root module. The name is
  declared as an external pin that this macro makes available.
  
  The name given to the macro pin is generated from the base name of the
  signal. If the signal is one bit wide, then the pin name is exactly
  the module port name. If the port is a vector, then the pin number is
  given as a vector. For example, the module:
  
  	module main(out, in);
  	    output out;
  	    input [2:0] in;
  	    [...]
  	endmodule
  
  leads to these SIG, records:
  
  	SIG, main/out, PIN=out
  	SIG, main/in&lt;2&gt;, PIN=in2
  	SIG, main/in&lt;1&gt;, PIN=in1
  	SIG, main/in&lt;0&gt;, PIN=in0
  
  
  EDIF ROOT PORTS
  
  The EDIF format is more explicit about the interface into an EDIF
  file. The code generator uses that control to generate an explicit
  interface definition into the design. (This is *not* the same as the
  PADS of a part.) The generated EDIF interface section contains port
  definitions, including the proper direction marks.
  
  With the (rename ...) s-exp in EDIF, it is possible to assign
  arbitrary text to port names. The EDIF code generator therefore does
  not resort to the mangling that is needed for the XNF target. The base
  name of the signal that is an input or output is used as the name of
  the port, complete with the proper case.
  
  However, since the ports are single bit ports, the name of vectors
  includes the string &quot;[0]&quot; where the number is the bit number. For
  example, the module:
  
  
  	module main(out, in);
  	    output out;
  	    input [2:0] in;
  	    [...]
  	endmodule
  
  creates these ports:
  
  	out   OUTPUT
  	in[0] INPUT
  	in[1] INPUT
  	in[2] INPUT
  
  Target tools, including Xilinx Foundation tools, understand the []
  characters in the name and recollect the signals into a proper bus
  when presenting the vector to the user.
  
  
  PADS AND PIN ASSIGNMENT
  
  The ports of a root module may be assigned to specific pins, or to a
  generic pad. If a signal (that is a port) has a PAD attribute, then
  the value of that attribute is a list of locations, one for each bit
  of the signal, that specifies the pin for each bit of the signal. For
  example:
  
  	module main( (* PAD = &quot;P10&quot; *)         output out,
  		     (* PAD = &quot;P20,P21,P22&quot; *) input [2:0] in);
  
  	    [...]
  
  	endmodule
  
  In this example, port ``out'' is assigned to pin 10, and port ``in''
  is assigned to pins 20-22. If the architecture supports it, a pin
  number of 0 means let the back end tools choose a pin. The format of
  the pin number depends on the architecture family being targeted, so
  for example Xilinx family devices take the name that is associated
  with the &quot;LOC&quot; attribute.
  
  NOTE: If a module port is assigned to a pin (and therefore attached to
  a PAD) then it is *not* connected to a port of the EDIF file. This is
  because the PAD (and possibly IBUF or OBUF) would become an extra
  driver to the port. An error.
  
  
  SPECIAL DEVICES
  
  The code generator supports the &quot;cellref&quot; attribute attached to logic
  devices to cause specific device types be generated, instead of the
  usual device that the code generator might generate. For example, to
  get a clock buffer out of a Verilog buf:
  
  	buf my_gbuf(out, in);
  	$attribute(my_buf, &quot;cellref&quot;, &quot;GBUF:O,I&quot;);
  
  The &quot;cellref&quot; attribute tells the code generator to use the given
  cell. The syntax of the value is:
  
  	&lt;cell type&gt;:&lt;pin name&gt;,...
  
  The cell type is the name of the library part to use. The pin names
  are the names of the type in the library, in the order that the logic
  device pins are connected.
  
  
  COMPILING WITH XILINX FOUNDATION
  
  Compile a single-file design with command line tools like so:
  
  	% iverilog -parch=virtex -o foo.edf foo.vl
  	% edif2ngd foo.edf foo.ngo
  	% ngdbuild -p v50-pq240 foo.ngo foo.ngd
  	% map -o map.ncd foo.ngd
  	% par -w map.ncd foo.ncd
  
  ---
  $Log: geda_igarus_fpga_lcg.html,v $
  Revision 1.1  2006/08/22 02:56:12  ahvezda
  First checkin of the wiki snapshot, prep work for new version of gEDA/gaf
  
  Revision 1.12  2005/09/19 21:45:36  steve
   Spelling patches from Larry.
  
  Revision 1.11  2003/08/07 05:17:34  steve
   Add arch=lpm to the documentation.
  
  Revision 1.10  2003/07/04 03:57:19  steve
   Allow attributes on Verilog 2001 port declarations.
  
  Revision 1.9  2003/07/04 01:08:03  steve
   PAD attribute can be used to assign pins.
  
  Revision 1.8  2003/07/02 00:26:49  steve
   Fix spelling of part= flag.
  
  Revision 1.7  2003/03/24 02:28:38  steve
   Document the virtex2 architecture.
  
  Revision 1.6  2003/03/24 00:47:54  steve
   Add new virtex2 architecture family, and
   also the new edif.h EDIF management functions.
  
  Revision 1.5  2002/04/30 04:26:42  steve
   Spelling errors.
  
  Revision 1.4  2001/09/16 22:26:47  steve
   Support the cellref attribute.
  
  Revision 1.3  2001/09/16 01:48:16  steve
   Suppor the PAD attribute on signals.
  
  Revision 1.2  2001/09/06 04:28:40  steve
   Separate the virtex and generic-edif code generators.
  
  Revision 1.1  2001/09/02 23:58:49  steve
   Add documentation for the code generator.
  
  </pre>
  
  </div>
  </div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_installation.html
  
  Index: geda_installation.html
  ===================================================================
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#installation_help" class="toc">Installation help</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_install_the_geda_suite" class="toc">How do I install the gEDA Suite?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_uninstall_the_geda_suite" class="toc">How do I uninstall the gEDA Suite?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_would_i_want_to_uninstall_the_geda_suite" class="toc">Why would I want to uninstall the gEDA Suite?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#aaaargh_i_put_the_cd_into_my_reader_and_mounted_the_cd_but_nothing_happened" class="toc">Aaaargh! I put the CD into my reader, and mounted the CD, but nothing happened!</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#help_me_i_m_trying_to_install_using_the_cd_rom_but_the_install_wizard_says_i_have_an_error" class="toc">Help me! I'm trying to install using the CD ROM, but the install wizard says I have an error!</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#waaaa_the_installation_ran_to_completion_but_i_get_a_segfault_or_other_problem_when_i_run_gschem_or_gattrib_or_gnetlist_or" class="toc">Waaaa! The installation ran to completion, but I get a segfault (or other problem) when I run gschem (or gattrib, or gnetlist, or. . . )!</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#fedora_core_4_install_notes" class="toc">Fedora Core 4 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#fedora_core_3_install_notes" class="toc">Fedora Core 3 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#fedora_core_2_install_notes" class="toc">Fedora Core 2 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#fedora_core_1_install_notes" class="toc">Fedora Core 1 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#suse_9.3_install_notes" class="toc">Suse 9.3 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#suse_10.0_install_notes" class="toc">Suse 10.0 install notes</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#windows_install_notes" class="toc">Windows install notes</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installation_help" id="installation_help">Installation help</a></h1>
  <div class="level1">
  
  <p>
  This section provides some information useful to people who want to install gEDA onto their computers.
  </p>
  
  </div>
  <!-- SECTION [1-136] -->
  <h2><a name="how_do_i_install_the_geda_suite" id="how_do_i_install_the_geda_suite">How do I install the gEDA Suite?</a></h2>
  <div class="level2">
  
  <p>
  The easiest way to install the gEDA Suite is to grab the gEDA Suite CD ROM and use it. The instructions are contained in the README available on the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">downloads page</a>.  <strong><em>Note that the CD ROM installer assumes that you are running the Gnome desktop!  The same is true of the gEDA tools:  They use the GTK widget set which underlies Gnome.  If you are running KDE, you need to at least get the Gnome libraries installed on your machine before trying to run the installer.</em></strong>
  </p>
  
  <p>
  The gEDA Suite CD holds the tarballs of more than one dozen popular gEDA applications. It also incorporates a <acronym title="Graphical User Interface">GUI</acronym>-based install wizard which checks your system configuration, asks you a few questions, and then oversees the compilation and installation of the different gEDA applications. The install wizard just automates the normal â??./configure &amp;&amp; make &amp;&amp; make installâ?? process used to build GNU software from source. Therefore, it is more or less platform independent (as long as you are running Linux).
  </p>
  
  <p>
  In the event that the install wizard canâ??t automatically install the gEDA Suite, you can still get the source tarballs off the CD and build them manually. The instructions are available from the download web page, as well as in the INSTALL file on the CD.
  </p>
  
  <p>
  Also, people have created RedHat RPMs, Debian Debs, and Mac OSX Fink packages if you prefer to install that way. These binary distributions are available on the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">downloads page</a>. Finally, source tarballs for all programs are also available on the <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">downloads page</a>.
  </p>
  
  <p>
  By the way, itâ??s always a good idea to install gEDA into its own directory. That way, when you want to upgrade the package you just need to delete the directory and re-install. (This advice is true for any large suite of applications in unix.) More on this below.
  </p>
  
  <p>
  Finally, if the instructions here arenâ??t enough, David Hart has placed a useful and detailed <a href="http://www.offramp.com/Lab-Install/doku.php?id=fc4#create_user_geda_account_and_install_geda_tool_suite"; class="urlextern" title="http://www.offramp.com/Lab-Install/doku.php?id=fc4#create_user_geda_account_and_install_geda_tool_suite";  rel="nofollow">guide for configuring and installing gEDA</a> (for Fedora Core 4, but probably helpful with other distros too), as well as a <a href="http://www.offramp.com/Lab-Install/doku.php?id=fc4#geda_tutorial"; class="urlextern" title="http://www.offramp.com/Lab-Install/doku.php?id=fc4#geda_tutorial";  rel="nofollow">gEDA Tutorial</a> for new users.
  </p>
  
  </div>
  <!-- SECTION [137-2495] -->
  <h2><a name="how_do_i_uninstall_the_geda_suite" id="how_do_i_uninstall_the_geda_suite">How do I uninstall the gEDA Suite?</a></h2>
  <div class="level2">
  
  <p>
  As of this writing, no advanced method to uninstall the gEDA Suite exists. Unlike a certain commercial operating system, Linux (and unix) were not designed with the goal of easy package management in mind, and we all suffer with this legacy.
  </p>
  
  <p>
  Therefore, we recommend that you install the gEDA Suite into its own special directory. For example, the CD Installer will place the Suiteâ??s executables into <strong><code>${HOME}/geda-install</code></strong> by default. Then, if you need to uninistall the gEDA Suite, you can just delete the entire directory.
  </p>
  
  <p>
  <span class="hilited">(More advanced methods to install/uninstall packages on Linux/unix also exist. Could somebody please write about them here?)</span>
  </p>
  
  </div>
  <!-- SECTION [2496-3207] -->
  <h2><a name="why_would_i_want_to_uninstall_the_geda_suite" id="why_would_i_want_to_uninstall_the_geda_suite">Why would I want to uninstall the gEDA Suite?</a></h2>
  <div class="level2">
  
  <p>
  Different applications belonging to gEDA/gaf all use the same shared library, libgeda.so. Things in the library change from one gEDA release to another. Therefore, applications are prevented from linking to libgeda.so if their release codes donâ??t match.
  </p>
  
  <p>
  If you need to upgrade one application in gEDA/gaf, you will need to first uninstall your old version, and then install an entirely new set of applications, including the library and all components of gEDA/gaf.
  </p>
  
  <p>
  Alternately, you can install the new gEDA/gaf into a new directory, and then edit your <strong><code>${PATH}</code></strong>, <strong><code>${PKG_CONFIG_PATH}</code></strong>, and <strong><code>${LD_LIBRARY_PATH}</code></strong> environment variables to remove the old directory, and point to the new one. Make sure you do this <strong>before</strong> you try installing the new gEDA/gaf.
  </p>
  
  </div>
  <!-- SECTION [3208-4045] -->
  <h2><a name="aaaargh_i_put_the_cd_into_my_reader_and_mounted_the_cd_but_nothing_happened" id="aaaargh_i_put_the_cd_into_my_reader_and_mounted_the_cd_but_nothing_happened">Aaaargh! I put the CD into my reader, and mounted the CD, but nothing happened!</a></h2>
  <div class="level2">
  
  <p>
   Amazingly enough, some people simply copy the installer .iso file using â??cpâ?? onto a blank CD, and then try to use it. This wonâ??t work. You need to â??burnâ?? a CD with the .iso in a way which writes the whole filesystem directly onto the CDROM. The linux/unix command to do this is usually â??cdrecordâ??, or perhaps a <acronym title="Graphical User Interface">GUI</acronym> derivative of this utility. Donâ??t just â??cpâ?? the .iso file onto a blank CD!
  </p>
  
  <p>
  Many modern Linux distributions will not automatically run executables on installed media. This is a security precaution. To overcome this, you need to mount the CD in a way which grants permission for executables to run. For example, in Gentoo and Debian you should mount the CD ROM this way: 
  </p>
  <pre class="code">mount -o exec -t iso9660 /dev/cdrom /mnt/cdrom</pre>
  
  <p>
  The detailed flag or mount point relevant to your distribution might be a little different; read the manual for mount (â??man mountâ??) if you have any questions about how to do this.
  </p>
  
  <p>
  After you have mounted the CD with execute permission, you can then run the installer from the command line like this: 
  </p>
  <pre class="code">/mnt/cdrom/installer</pre>
  
  <p>
  At this point, the install wizardâ??s <acronym title="Graphical User Interface">GUI</acronym> should pop up, and you can get to installing. If you canâ??t install, please try doing an â??lsâ?? of the CD to see if it is readable. That is, do this: 
  </p>
  <pre class="code">ls -l /mnt/cdrom/</pre>
  
  <p>
  And verify that you get a directory listing instead of an error message (or nothing at all).
  </p>
  
  </div>
  <!-- SECTION [4046-5564] -->
  <h2><a name="help_me_i_m_trying_to_install_using_the_cd_rom_but_the_install_wizard_says_i_have_an_error" id="help_me_i_m_trying_to_install_using_the_cd_rom_but_the_install_wizard_says_i_have_an_error">Help me! I'm trying to install using the CD ROM, but the install wizard says I have an error!</a></h2>
  <div class="level2">
  
  <p>
   First off, please keep in mind that the CD ROMâ??s installer only works on Linux. The CD ROM installer will not work on Sun, BSD, or Mac OSX, and it certainly wonâ??t work on Windows.
  </p>
  
  <p>
  As a general rule, if you are having problems installing gEDA from the CD, here are the things you can try:
  </p>
  <ol>
  <li class="level1"><div class="li"> If you run the installer with the <strong><code>â??log</code></strong> flag set, it will place a file called Install.log into your local directory (where you are running the installer). This file is a log of all commands issued and all responses generated during the install process. It allows you to save the data displayed on the log window displayed during the install process. Running the installer with <strong><code>â??log</code></strong> set is a good idea if you are experiencing problems; you can send your Install.log file to an expert who might be able to diagnose your problem. More on this later.</div>
  </li>
  <li class="level1"><div class="li"> After experiencing a problem, the first thing you should do is look through the gEDA Wiki. Itâ??s quite likely that somebody has already experienced your problem, reported it, and a work around has been found and posted. Different Linux distributions have displayed different problems in the past. Depending upon your distribution, consult the help sections below.</div>
  </li>
  <li class="level1"><div class="li"> If no mention of your specific problem has been posted on the Wiki, try a Google search. GEDA tips and tricks show up in many different places on the web, and Google can find them for you. Also, the geda-user list is continually indexed by Google. Since people frequently post bugs and bug workarounds there, Google will help you find these reports.</div>
  </li>
  <li class="level1"><div class="li"> Next, try posting a question on the geda-user e-mail list. Note that you must first subscribe to the geda-user e-mail list before posting any e-mail to the list. Others may have already developed a work-around for your problem. Some of the experts hang out on that list, and might offer a few helpful suggestions.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [5565-7576] -->
  <h2><a name="waaaa_the_installation_ran_to_completion_but_i_get_a_segfault_or_other_problem_when_i_run_gschem_or_gattrib_or_gnetlist_or" id="waaaa_the_installation_ran_to_completion_but_i_get_a_segfault_or_other_problem_when_i_run_gschem_or_gattrib_or_gnetlist_or">Waaaa! The installation ran to completion, but I get a segfault (or other problem) when I run gschem (or gattrib, or gnetlist, or. . . )!</a></h2>
  <div class="level2">
  
  <p>
  After you install the gEDA Suite off the CD ROM, make sure you do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Set your <strong><code>${PATH}</code></strong> to point to the location where your new gEDA executables live (for example, <strong><code>/home/your-name/geda-install/bin</code></strong>). Make sure that you remove pointers to old gEDA editions, if they exist. You should not only set the <strong><code>${PATH}</code></strong> in your current shell, but you should also set it in your shell config scripts (i.e. .bashrc or .cshrc)</div>
  </li>
  <li class="level1"><div class="li"> Type â??rehashâ?? to update your executable search path.</div>
  </li>
  <li class="level1"><div class="li"> Set your <strong><code>${LD_LIBRARY_PATH}</code></strong> to point to the location where your new gEDA executables live (for example, <strong><code>/home/your-name/geda-install/lib</code></strong>). Make sure to remove pointers to old gEDA editions, if they exist. You should not only set the <strong><code>${LD_LIBRARY_PATH}</code></strong> in your current shell, but you should also set it in your shell config scripts (i.e. .bashrc or .cshrc)</div>
  </li>
  <li class="level1"><div class="li"> Run â??su -c ldconfigâ?? to tell the kernal where to find your new libgeda.so.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [7577-8704] -->
  <h2><a name="fedora_core_4_install_notes" id="fedora_core_4_install_notes">Fedora Core 4 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_fc4.html" class="wikilink1" title="geda:fc4">FC4 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [8705-8783] -->
  <h2><a name="fedora_core_3_install_notes" id="fedora_core_3_install_notes">Fedora Core 3 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_fc3.html" class="wikilink1" title="geda:fc3">FC3 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [8784-8862] -->
  <h2><a name="fedora_core_2_install_notes" id="fedora_core_2_install_notes">Fedora Core 2 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_fc2.html" class="wikilink1" title="geda:fc2">FC2 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [8863-8941] -->
  <h2><a name="fedora_core_1_install_notes" id="fedora_core_1_install_notes">Fedora Core 1 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_fc1.html" class="wikilink1" title="geda:fc1">FC1 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [8942-9020] -->
  <h2><a name="suse_9.3_install_notes" id="suse_9.3_install_notes">Suse 9.3 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_suse_9.html" class="wikilink1" title="geda:suse_9.3">SuSE 9.3 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [9021-9104] -->
  <h2><a name="suse_10.0_install_notes" id="suse_10.0_install_notes">Suse 10.0 install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_suse_10.html" class="wikilink1" title="geda:suse_10.0">SuSE 10.0 notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [9105-9191] -->
  <h2><a name="windows_install_notes" id="windows_install_notes">Windows install notes</a></h2>
  <div class="level2">
  
  <p>
  <a href="geda_cygwin.html" class="wikilink1" title="geda:cygwin">Cygwin notes available here</a>
  </p>
  
  </div>
  <!-- SECTION [9192-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_installed_plugins.html
  
  Index: geda_installed_plugins.html
  ===================================================================
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   lang="en" dir="ltr">
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  <body>
  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#installed_plugins" class="toc">Installed plugins</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#hilited" class="toc">hilited</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#xterm" class="toc">xterm</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="installed_plugins" id="installed_plugins">Installed plugins</a></h1>
  <div class="level1">
  
  <p>
  The following plugins have been installed, to give the gEDA Project Wiki additional functionality.
  </p>
  
  </div>
  <!-- SECTION [1-132] -->
  <h2><a name="hilited" id="hilited">hilited</a></h2>
  <div class="level2">
  
  <p>
  The &ldquo;hilited&rdquo; plugin acts as a yellow highlighter. Surround the text you want to highlight with double-exclamation marks.
  </p>
  
  <p>
  Example:<br/>
   
  </p>
  <pre class="code">Sample text !!highlighted!! in a paragraph.</pre>
  
  <p>
  becomes:<br/>
   Sample text <span class="hilited">highlighted</span> in a paragraph.
  </p>
  
  </div>
  <!-- SECTION [133-400] -->
  <h2><a name="xterm" id="xterm">xterm</a></h2>
  <div class="level2">
  
  <p>
  The &ldquo;xterm&rdquo; plugin allows you to embed preformatted text.<br/>
   The <code>&lt;</code>xterm<code>&gt;&lt;</code>/xterm<code>&gt;</code> tags surround the text you wish to embed.<br/>
   The <code>&lt;</code>xterm<code>&gt;&lt;</code>/xterm<code>&gt;</code> tags differ from the built-in <code>&lt;</code>code<code>&gt;&lt;</code>/code<code>&gt;</code> tags as follows:
  </p>
  <ul>
  <li class="level1"><div class="li"> The text is indented.</div>
  </li>
  <li class="level1"><div class="li"> You can emphasize parts of the text.</div>
  </li>
  <li class="level1"><div class="li"> The text will have a lightgreen background, so it will stand out on the wiki-page.</div>
  </li>
  </ul>
  
  <p>
   Example:<br/>
   The following is indented from the current section&rsquo;s left margin: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">embedded <strong>preformatted</strong> words</font></pre>
  </p>
  
  <p>
  The following shows how the preformatted text will follow the <acronym title="Extensible HyperText Markup Language">XHTML</acronym> indent levels:
  </p>
  <ul>
  <li class="level1"><div class="li"> Test line 1.</div>
  </li>
  <li class="level1"><div class="li"> Test line 2.<br/>
   <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">Indented test line 3.</font></pre></div>
  </li>
  <li class="level1"><div class="li"> Test line 4.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [401-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_kig_howto.html
  
  Index: geda_kig_howto.html
  ===================================================================
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    <meta name="date" content="2006-04-20T11:02:57-0400" />
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  </head>
  <body>
  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#how_to_setup_keymapping_in_gschem" class="toc">How To Setup Keymapping In gschem</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#about_this_document" class="toc">About this document</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#functionality" class="toc">Functionality</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#keymaps" class="toc">Keymaps</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#an_example_on_keymaps" class="toc">An example on keymaps</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#description_of_keys" class="toc">Description of keys</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#actions" class="toc">Actions</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#function_calls" class="toc">Function calls</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#another_keymap" class="toc">Another keymap</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#where_are_the_key_mappings_stored" class="toc">Where are the key mappings stored</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#appendix_a_--_dictionary" class="toc">Appendix A -- Dictionary</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#appendix_b_--_built-in_actions_in_gschem" class="toc">Appendix B -- Built-in actions in gschem</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="how_to_setup_keymapping_in_gschem" id="how_to_setup_keymapping_in_gschem">How To Setup Keymapping In gschem</a></h1>
  <div class="level1">
  
  <p>
  by: Stefan Petersen, spe@xxxxxxxxxxxxx This document is released under <a href="http://www.fsf.org/copyleft/gpl.html"; class="urlextern" title="http://www.fsf.org/copyleft/gpl.html";  rel="nofollow">GPL</a>
  </p>
  
  <p>
  1999-07-24
  </p>
  
  </div>
  <!-- SECTION [1-177] -->
  <h2><a name="about_this_document" id="about_this_document">About this document</a></h2>
  <div class="level2">
  
  <p>
  The purpose of this document is to try to explain how key mapping works in gEDA/gschem schematic entry program. It uses the langauge Scheme a lot, which is a Lisp-dialect and is used in gschem as a scripting language. If you&rsquo;re not familiar with this language, please see the dictionary (see appendix A, page X, for a short description of common data structures used in Scheme.
  </p>
  
  </div>
  <!-- SECTION [178-588] -->
  <h2><a name="functionality" id="functionality">Functionality</a></h2>
  <div class="level2">
  
  <p>
  When you press a button in gschem, a Scheme function is called. This function (press-key) accepts one argument, the name of the pressed key. Then there are Scheme routines to evaluate which key you pressed and call the appropriate action.<br/>
   Since the evaluation routines are written in Scheme it&rsquo;s simple to change the behaviour of what happens when you presses a key. You can implement macros or do several things at each key press. For example, the &ldquo;repeat-last-key&rdquo; command is implemented completly in Scheme.
  </p>
  
  </div>
  <!-- SECTION [589-1128] -->
  <h2><a name="keymaps" id="keymaps">Keymaps</a></h2>
  <div class="level2">
  
  <p>
  The current implementation is built-up around &ldquo;keymaps&rdquo;. A keymap is a list with pairs. Each pairs first element (the car-element) is which key to react on, and the second element (cdr) is a &ldquo;what-to-do-next&rdquo;. This can either be an action, a function to call or another keymap.
  </p>
  
  </div>
  <!-- SECTION [1129-1427] -->
  <h3><a name="an_example_on_keymaps" id="an_example_on_keymaps">An example on keymaps</a></h3>
  <div class="level3">
  
  <p>
  Two simple examples of keymaps are seen in Figure 1 and Figure 2.
  </p>
  <pre class="code">(define global-keymap
    '((&quot;Escape&quot; . cancel)
      (&quot;a&quot; . add-keymap)))</pre>
  
  <p>
  Figure 1: First example of an simple keymap
  </p>
  
  <p>
  In figure 1 is the keymap called global-keymap. This keymap is the first keymap used. If you for example press the &lsquo;a&rsquo;-key, global-keymap tells us that next key pressed will be interpreted by add-keymap (see figure 2).
  </p>
  <pre class="code">(define add-keymap
    '((&quot;c&quot; . add-component)
      (&quot;a&quot; . add-attribute)
      (&quot;n&quot; . add-net-hotkey)))</pre>
  
  <p>
  Figure 2: Second example of an simple keymap
  </p>
  
  <p>
  If you, after you pressed &lsquo;a&rsquo;, press a &lsquo;c&rsquo; the built-in action add-component comes to live. This is exactly what had happend if you had selected Add, Component...in the menubar.<br/>
   When an action has been performed the current keymap is reset back to global-keymap.<br/>
   Available built-in actions are listed in appendix B.
  </p>
  
  </div>
  <!-- SECTION [1428-2357] -->
  <h3><a name="description_of_keys" id="description_of_keys">Description of keys</a></h3>
  <div class="level3">
  
  <p>
  The key are described as: 
  </p>
  <table class="inline">
  	<tr>
  		<td> For a </td><td> &ldquo;a&rdquo; </td>
  	</tr>
  	<tr>
  		<td class="leftalign"> For Shift-A  </td><td> &ldquo;Shift A&rdquo; </td>
  	</tr>
  	<tr>
  		<td> For Control-a </td><td> &ldquo;Control a&rdquo; </td>
  	</tr>
  	<tr>
  		<td> For Alt-a </td><td> &ldquo;Alt a&rdquo; </td>
  	</tr>
  </table>
  <br />
  
  <p>
   There are a few simple rules to follow when keys for a new keymap is defined:
  </p>
  <ul>
  <li class="level1"><div class="li"> Everything is case sensitive</div>
  </li>
  <li class="level1"><div class="li"> At this point in time you can only have one modifier (shift, control, alt) at a time.</div>
  </li>
  <li class="level1"><div class="li"> Keys must be unique in each keymap, especially the global one</div>
  </li>
  <li class="level1"><div class="li"> Strings (without any modifers) are the same strings specified for the keys in the file /usr/lib/X11/XKeysymDB (at least on a linux box) </div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2358-2925] -->
  <h3><a name="actions" id="actions">Actions</a></h3>
  <div class="level3">
  
  <p>
  The built-in actions that can be called are listed in Appendix B.<br/>
   Sometimes you may notice that there are similar actions, like edit-rotate-90 and edit-rotate-90-hotkey. They do the same thing, just that the -hotkey actions is run immediately, while the other wait for you to select something.
  </p>
  
  </div>
  <!-- SECTION [2926-3240] -->
  <h3><a name="function_calls" id="function_calls">Function calls</a></h3>
  <div class="level3">
  
  <p>
  If the cdr-element is an ordinary Scheme function that function is called. The function can&rsquo;t receive any arguments.<br/>
   This can be used if you want to do complex tasks, like several actions in a row or do some calculation. You can do rather advanced actions since the Guile dialect of Scheme used in gschem is extended from plain Scheme. For further information on Guile, please see the Guile documentation.
  </p>
  
  </div>
  <!-- SECTION [3241-3674] -->
  <h3><a name="another_keymap" id="another_keymap">Another keymap</a></h3>
  <div class="level3">
  
  <p>
  If the cdr-element is another keymap then that command is a multi-key command, ie you need to press at least two keys to cause an action. The first key is desribed in the first keymap, which points to the next keymap. The second keymap describes what should happen when the second key is pressed.
  </p>
  
  </div>
  <!-- SECTION [3675-3997] -->
  <h2><a name="where_are_the_key_mappings_stored" id="where_are_the_key_mappings_stored">Where are the key mappings stored</a></h2>
  <div class="level2">
  
  <p>
  The keymap is stored in the startup file for gschem, namely <code>&lt;startpath, typically /usr/local&gt;/share/gEDA/system-gschemrc</code>.<br/>
   You can then redefine or add keymaps as you like (I think) in your local setup file for gschem, ~/.gEDA/gschemrc
  </p>
  
  <p>
  The Scheme functions used to resolve keypresses to actions are stored at <code>&lt;startpath, typically /usr/local&gt;/share/gEDA/scheme/gschem.scm</code>. This is configurable in the gschemrc files.
  </p>
  
  </div>
  <!-- SECTION [3998-4471] -->
  <h3><a name="appendix_a_--_dictionary" id="appendix_a_--_dictionary">Appendix A -- Dictionary</a></h3>
  <div class="level3">
  <table class="inline">
  	<tr>
  		<td> <strong>function</strong> </td><td>A subprogram in Scheme, C or other programming languages. </td>
  	</tr>
  	<tr>
  		<td><strong>action</strong> </td><td>What gschem (in this case) does when you press a key or a set of keys. </td>
  	</tr>
  	<tr>
  		<td><strong>list</strong> </td><td>A data structure very common in Lisp-looking languages like Scheme. Simply put, a long list of values. </td>
  	</tr>
  	<tr>
  		<td><strong>pair</strong> </td><td>(also dotted pair) A datstructure also very common in Lisp-looking languages. </td>
  	</tr>
  	<tr>
  		<td><strong>car element</strong> </td><td>First element in a pair. Since lists are decendents from pairs, car is also the first element in a list. </td>
  	</tr>
  	<tr>
  		<td><strong>cdr element</strong> </td><td>(pronounced cudr) The second element in a pair. In the list case it denotes the rest of list. </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [4472-5116] -->
  <h2><a name="appendix_b_--_built-in_actions_in_gschem" id="appendix_b_--_built-in_actions_in_gschem">Appendix B -- Built-in actions in gschem</a></h2>
  <div class="level2">
  
  <p>
  Run: <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">grep gh_register_procedure_0_0 gschem/src/g_register.c</font></pre>
  </p>
  
  <p>
  and do some work in emacsen.
  </p>
  
  <p>
  <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">file-new-window
  file-new
  file-open
  file-script
  file-save
  file-save-as
  file-save-all
  file-print
  file-image
  file-close-window
  file-quit
  edit-select
  edit-copy
  edit-copy-hotkey
  edit-move
  edit-move-hotkey
  edit-delete
  edit-rotate-90
  edit-rotate-90-hotkey
  edit-mirror
  edit-mirror-hotkey
  edit-slot
  edit-color
  edit-edit
  edit-lock
  edit-unlock
  edit-translate
  edit-embed
  edit-unembed
  edit-hidden
  view-redraw
  view-zoom-full
  view-zoom-limits
  view-zoom-in
  view-zoom-out
  view-zoom-box
  view-zoom-box-hotkey
  view-pan
  view-pan-hotkey
  view-update-nets
  page-manager
  page-next
  page-prev
  page-new
  page-close
  page-discard
  page-print
  add-component
  add-attribute
  add-net
  add-net-hotkey
  add-text
  add-line
  add-line-hotkey
  add-box
  add-box-hotkey
  add-circle
  add-circle-hotkey
  add-arc
  add-arc-hotkey
  add-pin
  add-pin-hotkey
  hierarchy-open-symbol
  attributes-attach
  attributes-detach
  attributes-show-name
  attributes-show-value
  attributes-show-both
  attributes-visibility-toggle
  options-text-size
  options-snap-size
  options-action-feedback
  options-grid
  options-snap
  options-show-log-window
  options-show-coord-window
  misc-misc
  cancel</font></pre> 
  </p>
  
  </div>
  <!-- SECTION [5117-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_master_attributes_list.html
  
  Index: geda_master_attributes_list.html
  ===================================================================
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    <meta name="date" content="2006-04-22T11:15:17-0400" />
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  <body>
  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gaf_master_attribute_document" class="toc">gEDA/gaf Master Attribute Document</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_are_attributes" class="toc">What are Attributes?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#symbol_only_attributes" class="toc">Symbol only Attributes</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#device" class="toc">device</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#graphical" class="toc">graphical</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#description" class="toc">description</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#author" class="toc">author</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#comment" class="toc">comment</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pinseq" class="toc">pinseq</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pinnumber" class="toc">pinnumber</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pintype" class="toc">pintype</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pinlabel" class="toc">pinlabel</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#numslots" class="toc">numslots</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#slotdef" class="toc">slotdef</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#footprint" class="toc">footprint</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#documentation" class="toc">documentation</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#schematic_only_attributes" class="toc">Schematic only Attributes</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#netname" class="toc">netname</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#source" class="toc">source</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#symbol_and_schematic_attributes" class="toc">Symbol and Schematic Attributes</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#refdes" class="toc">refdes</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#slot" class="toc">slot</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#net" class="toc">net</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#value" class="toc">value</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#symversion" class="toc">symversion</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#obsolete_attributes" class="toc">Obsolete Attributes</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#uref" class="toc">uref</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#name" class="toc">name</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#label" class="toc">label</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pin" class="toc">pin#</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#slot1" class="toc">slot#</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#type" class="toc">type</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#email" class="toc">email</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_revision_history" class="toc">Document Revision History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gaf_master_attribute_document" id="geda_gaf_master_attribute_document">gEDA/gaf Master Attribute Document</a></h1>
  <div class="level1">
  
  <p>
  by: Ales V. Hvezda, ahvezda@xxxxxxxxxxxxx
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  July 6th, 2004
  </p>
  
  </div>
  <!-- SECTION [1-187] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  This document describes all the attributes used in in gEDA/gaf (<acronym title="GNU General Public License">GPL</acronym>&lsquo;d Electronic Design Automation / Gschem And Friends). This document is broken down into several section: this overview, symbol only attributes, schematic only attributes, attributes which can appear in both symbols and schematics, and attributes which are obsolete or deprecated.<br/>
   In this document, attribute names are in <strong>bold</strong> and examples are in the <code>typewriter</code> font.
  </p>
  
  </div>
  <!-- SECTION [188-654] -->
  <h2><a name="what_are_attributes" id="what_are_attributes">What are Attributes?</a></h2>
  <div class="level2">
  
  <p>
  Attributes in the gEDA/gaf system are nothing more than text items which take on the form: <strong>name</strong>=value. Name can be anything just as long as it doesn&rsquo;t contain a equals sign. Value can also be anything just as long as it is something (vs nothing). <strong>name</strong>= (without a value part) is not a valid attribute. Also, there cannot be any spaces immediately before or after the equals sign.<br/>
   Attributes can be attached to some part of the symbol. If the attribute conveys information specific to an object, then the attribute should be attached directly to the object, otherwise the attribute should be free standing or  oating. Free standing attributes just exist in the symbol file as text items which take on the form <strong>name</strong>=value.
  </p>
  
  </div>
  <!-- SECTION [655-1423] -->
  <h2><a name="symbol_only_attributes" id="symbol_only_attributes">Symbol only Attributes</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [1424-1458] -->
  <h3><a name="device" id="device">device</a></h3>
  <div class="level3">
  
  <p>
  <strong>device</strong>= is the device name of the symbol and is required by gnetlist.<br/>
   <strong>device</strong>= should be placed somewhere in the symbol and made invisible. This is a free standing or  oating attribute. If the object is a graphic then <strong>device</strong>= should be set to none (<strong>device</strong>=none) and attach a <a href="#graphical" title="geda:master_attributes_list &crarr;" class="wikilink1">graphical</a>= attribute. Do not confuse this attribute with just having a text label which the device name. Do not put spaces into the device name; there are some programs which dislike spaces in the device specifier. Generally the device name is in all caps.<br/>
   Examples: <code>device=7400 device=CONNECTOR 10 device=NPN TRANSISTOR</code>
  </p>
  
  </div>
  <!-- SECTION [1459-2100] -->
  <h3><a name="graphical" id="graphical">graphical</a></h3>
  <div class="level3">
  
  <p>
  Symbols which have no electrical or circuit significance need a <strong>graphical</strong>=1 attribute. Symbols like titleboxes are purely graphical symbols. Any symbol which has <strong>graphical</strong>=1 is ignored by gnetlist.<br/>
   <strong>graphical</strong>=1 should exist somewhere in the symbol and made invisible. This is a free standing or  oating attribute. Don&rsquo;t forget to set <a href="#device" title="geda:master_attributes_list &crarr;" class="wikilink1">device</a>=none.<br/>
   Example: <code>graphical=1</code>
  </p>
  
  </div>
  <!-- SECTION [2101-2513] -->
  <h3><a name="description" id="description">description</a></h3>
  <div class="level3">
  
  <p>
  The <strong>description</strong> attribute provides a simple one line description of what the symbol is supposed to represent.<br/>
   Example: <code>description=4 NAND gates with 2 inputs</code>
  </p>
  
  </div>
  <!-- SECTION [2514-2704] -->
  <h3><a name="author" id="author">author</a></h3>
  <div class="level3">
  
  <p>
  The <strong>author</strong> attribute identifies the name of the author of this symbol and their e-mail address. This attribute is optional, but it is nice to know who created which symbols. It also serves the purpose of known who to contact if there are questions about the intent(s) of the symbol. This attribute is free form and it can also include people&rsquo;s names who modified the symbol as well as multiple e-mail addresses. It is probably also a good idea to obfuscate the e-mail address so it is not harvested for spam purposes.<br/>
   Example: <code>author=Ales Hvezda ahvezdaATgeda.seul.org</code>
  </p>
  
  </div>
  <!-- SECTION [2705-3301] -->
  <h3><a name="comment" id="comment">comment</a></h3>
  <div class="level3">
  
  <p>
  The <code>comment</code> attribute can contain anything. This attribute can convey any additional information which might not fit into any other attribute. There can be multiple instances of this attribute.<br/>
   Example: <code>comment=This is a comment inside a symbol</code>
  </p>
  
  </div>
  <!-- SECTION [3302-3575] -->
  <h3><a name="pinseq" id="pinseq">pinseq</a></h3>
  <div class="level3">
  
  <p>
  This attribute is used to give each pin an unique number or sequence. All pins must have a <strong>pinseq</strong>=# attribute attached to the pin object. This attribute should be hidden. This attribute is used extensively by gschem and gnetlist.<br/>
   In some backends (especially the SPICE backend), gnetlist will output pins in the order of increasing pin sequence. The sequence numbers start at 1 and should increase without skipping any numbers. This attribute is not the pin number (i.e. device pin numbers, like GND is 7 on TTL). For pin numbers see the <a href="#pinnumber" title="geda:master_attributes_list &crarr;" class="wikilink1">pinnumber</a> attribute.<br/>
   Examples: <code>pinseq=1 pinseq=2 pinseq=3</code><br/>
  
  </p>
  
  <p>
  This attribute replaces the obsolete <strong>pin#</strong>=# attribute.
  </p>
  
  </div>
  <!-- SECTION [3576-4268] -->
  <h3><a name="pinnumber" id="pinnumber">pinnumber</a></h3>
  <div class="level3">
  
  <p>
  This attribute is the pin number (i.e. like GND is 7 on 74 TTL). All pins must have a <strong>pinnumber</strong>=# attribute attached to the pin object.<br/>
   You can have numbers or letters for the value. This attribute should be visible with the value only visible. You also need a <a href="#pinseq" title="geda:master_attributes_list &crarr;" class="wikilink1">pinseq</a> attribute.<br/>
   Examples: <code>pinnumber=1 pinnumber=13 pinnumber=A0</code><br/>
  
  </p>
  
  <p>
  This attribute replaces the obsolete pin#=# attribute.
  </p>
  
  </div>
  <!-- SECTION [4269-4691] -->
  <h3><a name="pintype" id="pintype">pintype</a></h3>
  <div class="level3">
  
  <p>
  Each pin must have a <strong>pintype</strong>=value attribute attached to it and should be make hidden. Table 1 shows valid values for this attribute.<br/>
   This attribute is not used extensively in the symbol library, but it will be used for DRC and netlisting.<br/>
   Examples: <code>pintype=clk pintype=in pintype=pas</code><br/>
   
  </p>
  <table class="inline">
  	<tr>
  		<td>in</td><td>Input</td>
  	</tr>
  	<tr>
  		<td>out</td><td>Output</td>
  	</tr>
  	<tr>
  		<td>io</td><td>Input/Output</td>
  	</tr>
  	<tr>
  		<td>oc</td><td>Open collector</td>
  	</tr>
  	<tr>
  		<td>oe</td><td>Open emitter</td>
  	</tr>
  	<tr>
  		<td>pas</td><td>Passive</td>
  	</tr>
  	<tr>
  		<td>tp</td><td>Totem pole</td>
  	</tr>
  	<tr>
  		<td>tri</td><td>Tristate (high impedance)</td>
  	</tr>
  	<tr>
  		<td>clk</td><td>Clock</td>
  	</tr>
  	<tr>
  		<td>pwr</td><td>Power/Ground</td>
  	</tr>
  	<tr>
  		<td colspan="2">Table 1: pintype values</td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [4692-5210] -->
  <h3><a name="pinlabel" id="pinlabel">pinlabel</a></h3>
  <div class="level3">
  
  <p>
  This attribute labels a pin object. This attribute is primarily used by gnetlist to support hierarchical designs.<br/>
   This attribute must be attached to the pin and be left visible. Please make this attribute green (instead of the default attribute yellow).<br/>
   Examples: <code>pinlabel=A0 pinlabel=DATA1 pinlabel=CLK</code><br/>
  
  </p>
  
  </div>
  <!-- SECTION [5211-5544] -->
  <h3><a name="numslots" id="numslots">numslots</a></h3>
  <div class="level3">
  
  <p>
  If a component has multiple slots in a physical package (such as a 7400 (NAND) which has 4 NANDs per package) then you need a <strong>numslots</strong>=# attribute. The # is the number of slots that are in a physical device. <strong>numslots</strong>=# should exist somewhere in the symbol and be made invisible. This is a free standing or floating attribute. If the symbol does not need slotting, then put <strong>numslots</strong>=0 into the symbol file.<br/>
   Example: <code>numslots=4</code>
  </p>
  
  </div>
  <!-- SECTION [5545-6008] -->
  <h3><a name="slotdef" id="slotdef">slotdef</a></h3>
  <div class="level3">
  
  <p>
  If a component has multiple slots in a physical package then you must attach a <strong>slotdef</strong>=slotnumber:#,#,#... for every device inside the physical package.<br/>
   The slotnumber corresponds to the slot number. The colon after the slot number is required. For example, if a device has 4 slots then there would be <strong>slotdef</strong>=1:..., <strong>slotdef</strong>=2:..., <strong>slotdef</strong>=3:..., and slotdef=4:... attributes somewhere in the symbol and be made invisible. This is a free standing or  oating attribute.<br/>
   The #&rsquo;s have a one-to-one correspondence to the <strong>pinseq</strong> attributes and specify which <strong>pinnumber</strong>=# is used during display (gschem) or netlisting (gnetlist).<br/>
   It is recommended that all symbols which have slots have a <a href="#slot" title="geda:master_attributes_list &crarr;" class="wikilink1">slot</a>=1 attribute attached in the same fashion as the <a href="#device" title="geda:master_attributes_list &crarr;" class="wikilink1">device</a>= attribute.<br/>
   See 7400-1.sym as a concrete example.<br/>
   Examples: <code>slotdef=1:1,2,3 slotdef=2:4,5,6 slotdef=3:7,8,9</code><br/>
   This attribute replaces the obsolete <strong>slot</strong>#=# attribute.
  </p>
  
  </div>
  <!-- SECTION [6009-6987] -->
  <h3><a name="footprint" id="footprint">footprint</a></h3>
  <div class="level3">
  
  <p>
  <strong>footprint</strong>=package name should exist somewhere in the symbol and be made invisible. This attribute is used by gnetlist and primarily for the PCB package.<br/>
   Attach this attribute just like the <a href="#device" title="geda:master_attributes_list &crarr;" class="wikilink1">device</a>= attribute. This is a free standing or floating attribute.<br/>
   package name is the pcb footprint or package type like DIP14 or DIP40. Although this attribute in principle is pcb package dependent, gEDA/gaf conventions exist to make this attribute as portable as possible, allowing for easy collaboration and sharing between users. See the <a href="http://geda.seul.org/wiki/geda:scg#footprint_naming_conventions"; class="wikilink1" title="geda:scg">Footprint naming conventions in the Symbol Creation Guide</a>.<br/>
   If the symbol does not have a footprint, then the value of <strong>footprint</strong>= should be set to none. If the footprint must be overridden in a schematic, then the value of <strong>footprint</strong>= should be set to none. If the footprint is not known, then the value of footprint= should be set to unknown.
  </p>
  
  </div>
  <!-- SECTION [6988-7946] -->
  <h3><a name="documentation" id="documentation">documentation</a></h3>
  <div class="level3">
  
  <p>
  <strong>documentation</strong>=documentation_locator may exist somewhere in the symbol and be made invisible. This attribute is used by gschemdoc to find relevant documentation for the symbol, or rather, the device or component associated with the symbol.<br/>
   Attach this attribute just like the <a href="#device" title="geda:master_attributes_list &crarr;" class="wikilink1">device</a>= attribute. This is a freestanding or floating attribute.<br/>
   documentation_locator is either the base filename of the documentation, or it is the complete Internet <acronym title="Uniform Resource Locator">URL</acronym> (Uniform Resource Locator). If it is the filename, an attempt will be made to search for it in the local gEDA share directory named <strong>documentation</strong>.<br/>
   Filename example: <code>documentation=sn74ls00.pdf</code><br/>
   <acronym title="Uniform Resource Locator">URL</acronym> example: <code>documentation=<a href="http://www-s.ti.com/sc/ds/sn74ls00.pdf"; class="urlextern" title="http://www-s.ti.com/sc/ds/sn74ls00.pdf";  rel="nofollow">http://www-s.ti.com/sc/ds/sn74ls00.pdf</a></code>
  </p>
  
  </div>
  <!-- SECTION [7947-8705] -->
  <h2><a name="schematic_only_attributes" id="schematic_only_attributes">Schematic only Attributes</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [8706-8743] -->
  <h3><a name="netname" id="netname">netname</a></h3>
  <div class="level3">
  
  <p>
  This attribute should be attached to a net object to give it a name. Multiple net names for connected net segments is discouraged. All nets which have the same value are considered electrically connected. This attribute is not valid inside symbols (as you cannot have nets inside of symbols).<br/>
   Examples: <code>netname=DATA0 H netname=CLK L</code><br/>
  
  </p>
  
  </div>
  <!-- SECTION [8744-9103] -->
  <h3><a name="source" id="source">source</a></h3>
  <div class="level3">
  
  <p>
  The source= attribute is used to specify that a symbol has underlying schematics. This attribute is attached directly to a component.<br/>
   This attribute should only be attached to instantiated components in schematics. Attach the attribute to a component and specify the filename (not the path) of the underlying schematic (like block.sch) for the value. The specified schematic must be in a source-library path. This attribute can be attached multiple times with difierent values which basically means that there are multiple underlying schematics.<br/>
   Examples: <code>source=underlying.sch source=memory.sch</code>
  </p>
  
  </div>
  <!-- SECTION [9104-9725] -->
  <h2><a name="symbol_and_schematic_attributes" id="symbol_and_schematic_attributes">Symbol and Schematic Attributes</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [9726-9769] -->
  <h3><a name="refdes" id="refdes">refdes</a></h3>
  <div class="level3">
  
  <p>
  This attribute is used to specify the reference designator to a particular instantiated component. It must be on ALL components which have some sort of electrical significance. This attribute can also be on the inside of a symbol (it will be promoted, i.e. attached to the outside of the symbol, if it is visible) to provide a default refdes value (such as U?).<br/>
   Examples: <code>refdes=U1 refdes=R10 refdes=CONN1</code><br/>
  
  </p>
  
  </div>
  <!-- SECTION [9770-10201] -->
  <h3><a name="slot" id="slot">slot</a></h3>
  <div class="level3">
  
  <p>
  This attribute is used to specify a slot for a slotted component. It should be attached to an instantiated component. This attribute can also be on the inside of a symbol (it will be promoted, i.e. attached to the outside of the symbol, if it is visible) to provide a default slot.
  </p>
  
  </div>
  <!-- SECTION [10202-10499] -->
  <h3><a name="net" id="net">net</a></h3>
  <div class="level3">
  
  <p>
  The <strong>net</strong>= attribute is used to create power/ground and arbitrary nets. Please see the  <a href="http://geda.seul.org/wiki/geda:na_howto"; class="wikilink1" title="geda:na_howto">net= attribute mini-HOWTO</a> for more info. When this attribute is inside a symbol, it is used to create nets. When this attribute is attached to an instantiated component (in a schematic), then the <strong>net</strong>= can also be used to create new nets and can used to override existing nets.
  </p>
  
  </div>
  <!-- SECTION [10500-10903] -->
  <h3><a name="value" id="value">value</a></h3>
  <div class="level3">
  
  <p>
  Used mainly in the spice backend netlister to specify the value of the various elements. No translation is done on this, and it is placed as is into the netlist.<br/>
   Examples: <code>value=1K value=10V</code><br/>
  
  </p>
  
  </div>
  <!-- SECTION [10904-11119] -->
  <h3><a name="symversion" id="symversion">symversion</a></h3>
  <div class="level3">
  
  <p>
  The <strong>symversion</strong>= attribute is used to version the contents of symbols. Normally this attribute is not present, but once a symbol has been accepted into the main gEDA symbol library and there are changes to it, this attribute must be placed into the symbol file and properly incremented. The value of this attribute takes the following form:<br/>
   <strong>major.minor</strong>
  </p>
  
  <p>
  where major and minor are just plain integers (separated by a period). The major number is incremented when a symbol has some sort of a change which will break or might break an existing schematic. The minor number is only incremented when a cosmetic or very minor change is made to the symbol. The major and minor numbers are not coupled in any way, however, when making major version changes, the minor version number can be reset to zero.<br/>
   If this attribute is inside of a symbol and that symbol is placed onto a schematic, then the <strong>symversion</strong>= attribute will be automatically promoted and attached to the outside of the symbol. During the load of the symbol from disk, the value of the <strong>symversion</strong>= inside the symbol file (if any) and the <strong>symversion</strong>= attached to the symbol (if any) are compared. If the values are the same then the placed symbol matches the disk symbol file, however if the values do not match, then libgeda will output a warning/error message (based on whether it is a major or minor version change).<br/>
   New symbols should not receive this attribute at all. Only when the symbol is change should this attribute be placed into the symbol file and maintained. Users should not attach this attribute manually to instantiated symbols. This attribute should normally be made invisible when placed inside of a symbol file. This attribute is always promoted when it is found inside of a symbol (during component placement).<br/>
   Examples: <code>symversion=1.1</code><br/>
  
  </p>
  
  </div>
  <!-- SECTION [11120-12988] -->
  <h2><a name="obsolete_attributes" id="obsolete_attributes">Obsolete Attributes</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [12989-13020] -->
  <h3><a name="uref" id="uref">uref</a></h3>
  <div class="level3">
  
  <p>
  The uref= attribute is obsolete and cannot not be used. It was used to provide the same information as <a href="#refdes" title="geda:master_attributes_list &crarr;" class="wikilink1">refdes</a>.
  </p>
  
  </div>
  <!-- SECTION [13021-13152] -->
  <h3><a name="name" id="name">name</a></h3>
  <div class="level3">
  
  <p>
  The <strong>name</strong>= attribute should not be attached or appear in any symbol. It is considered ambiguous. <strong>name</strong>= was never used by gEDA/gaf.
  </p>
  
  </div>
  <!-- SECTION [13153-13306] -->
  <h3><a name="label" id="label">label</a></h3>
  <div class="level3">
  
  <p>
  The <strong>label</strong>= attribute is obsolete and cannot be used. It was used to give nets names/labels and to label pins. The replacement attributes for this are <a href="#netname" title="geda:master_attributes_list &crarr;" class="wikilink1">netname</a> and <a href="#pinlabel" title="geda:master_attributes_list &crarr;" class="wikilink1">pinlabel</a> respectively.
  </p>
  
  </div>
  <!-- SECTION [13307-13522] -->
  <h3><a name="pin" id="pin">pin#</a></h3>
  <div class="level3">
  
  <p>
  The <strong>pin#</strong>=# attribute is obsolete and cannot be used. It was used to provide sequence and number information to pins. The replacement attributes for this are <a href="#pinseq" title="geda:master_attributes_list &crarr;" class="wikilink1">pinseq</a> and <a href="#pinnumber" title="geda:master_attributes_list &crarr;" class="wikilink1">pinnumber</a>.
  </p>
  
  </div>
  <!-- SECTION [13523-13731] -->
  <h3><a name="slot1" id="slot1">slot#</a></h3>
  <div class="level3">
  
  <p>
  The <strong>slot#</strong>=# attribute is obsolete and cannot be used. It was used to provide slotting information to components. The replacement attribute for this is <a href="#slotdef" title="geda:master_attributes_list &crarr;" class="wikilink1">slotdef</a>.
  </p>
  
  </div>
  <!-- SECTION [13732-13917] -->
  <h3><a name="type" id="type">type</a></h3>
  <div class="level3">
  
  <p>
  The <strong>type</strong>= attribute is obsolete and cannot be used. It was used to provide type information on pins. The replacement attribute for this is <a href="#pintype" title="geda:master_attributes_list &crarr;" class="wikilink1">pintype</a>.
  </p>
  
  </div>
  <!-- SECTION [13918-14090] -->
  <h3><a name="email" id="email">email</a></h3>
  <div class="level3">
  
  <p>
  The information in this attribute has been merged with <a href="#author" title="geda:master_attributes_list &crarr;" class="wikilink1">author</a>.
  </p>
  
  </div>
  <!-- SECTION [14091-14175] -->
  <h2><a name="document_revision_history" id="document_revision_history">Document Revision History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td>July 14th, 2002</td><td>Created attributes.tex from attributes.txt.</td>
  	</tr>
  	<tr>
  		<td>July 14th, 2002</td><td>Updated doc to be in sync with post-20020527.</td>
  	</tr>
  	<tr>
  		<td>August 25th, 2002</td><td>Added obsolete type= attribute.</td>
  	</tr>
  	<tr>
  		<td>September 14, 2002</td><td>Added description= attribute. Minor xes</td>
  	</tr>
  	<tr>
  		<td>October 7, 2002</td><td>Added doc= attribute; Egil Kvaleberg.</td>
  	</tr>
  	<tr>
  		<td>February 11, 2003</td><td>Added reference to footprint conventions.</td>
  	</tr>
  	<tr>
  		<td>February 23, 2003</td><td>Added author=, email=, and comment= attributes.</td>
  	</tr>
  	<tr>
  		<td>July 6th, 2004</td><td>Added symversion= attributes.</td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [14176-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_mcalc_readme.html
  
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  <h1><a name="mcalc_readme" id="mcalc_readme">mcalc README</a></h1>
  <div class="level1">
  <pre class="code">$Id: geda_mcalc_readme.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
  
  WHAT IS IT?
  ------------
  
  mstrip is a JavaScript based microstrip analysis/synthesis calculator.
  It is designed to be easy to use and fairly accurate.  The accuracy is
  generally within a percent or so for the characteristic impedance which
  greatly exceeds the simplified formulations found in most text books.
  
  
  HOW DO I INSTALL IT?
  --------------------
  
  To install this package, simply copy all the files in the archive to the
  installation directory.
  
  To use this pacakge, just point your JavaScript capable web broswer at
  the file 'index.html'.
  
  
  CAN I COPY IT?
  --------------
  Please refer to the file 'copying.html' for copyright information.
  
  
  IS THERE A HISTORY FILE?
  ------------------------
  Please refer to the file 'verinfo.html' for version history.</pre>
  
  </div>
  </div>
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  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_na_howto.html
  
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#net_attribute_mini-howto" class="toc">net= attribute mini-HOWTO</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_net_attribute_used_for" class="toc">What is the net= attribute used for?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_format_of_the_net_attribute" class="toc">What is the format of the net= attribute?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_you_actually_use_the_net_attribute" class="toc">How do you actually use the net= attribute?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#caveats_bugs" class="toc">Caveats / Bugs</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#example" class="toc">Example</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#final_notes" class="toc">Final notes</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="net_attribute_mini-howto" id="net_attribute_mini-howto">net= attribute mini-HOWTO</a></h1>
  <div class="level1">
  
  <p>
  by: Ales Hvezda
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  October 2nd, 2003
  </p>
  
  <p>
  The information in this document is current as of 19991011.
  </p>
  
  </div>
  <!-- SECTION [1-216] -->
  <h2><a name="what_is_the_net_attribute_used_for" id="what_is_the_net_attribute_used_for">What is the net= attribute used for?</a></h2>
  <div class="level2">
  
  <p>
  The <strong><code>net=</code></strong> attribute is used to specify power, ground, and/or arbitrary nets in the gEDA system.<br/>
   The <strong><code>net=</code></strong> attribute is used instead some of the other systems of specifying power/ground (such as having power/ground pins on symbols or power boxes). Some devices have lots of power/ground pins and having all of these pins on the symbol would increase its size and make it unmanageable. The <strong><code>net=</code></strong> attribute is the power/ground specification of choice in the gEDA system because of its simplicity and versatility. Now having said all this, you can have power/ground pins on a symbol, but gnetlist will probably not recognize these nets connected to these pins as separate power/ground nets. Please keep this in mind as you draw symbols.
  </p>
  
  </div>
  <!-- SECTION [217-1022] -->
  <h2><a name="what_is_the_format_of_the_net_attribute" id="what_is_the_format_of_the_net_attribute">What is the format of the net= attribute?</a></h2>
  <div class="level2">
  
  <p>
  Attributes in gEDA are simple text items which are in the form <code>name=value</code>. All proper attributes follow this form. Attribute names are always lower case, but the value can be upper or lower case. gnetlist and friends are case sensitive. Typically net/signal names by default are upper case.<br/>
   Attribute can be attached to an object or in certain cases (like the <strong><code>net=</code></strong> attribute) can be free oating (not attached to anything). The free floating attributes are also called toplevel attributes.<br/>
   The <strong><code>net=</code></strong> attribute is a text item which takes on the following form: 
  </p>
  <pre class="code">net=signalname:pinname,pinname,pinname,...</pre>
  
  <p>
  where:
  </p>
  <table class="inline">
  	<tr>
  		<td> <strong><code>net=</code></strong> </td><td> The attribute name (always the same, lowercase) </td>
  	</tr>
  	<tr>
  		<td> signalname </td><td> The signal or net being defines (like +5V, GND, etc...) </td>
  	</tr>
  	<tr>
  		<td> pinname </td><td> The pin name (or number) which is assigned to this signal/net (or pin names/numbers) </td>
  	</tr>
  </table>
  <br />
  
  <p>
   The signalname cannot contain the &ldquo;:&rdquo; character (since it is a delimiter). The pinname is the pin name (A1, P2, D1, etc...) or pin number (1, 2, 5, 13, etc...). The pinname cannot contain the &ldquo;,&rdquo; character (since it is also a delimiter). pinnames are typically the same sort of numbers/names like the <code>pin#=#</code> attribute (if you are familiar with that attribute).<br/>
   You can only have ONE signalname per <strong><code>net=</code></strong> attribute, but you can have as many pinnames/numbers as you want.
  </p>
  
  </div>
  <!-- SECTION [1023-2446] -->
  <h2><a name="how_do_you_actually_use_the_net_attribute" id="how_do_you_actually_use_the_net_attribute">How do you actually use the net= attribute?</a></h2>
  <div class="level2">
  
  <p>
  You can place the <strong><code>net=</code></strong> attribute in several places. Here&rsquo;s the list so far:
  </p>
  <ul>
  <li class="level1"><div class="li"> Inside a symbol either as an attached attribute or an unattached attribute (toplevel attribute). Example which creates power/gnd nets: <strong><code>net=GND:7</code></strong> or <strong><code>net=+5V:14</code></strong></div>
  </li>
  <li class="level1"><div class="li"> Outside a symbol (which is instantiated on a schematic) attached as an attribute to override an existing <strong><code>net=</code></strong> created net/signal. Suppose a symbol has a <strong><code>net=GND:7</code></strong> inside it already; attaching this to the symbol: <strong><code>net=AGND:7</code></strong> overrides the GND net (on pin 7) calling it AGND and connects/associates it to pin 7.</div>
  </li>
  <li class="level1"><div class="li"> Outside or inside a symbol to connect a net to a visible pin automatically. This is still untested and still might have some undesirable (negative) side effects. Use with caution.</div>
  </li>
  <li class="level1"><div class="li"> Attached to one of those special power/gnd symbol (like vcc/gnd/vdd) and you can change what that symbol represents. You could change the ground symbol to create a net called DIGITAL GND without editing the symbol (<strong><code>net=DIGITAL_GND:1</code></strong>).<br/>
   In the current symbol (19991011) library there are symbols named <strong>vdd-1.sym</strong>, <strong>vcc-1.sym</strong>, <strong>vee-1.sym</strong>, etc... which do not have a <strong><code>net=</code></strong> attribute inside, so you must attach the <strong><code>net=</code></strong> attribute yourself (in the schematic).<br/>
   There also symbols named 5V-minus-1.sym, 12V-plus-1.sym, 9V-plus-1.sym, etc... which have the appropriate <strong><code>net=</code></strong> attribute in them already (can be overridden though). You can use these symbol as examples of how to use the <strong><code>net=</code></strong> attribute.<br/>
  </div>
  </li>
  </ul>
  
  <p>
  You can have as many <strong><code>net=</code></strong> attributes as you want. Just remember that <strong><code>net=</code></strong> attributes attached to the outside of a symbol override any equivalent internal (inside the symbol) <strong><code>net=</code></strong> attributes. If you run into a case where this doesn&rsquo;t work, please let <strong>ahvezdaATgeda.seul.org</strong>. In fact, send any bug reports to that individual.
  </p>
  
  </div>
  <!-- SECTION [2447-4387] -->
  <h2><a name="caveats_bugs" id="caveats_bugs">Caveats / Bugs</a></h2>
  <div class="level2">
  
  <p>
  The <strong><code>net=</code></strong> attribute/mechanism is fairly new, so there are bound to be bugs (many bugs). Here are some of the identified issues:
  </p>
  <ul>
  <li class="level1"><div class="li"> As of 19991011 almost all of the symbols in the standard library do not have the <strong><code>net=</code></strong> attribute or any other power/ground specifiers. Hopefully this will be updated sometime (any volunteers?).</div>
  </li>
  <li class="level1"><div class="li"> Attach a special power symbol (vcc/gnd) to a already named net will alias (rename) that net to the signalname specified in the <strong><code>net=</code></strong> attribute (in/attached to the vcc/gnd symbol). You can override this (so the reverse is true) by playing with the &ldquo;net-naming-priority&rdquo;. Be careful with this. There might be other &ldquo;aliasing&rdquo; issues which have not been identified yet.</div>
  </li>
  <li class="level1"><div class="li"> Creating a <strong><code>net=</code></strong> attribute which associates a signal name with a pin which is already visible on the symbol, is probably a bad idea. This does work, but all the ramifications have not been explored yet.</div>
  </li>
  <li class="level1"><div class="li"> It is probably a bad idea to have the same <strong><code>net=</code></strong> attribute attached several times. Ales has not formalized what happens in this case. Just remember that the <strong><code>net=</code></strong> attribute on the outside of a symbol should override the internal one.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4388-5599] -->
  <h2><a name="example" id="example">Example</a></h2>
  <div class="level2">
  
  <p>
  Here&rsquo;s a schematic which uses standard symbols (note: the 7400 does not have the <strong><code>net=</code></strong> attribute inside yet). This schematic consists of a 7400 with the <strong><code>net=</code></strong> attributes attached for power and ground, One of the input pins grounded using a gnd symbol and the other at a logic one using the vcc symbol (with an attached <strong><code>net=</code></strong> attribute). One of the input net is named, but as you will see, the netname is replaced by the <strong><code>net=</code></strong> signal name (see above for more info on this). The output is pulled up with a pull up resistor which has power specified using the +5V symbol.<br/>
   
  </p>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_net.html" class="media" title="geda:net.jpg"><img src="_media/geda_net.jpg" class="media" title="net.jpg" alt="net.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  <pre class="code">v 19991011
  C 38700 58100 1 0 0 7400-1.sym
  {
  T 39000 59000 5 10 1 1 0
  uref=U100
  T 38900 59500 5 10 1 1 0
  net=GND:7
  T 38900 59300 5 10 1 1 0
  net=+5V:14
  }
  N 38700 58800 37400 58800 4
  {
  T 37600 58900 5 10 1 1 0
  netname=NETLABEL
  }
  N 37400 58800 37400 59200 4
  N 38700 58400 37400 58400 4
  N 37400 58000 37400 58400 4
  C 37300 57700 1 0 0 gnd-1.sym
  C 37200 59200 1 0 0 vcc-1.sym
  {
  T 36800 59200 5 10 1 1 0
  net=+5V:1
  }
  N 40000 58600 41600 58600 4
  {
  T 41200 58700 5 10 1 1 0
  netname=OUTPUT
  }
  C 40700 58800 1 90 0 resistor-1.sym
  {
  T 40800 59200 5 10 1 1 0
  uref=R1
  }
  N 40600 58800 40600 58600 4
  N 40600 59900 40600 59700 4
  C 40400 59900 1 0 0 5V-plus-1.sym</pre>
  
  <p>
  <strong>gnetlist</strong> (using the geda netlist format) run using this sample schematic outputs this: 
  </p>
  <pre class="code">START header
  
  gEDA's netlist format
  Created specifically for testing of gnetlist
  
  END header
  
  START components
  
  R1 device=RESISTOR
  U100 device=7400
  
  END components
  
  START renamed-nets
  
  NETLABEL -&gt; +5V
  
  END renamed-nets
  
  START nets
  
  +5V : R1 2, U100 14, U100 1
  GND : U100 7, U100 2
  OUTPUT : R1 1, U100 3
  
  END nets</pre>
  
  <p>
  Notice how NETLABEL was renamed (aliased to the +5V net).
  </p>
  
  </div>
  <!-- SECTION [5600-7377] -->
  <h2><a name="final_notes" id="final_notes">Final notes</a></h2>
  <div class="level2">
  
  <p>
  Send all bugs to <strong>ahvezdaATgeda.seul.org</strong> or <strong>geda-devATgeda.seul.org</strong> (mailing list, please subscribe first). [I&rsquo;m sure there&rsquo;s more to say here] 
  </p>
  
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  <!-- SECTION [7378-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_ngnutmeg_mp.html
  
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  <h1><a name="ngnutmeg_man-page" id="ngnutmeg_man-page">ngnutmeg man-page</a></h1>
  <div class="level1">
  <pre class="code">NUTMEG(1)							     NUTMEG(1)
  
  
  
  NAME
         nutmeg - spice post-processor
  
  SYNOPSIS
         nutmeg [ - ] [ -n ] [ -t term ] [ datafile ... ]
  
  DESCRIPTION
         Nutmeg  is  a  post  processor for SPICE - it takes the raw output file
         created by spice -r and plots the data on  a  graphics  terminal	 or  a
         workstation  display.   Note that the raw output file is different from
         the data that SPICE writes to the standard output.
  
         Arguments are:
  
         -      DonÃ¢â?¬â?¢t try to load the default data file (&quot;rawspice&quot;) if no other
  	      files are given.
  
         -n (or --no-spiceinit)
  	      DonÃ¢â?¬â?¢t try to source the file &quot;.spiceinit&quot; upon startup. Normally
  	      nutmeg tries to find the file in the current directory,  and  if
  	      it is not found then in the userÃ¢â?¬â?¢s home directory.
  
         -t term (or --term=term)
  	      The program is being run on a terminal with mfb name term.
  
         -h (or --help)
  	      Display  a  verbose  help on the arguments available to the pro-
  	      gram.
  
         -v (or --version)
  	      Display a version number and copyright information of  the  pro-
  	      gram.
  
         Further	arguments are taken to be data files in binary or ascii format
         (see sconvert(1)) which are loaded into	nutmeg.	 If  the  file	is  in
         binary format, it may be only partially completed (useful for examining
         SPICE ouput before the simulation is finished). One  file  may  contain
         any number of data sets from different analyses.
  
         Nutmeg  data is in the form of vectors: time, voltage, etc. Each vector
         has a type, and vectors can be operated on and combined algebraicly  in
         ways  consistent	 with their types. Vectors are normally created when a
         data file is read in (see the load command below), and when the initial
         datafile is loaded. They can also be created with the let command.
  
         An  expression is an algebraic formula involving vectors and scalars (a
         scalar is a vector of length 1), and the following operations:
  
  	      +, -, *, %, /, ^, and ,.
  
         % is the modulo operator, and the comma operator has two	 meanings:  if
         it  is  present	in  the argument list of a user-definable function, it
         serves to seperate the arguments. Otherwise, the term x , y is  synony-
         mous with x + j(y).
  
         Also available are the logical operations &amp; (and), | (or), ! (not), and
         the relational operations &lt;, &gt;, &gt;=, &lt;=, =, and &lt;&gt; (not equal).  If used
         in  an  algebraic  expression they work like they would in C, producing
         values of 0 or 1.  The relational operators  have  the  following  syn-
         onyms:  &quot;gt&quot;  is &gt;, &quot;lt&quot; is &lt;, &quot;ge&quot; is &gt;=, &quot;le&quot; is &lt;=, &quot;ne&quot; is &lt;&gt;, &quot;eq&quot;
         is =, &quot;and&quot; is &amp;, &quot;or&quot; is |, and &quot;not&quot; is !.  These are useful  when  &lt;
         and &gt; might be confused with IO redirection (which is almost always).
  
         The following functions are available:
  
  	      mag(vector) - The magnitude of vector.
  
  	      ph(vector) - The phase of vector.
  
  	      j(vector) - i (sqrt(-1)) times vector.
  
  	      real(vector) - The real component of vector.
  
  	      imag(vector) - The imaginary part of vector.
  
  	      db(vector) - 20 * log10(mag(vector)).
  
  	      log(vector) - The logarithm (base 10) of the vector.
  
  	      ln(vector) - The natural logarithm (base e) of vector.
  
  	      exp(vector) - e to the vector power.
  
  	      abs(vector) - The absolute value of vector.
  
  	      sqrt(vector) - The square root of vector.
  
  	      sin(vector) - The sin of vector.
  
  	      cos(vector) - The cosine of vector.
  
  	      tan(vector) - The tangent of vector.
  
  	      atan(vector) - The inverse tangent of vector.
  
  	      norm(vector) - The vector normalized to 1 (i.e, the largest mag-
  	      nitude of any component will be 1).
  
  	      rnd(vector) - A vector with  each	 component  a  random  integer
  	      between  0 and the absolute value of the vectorsÃ¢â?¬â?¢s corresponding
  	      component.
  
  	      mean(vector) - The result is a scalar (a length 1	 vector)  that
  	      is the mean of the elements of vector.
  
  	      vector(number)  -	 The result is a vector of length number, with
  	      elements 0, 1, ...  number - 1. If number is a vector then  just
  	      the  first element is taken, and if it isnÃ¢â?¬â?¢t an integer then the
  	      floor of the magnitude is used.
  
  	      length(vector) - The length of vector.
  
  	      interpolate(plot.vector) - The result of interpolating the named
  	      vector  onto  the scale of the current plot.  This function uses
  	      the variable polydegree to determine the	degree	of  interpola-
  	      tion.
  
         A  vector  may be either the name of a vector already defined, a float-
         ing- point number (a scalar), or a list	like  [elt1  elt2  ...	eltn],
         which  is  a vector of length n.	 A number may be written in any format
         acceptable to SPICE, such as 14.6MEG or -1.231E-4. Note	that  you  can
         either  use scientific notation or one of the abbreviations like MEG or
         G, but not both.	 As with SPICE, a number may have trailing  alphabetic
         characters after it.
  
         The  notation  expr  [lower  upper], where lower and upper are numbers,
         denotes the range of elements from expr between lower and  upper.   The
         notation	 expr  [num]  denotes the numÃ¢â?¬â?¢th element of expr.  If upper is
         lower than lower, the order of the elements in the vector is  reversed.
         In  all	other  cases,  [  and  ]  serve to surround literal vectors as
         described above.	 (You may have to use a lot  of	 parentheses  to  make
         sure  that you get what you want.  For instance, you have to type print
         (foo) ([1 2]) to print the two vectors.	Otherwise it  will  be	inter-
         preted  as  a  function call or a vector with an index.)	 Note that the
         expression foo[10 20][5] will not yield the 15th element	 of  foo,  but
         rather the 5th.	In general only the last index suffix on an expression
         will take effect.
  
         To reference vectors in a plot that is not the current  plot  (see  the
         setplot command, below), the notation plotname.vecname can be used.
  
         Either  a  plotname  or	a vector name may be the wildcard all.	If the
         plotname is all, matching vectors from all plots are specified, and  if
         the  vector  name is all, all vectors in the specified plots are refer-
         enced.  Note that you may not  use  binary  operations  on  expressions
         involving  wildcards  - it is not obvious what all + all should denote,
         for instance.
  
         Thus some (contrived) examples of expressions are:
  
  	      cos(TIME) + db(v(3))
  
  	      sin(cos(log([1 2 3 4 5 6 7 8 9 10])))
  
  	      TIME * rnd(v(9)) - 15 * cos(vin#branch) ^ [7.9e5 8]
  
  	      not ((ac3.FREQ[32] &amp; tran1.TIME[10]) gt 3)
  
         Nutmeg commands are as follows:
  
         plot exprs [ylimit ylo yhi] [xlimit xlo xhi] [xindices xilo xihi]
  	      [xcompress comp] [xdelta xdel] [ydelta ydel] [xlog] [ylog] [vs xname]
  		      [xlabel word] [ylabel word] [title word] [samep]
  	      Plot the given exprs on the screen (if you  are  on  a  graphics
  	      terminal).  The  xlimit  and ylimit arguments determine the high
  	      and low x- and y-limits of the axes, respectively. The  xindices
  	      arguments	 determine  what  range	 of points are to be plotted -
  	      everything between the xiloÃ¢â?¬â?¢th point and the  xihiÃ¢â?¬â?¢th  point  is
  	      plotted.	 The xcompress argument specifies that only one out of
  	      every comp points should be plotted. If an xdelta	 or  a	ydelta
  	      parameter	 is  present,  it  specifies  the spacing between grid
  	      lines on the X- and Y-axis.  These parameter names may be abbre-
  	      viated to xl, yl, xind, xcomp, xdel, and ydel respectively.  The
  	      xname argument is an expression to use as the scale  on  the  x-
  	      axis.   If  xlog	or  ylog are present, the X or Y scale respec-
  	      tively will be logarithmic.  The	xlabel	and  ylabel  arguments
  	      cause  the  specified  labels  to	 be used for the X and Y axes,
  	      respectively.  If samep is given, the values of the other param-
  	      eters  (other  than  xname) from the previous plot, hardcopy, or
  	      asciiplot command will be used unless re-defined on the  command
  	      line.   Finally, the title argument will be used in the place of
  	      the plot name at the bottom of the graph.
  
         hardcopy file plotargs
  	      Just like plot, except creates a file called file containing the
  	      plot.   The  file	 is  an	 image	in  plot(5) format, and can be
  	      printed by either the plot(1) program or lpr with the -g flag.
  
         asciiplot plotargs
  	      Produce a line printer plot of the vectors.  The plot is sent to
  	      the  standard  output,  so you can put it into a file with asci-
  	      iplot args ... &gt; file.   The  set	 options  width,  height,  and
  	      nobreak  determine the width and height of the plot, and whether
  	      there are page breaks, respectively. Note	 that  you  will  have
  	      problems	if you try to asciiplot something with an X-scale that
  	      isnÃ¢â?¬â?¢t monotonic (i.e, something like sin(TIME) ), because	 asci-
  	      iplot uses a simple-minded sort of linear interpolation.
  
         define function(arg1, arg2, ...) expression
  	      Define  the  user-definable  function with the name function and
  	      arguments arg1, arg2, ... to be expression,  which  may  involve
  	      the arguments. When the function is later used, the arguments it
  	      is given are substituted for the formal  arguments  when	it  is
  	      parsed.	If expression is not present, any definition for func-
  	      tion is printed, and if there are no arguments  to  define  then
  	      all  currently active definitions are printed. Note that you may
  	      have different functions defined with the same name but  differ-
  	      ent arities.  Some useful definitions are:
  
  	      define max(x,y) (x &gt; y) * x + (x &lt;= y) * y
  	      define min(x,y) (x &lt; y) * x + (x &gt;= y) * y
  
         undefine function ...
  	      Definitions for the named user-defined functions are deleted.
  
         let name = expr
  	      Creates  a  new  vector  called name with the value specified by
  	      expr, an expression as described above. If expr is []  (a	 zero-
  	      length  vector) then the vector becomes undefined.  If there are
  	      no arguments, let is the same as display.
  
         print [col] [line] expr ...
  	      Prints the vector described by the expression expr.  If the  col
  	      argument	is  present,  print the vectors named side by side. If
  	      line is given, the vectors are printed horizontally.  col is the
  	      default,	unless	all the vectors named have a length of one, in
  	      which case line is the default.  The options width, length,  and
  	      nobreak  are  effective for this command (see asciiplot). If the
  	      expression is all, all of the  vectors  available	 are  printed.
  	      Thus  print  col all &gt; file will print everything in the file in
  	      SPICE2 format.  The scale vector (time, frequency)  will	always
  	      be in the first column unless the variable noprintscale is true.
  
         load [filename] ...
  	      Loads the raw data in either binary or  ascii  format  from  the
  	      files  named.  The default filename is rawspice, or the argument
  	      to the -r flag if there was one.
  
         source filename
  	      Reads commands from the file filename.  Lines beginning with the
  	      character * are considered comments and ignored.
  
         help [all] [command ...]
  	      Prints  help.  If the argument all is given, a short description
  	      of everything you could possibly type is printed.	  If  commands
  	      are  given,  descriptions of those commands are printed.	Other-
  	      wise help for only a few major commands is printed.
  
         display [varname ...]
  	      Prints a summary of currently defined vectors, or of  the	 names
  	      specified.   The	vectors are sorted by name unless the variable
  	      nosort is set.  The information given is the name of the vector,
  	      the  length,  the	 type of the vector, and whether it is real or
  	      complex data. Additionally, one vector will be labeled  [scale].
  	      When a command such as plot is given without a vs argument, this
  	      scale is used for the X-axis. It is always the first vector in a
  	      rawfile, or the first vector defined in a new plot. If you unde-
  	      fine the scale (i.e, let TIME = []), a random  remaining	vector
  	      will become the scale.
  
         setplot [plotname]
  	      Set  the	current plot to the plot with the given name, or if no
  	      name is given, prompt the user with  a  menu.   (Note  that  the
  	      plots  are  named	 as  they are loaded, with names like tran1 or
  	      op2. These names are shown by the setplot and  display  commands
  	      and  are	used  by  diff,	 below.)   If  the  &quot;New plot&quot; item is
  	      selected, the current plot  will	become	one  with  no  vectors
  	      defined.	 Note  that  here the word &quot;plot&quot; refers to a group of
  	      vectors that are the result of one SPICE run.   When  more  than
  	      one  file	 is loaded in, or more than one plot is present in one
  	      file, nutmeg keeps them seperate and only shows you the  vectors
  	      in the current plot.
  
         settype type vector ...
  	      Change the type of the named vectors to type.  Type names can be
  	      found in the manual page for sconvert.
  
         diff plot1 plot2 [vec ...]
  	      Compare all the vectors in the  specified	 plots,	 or  only  the
  	      named  vectors  if any are given. There are different vectors in
  	      the two plots, or any values in the vectors differ significantly
  	      the  difference  is  reported. The variables abstol, reltol, and
  	      vntol are used to determine what &quot;significantly&quot; means (see  the
  	      SPICE3 UserÃ¢â?¬â?¢s Manual).
  
         quit   Quit nutmeg.
  
         bug    Send  a  bug report. (If you have defined BUGADDR, the mail will
  	      go there.)
  
         write [file] [exprs]
  	      Writes out the  exprÃ¢â?¬â?¢s  to  file.	  First	 vectors  are  grouped
  	      together	by  plots,  and	 written  out  as  such.  (I.e, if the
  	      expression list contained three vectors from one	plot  and  two
  	      from  another,  then  two	 plots will be written, one with three
  	      vectors and one with two.)  Additionally, if  the	 scale	for  a
  	      vector  isnÃ¢â?¬â?¢t  present, it is automatically written out as well.
  	      The default format is ascii, but this can be  changed  with  the
  	      set  filetype command.  The default filename is rawspice, or the
  	      argument to the -r flag on the command line, if there  was  one,
  	      and the default expression list is all.
  
         shell [args ...]
  	      Fork  a  shell,  or  execute  the	 arguments as a command to the
  	      shell.
  
         alias [word] [text ...]
  	      Causes word to be aliased to text.  History substitutions may be
  	      used, as in C-shell aliases.
  
         unalias [word ...]
  	      Removes any aliases present for the words.
  
         history [number]
  	      Print  out the history, or the last number commands typed at the
  	      keyboard.	 Note: in   version  3a7  and  earlier,	 all  commands
  	      (including ones read from files) were saved.
  
         set [word] [word = value] ...
  	      Set  the	value  of word to be value, if it is present.  You can
  	      set any word to be any value, numeric or string.	If no value is
  	      given  then the value is the boolean Ã¢â?¬â?¢trueÃ¢â?¬â?¢.   The value of word
  	      may be inserted into a command by writing $word.	If a  variable
  	      is  set  to  a  list  of values that are enclosed in parentheses
  	      (which must be seperated from their values by white space),  the
  	      value  of the variable is the list.  The variables meaningful to
  	      nutmeg (of which there are too many) are:
  
  		       abstol
  		       The absolute tolerance used by the diff command.
  
  		       appendwrite
  		       Append to the file when a write command is  issued,  if
  		       one already exists.
  
  		       colorN
  		       These  variables	 determine  the	 colors	 used, if X is
  		       being run on a color display.  N may be between	0  and
  		       15.  Color 0 is the background, color 1 is the grid and
  		       text color, and colors 2 through 15 are used  in	 order
  		       for  vectors plotted.  The value of the color variables
  		       should be names of colors, which may be	found  in  the
  		       file /usr/lib/rgb.txt.
  
  		       combplot
  		       Plot vectors by drawing a vertical line from each point
  		       to the X-axis, as opposed to joining the points.	  Note
  		       that  this  option  is subsumed in the plottype option,
  		       below.
  
  		       cpdebug
  		       Print cshpar debugging information. (Must  be  complied
  		       with the -DCPDEBUG flag.)
  
  		       debug
  		       If  set then a lot of debugging information is printed.
  		       (Must be compiled with the -DFTEDEBUG flag.)
  
  		       device
  		       The name (/dev/tty??) of the graphics device.  If  this
  		       variable isnÃ¢â?¬â?¢t set then the userÃ¢â?¬â?¢s terminal is used. To
  		       do plotting on another monitor you will	probably  have
  		       to  set both the device and term variables.  (If device
  		       is set to the name of a	file,  nutmeg  will  dump  the
  		       graphics control codes into this file -- this is useful
  		       for saving plots.)
  
  		       echo
  		       Print out each command before it is executed.
  
  		       filetype
  		       This can be either ascii or binary, and determines what
  		       the format of rawfiles will be. The default is ascii.
  
  		       fourgridsize
  		       How  many  points  to  use  for interpolating into when
  		       doing fourier analysis.
  
  		       gridsize
  		       If this variable is set to an integer, this number will
  		       be  used	 as the number of equally spaced points to use
  		       for the Y-axis when plotting.   Otherwise  the  current
  		       scale  will  be used (which may not have equally spaced
  		       points).	 If the current	 scale	isnÃ¢â?¬â?¢t  strictly	 mono-
  		       tonic, then this option will have no effect.
  
  		       hcopydev
  		       If  this	 is  set, when the hardcopy command is run the
  		       resulting file is automatically printed on the  printer
  		       named hcopydev with the command lpr -Phcopydev -g file.
  
  		       hcopydevtype
  		       This variable specifies the type of the printer	output
  		       to use in the hardcopy command.	If hcopydevtype is not
  		       set, plot (5) format is assumed.	 The standard  distri-
  		       bution  currently  recognizes postscript as an alterna-
  		       tive output format.   When  used	 in  conjunction  with
  		       hcopydev,  hcopydevtype	should	specify	 a format sup-
  		       ported by the printer.
  
  		       height
  		       The length of the page for asciiplot and print col.
  
  		       history
  		       The number of events to save in the history list.
  
  		       nfreqs
  		       The number of frequencies to  compute  in  the  fourier
  		       command. (Defaults to 10.)
  
  		       nobreak
  		       DonÃ¢â?¬â?¢t have asciiplot and print col break between pages.
  
  		       noasciiplotvalue
  		       DonÃ¢â?¬â?¢t print the first vector plotted to the  left  when
  		       doing an asciiplot.
  
  		       noclobber
  		       DonÃ¢â?¬â?¢t  overwrite	 existing files when doing IO redirec-
  		       tion.
  
  		       noglob
  		       DonÃ¢â?¬â?¢t expand the global characters Ã¢â?¬Ë?*Ã¢â?¬â?¢, Ã¢â?¬Ë??Ã¢â?¬â?¢,  Ã¢â?¬Ë?[Ã¢â?¬â?¢,  and
  		       Ã¢â?¬Ë?]Ã¢â?¬â?¢. This is the default.
  
  		       nogrid
  		       DonÃ¢â?¬â?¢t  plot  a  grid when graphing curves (but do label
  		       the axes).
  
  		       nomoremode
  		       If nomoremode is not set, whenever a  large  amount  of
  		       data  is being printed to the screen (e.g, the print or
  		       asciiplot commands), the output will be	stopped	 every
  		       screenful  and  will continue when a carriage return is
  		       typed. If nomoremode is set then data will  scroll  off
  		       the screen without hesitation.
  
  		       nonomatch
  		       If  noglob  is  unset and a global expression cannot be
  		       matched, use the global characters literally instead of
  		       complaining.
  
  		       nosort
  		       DonÃ¢â?¬â?¢t have display sort the variable names.
  
  		       noprintscale
  		       DonÃ¢â?¬â?¢t  print  the  scale	 in the leftmost column when a
  		       print col command is given.
  
  		       numdgt
  		       The number of digits to print when printing  tables  of
  		       data  (fourier, print col).  The default precision is 6
  		       digits.	On the VAX, approximately  16  decimal	digits
  		       are  available using double precision, so numdgt should
  		       not be more than 16.  If the number  is	negative,  one
  		       fewer  digit  is	 printed  to ensure constant widths in
  		       tables.
  
  		       plottype
  		       This should be one of  normal,  comb,  or  point:chars.
  		       normal,	the   default,	causes points to be plotted as
  		       parts of connected lines.  comb causes a comb  plot  to
  		       be  done	 (see the description of the combplot variable
  		       above).	point causes each point to be  plotted	seper-
  		       ately - the chars are a list of characters that will be
  		       used for each vector plotted.  If they are omitted then
  		       a default set is used.
  
  		       polydegree
  		       The  degree  of	the  polynomial	 that the plot command
  		       should fit to the data. If polydegree is N, then nutmeg
  		       will fit a degree N polynomial to every set of N points
  		       and draw 10 intermediate points in  between  each  end-
  		       point. If the points arenÃ¢â?¬â?¢t monotonic, then it will try
  		       rotating the curve and reducing the degree until a  fit
  		       is achieved.
  
  		       polysteps
  		       The  number of points to interpolate between every pair
  		       of points  available  when  doing  curve	 fitting.  The
  		       default	is  10.	 (This should really be done automati-
  		       cally.)
  
  		       program
  		       The name of the current program (argv[0]).
  
  		       prompt
  		       The prompt, with the character Ã¢â?¬Ë?!Ã¢â?¬â?¢ replaced by the cur-
  		       rent event number.
  
  		       rawfile
  		       The default name for rawfiles created.
  
  		       reltol
  		       The relative tolerance used by the diff command.
  
  		       rhost
  		       The  machine to use for remote SPICE-3 runs, instead of
  		       the default one. (See the  description  of  the	rspice
  		       command, below.)
  
  		       rprogram
  		       The  name  of  the  remote program to use in the rspice
  		       command.
  
  		       slowplot
  		       Stop between each graph plotted and wait for  the  user
  		       to type return before continuing.
  
  		       sourcepath
  		       A  list of the directories to search when a source com-
  		       mand is given.  The default is  the  current  directory
  		       and  the	 standard spice library (/usr/local/lib/spice,
  		       or whatever LIBPATH is #defined to in the  source.
  
  		       spicepath
  		       The program to use for the aspice command. The  default
  		       is /cad/bin/spice.
  
  		       term
  		       The mfb name of the current terminal.
  
  		       units
  		       If  this	 is  degrees, then all the trig functions will
  		       use degrees instead of radians.
  
  		       unixcom
  		       If a command isnÃ¢â?¬â?¢t defined, try to execute it as a UNIX
  		       command.	  Setting this option has the effect of giving
  		       a rehash command, below.	 This is useful for people who
  		       want to use nutmeg as a login shell.
  
  		       verbose
  		       Be  verbose.  This  is  midway between echo and debug /
  		       cpdebug.
  
  		       vntol
  		       The absolute voltage tolerance used by  the  diff  com-
  		       mand.
  
  		       width
  		       The width of the page for asciiplot and print col.
  
  		       xbrushheight
  		       The height of the brush to use if X is being run.
  
  		       xbrushwidth
  		       The width of the brush to use if X is being run.
  
  		       xfont
  		       The  name  of  the X font to use when plotting data and
  		       entering labels.	 The plot may not look entirely	 great
  		       if this is a variable-width font.
  
  
         unset [word] ...
  	      Unset the variables word.
  
         shift [varname] [number]
  	      If  varname is the name of a list variable, it is shifted to the
  	      left by number elements. (I.e, the number leftmost elements  are
  	      removed.)	  The  default varname is argv, and the default number
  	      is 1.
  
         rusage [resource ...]
  	      Print resource usage statistics.	If any	resources  are	given,
  	      just   print  the	 usage	of  that  resource.   Currently	 valid
  	      resources are:
  
  		       elapsed
  		       The amount of time elapsed since the last rusage elaped
  		       call.
  
  		       faults
  		       Number  of page faults and context switches (BSD only).
  
  		       space
  		       Data space used.
  
  		       time
  		       CPU time used so far.
  
  		       everything
  		       All of the above.
  
         cd [directory]  Change the current working directory to	directory,  or
  		       to the userÃ¢â?¬â?¢s home directory if none is given.
  
         aspice [output-file]
  		       Start  a	 SPICE-3 run, and when it is finished load the
  		       data. The raw data is kept in a temporary file. If out-
  		       put-file	 is  specified	then  the diagnostic output is
  		       directed into that file, otherwise it is thrown away.
  
         jobs	       Report on the asynchronous SPICE-3 jobs currently  run-
  		       ning.   Nutmeg  checks  to see if the jobs are finished
  		       every time you execute a command.  If it is  done  then
  		       the data is loaded and becomes available.
  
         rspice [input file]
  		       Runs  a	SPICE-3	 remotely  taking  the input file as a
  		       SPICE-3 input deck, or the current circuit if no	 argu-
  		       ment  is	 given.	 Nutmeg waits for the job to complete,
  		       and passes output from the remote  job  to  the	userÃ¢â?¬â?¢s
  		       standard	 output.  When the job is finished the data is
  		       loaded in as with aspice. If the variable rhost is set,
  		       nutmeg will connect to this host instead of the default
  		       remote SPICE-3 server machine. Note that	 this  command
  		       will  only work if your system administrator is running
  		       a SPICE-3 daemon on the remote host.  If	 the  variable
  		       rprogram is set, then rspice will use this as the path-
  		       name to the program to run.
  
         echo [stuff...] Echos the arguments.
  
         fourier fundamental_frequency [value ...]
  		       Does a fourier analysis of each of  the	given  values,
  		       using  the  first  10 multiples of the fundamental fre-
  		       quency (or the first nfreqs, if that variable is set  -
  		       see below). The output is like that of the .four	 card.
  		       The values may be any valid expression.	The values are
  		       interpolated onto a fixed-space grid with the number of
  		       points given by the fourgridsize variable, or 200 if it
  		       is  not set.  The interpolation will be of degree poly-
  		       degree if that variable is set, or 1.  If polydegree is
  		       0,  then no interpolation will be done.	This is likely
  		       to give erroneous results if  the  time	scale  is  not
  		       monotonic, though.
  
         version [version id]
  		       Print  out  the	version of nutmeg that is running.  If
  		       there are arguments, it checks to make  sure  that  the
  		       arguments  match the current version of SPICE. (This is
  		       mainly used as a Command: line in rawfiles.)
  
         rehash	       Recalculate the internal hash tables used when  looking
  		       up  UNIX	 commands,  and	 make all UNIX commands in the
  		       userÃ¢â?¬â?¢s PATH available for command completion.  This  is
  		       useless	unless you have set unixcom first (see above).
  
         The following control structures are available:
  
  	      while condition
  		   statement
  		   ...
  	      end
  
         While condition, an arbitrary algebraic expression,  is	true,  execute
         the statements.
  
  	      repeat [number]
  		   statement
  		   ...
  	      end
  
         Execute	the  statements	 number	 times,	 or  forever if no argument is
         given.
  
  	      dowhile condition
  		   statement
  		   ...
  	      end
  
         The same as while, except  that	the  condition	is  tested  after  the
         statements are executed.
  
  	      foreach var value ...
  		   statement
  		   ...
  	      end
  
         The statements are executed once for each of the values, each time with
         the variable var set to the current one.	 (var can be accessed  by  the
         $var notation - see below).
  
  	      if condition
  		   statement
  		   ...
  	      else
  		   statement
  		   ...
  	      end
  
         If  the condition is non-zero then the first set of statements are exe-
         cuted, otherwise the second set.	 The else and the second set of state-
         ments may be omitted.
  
  	      label word
  
         If  a statement of the form goto word is encountered, control is trans-
         fered to this point, otherwise this is a no-op.
  
  	      goto word
  
         If a statement of the form label word is present in  the	 block	or  an
         enclosing  block,  control is transfered there.	Note that if the label
         is at the top level, it must be before the goto statement (i.e, a  for-
         ward goto may occur only within a block).
  
  	      continue
  
         If  there  is  a while, dowhile, or foreach block enclosing this state-
         ment, control passes to the test, or in the case of foreach,  the  next
         value is taken.	Otherwise an error results.
  
  	      break
  
         If  there  is  a while, dowhile, or foreach block enclosing this state-
         ment, control passes out of the block. Otherwise an error results.
  
         Of course, control structures may be nested.  When a block  is  entered
         and  the	 input	is  the	 terminal,  the prompt becomes a number of &gt;Ã¢â?¬â?¢s
         equalling the number of blocks the user has entered. The	 current  con-
         trol structures may be examined with the debugging command cdump.
  
         If  a word is typed as a command, and there is no built-in command with
         that name, the directories in the sourcepath list are searched in order
         for  the	 file.	If it is found, it is read in as a command file (as if
         it were sourced).  Before it is read, however, the variables  argc  and
         argv  are set to the number of words following the filename on the com-
         mand line, and a list of those words respectively.  After the  file  is
         finished, these variables are unset.  Note that if a command file calls
         another, it must save its argv and argc since they  will	 get  altered.
         Also,  command  files  may  not	be re-entrant since there are no local
         variables.  (Of course, the  procedures	may  explicitly	 manipulate  a
         stack...)   This	 way  one can write scripts analogous to shell scripts
         for nutmeg and .	 Note that for the script to work with , it must begin
         with  a blank line (or whatever you like, since it will be thrown away)
         and then a line with .control on it.  This is an unfortunate result  of
         the  source  command being used for both circuit input and command file
         execution.  Note also that this allows the user to merely type the name
         of a circuit file as a command, and it will be automatically run.
  
         There	  are	  various     command	  scripts     installed	    in
         /usr/local/lib/spice/scripts (or whatever the path is on your machine),
         and  the	 default  sourcepath  includes	this directory, so you can use
         these command files (almost) like builtin commands.
  
         Nutmeg will use either X or MFB, depending  on  whether	it  finds  the
         variable	 DISPLAY in the environment.  If you are using X on a worksta-
         tion, it should already be present, but if you want to display graphics
         on  a different machine than the one you are running nutmeg on, DISPLAY
         should be of the form machine:0.
  
         If X is being used, the cursor may be positioned at any	point  on  the
         screen  when the window is up and characters typed at the keyboard will
         be added to the window at that point.  The window may then be sent to a
         printer using the xpr(1) program.
  
         There are a number of pre-defined constants in nutmeg. They are:
  	    pi	      pi
  	    e	      The base of natural logarithms
  	    c	      The speed of light
  	    i	      The square root of -1
  	    kelvin	   Absolute 0 in Centigrade
  	    echarge	   The charge on an electron
  	    boltz	   BoltzmanÃ¢â?¬â?¢s constant
  	    planck	   PlanckÃ¢â?¬â?¢s constant (h)
  
  
         These  are  all	in MKS units. If you have another variable with a name
         that conflicts with one of these then it takes precedence.
  
         Nutmeg occasionally checks to see if it is getting close to running out
         of  space, and warns the user if this is the case. (This is more likely
         to be useful with the SPICE front end.)
  
         C-shell type quoting with &quot;&quot; and Ã¢â?¬â?¢Ã¢â?¬â?¢, and backquote substitution may  be
         used.  Within single quotes, no further substitution (like history sub-
         stitution) is done, and	within	double	quotes,	 the  words  are  kept
         together	 but further substitution is done. Any text between backquotes
         is replaced by the result of executing the text as  a  command  to  the
         shell.
  
         Tenex-style  (Ã¢â?¬â?¢set  filecÃ¢â?¬â?¢  in  the 4.3 C-shell) command, filename, and
         keyword completion is possible: If EOF (control-D) is typed  after  the
         first  character	 on the line, a list of the commands or possible argu-
         ments is printed. (If it is alone on the line it will exit nutmeg.)  If
         escape  is  typed,  then	 nutmeg will try to complete what the user has
         already typed.  To get a list of all commands,  the  user  should  type
         &lt;space&gt; ^D.
  
         The  values  of	variables  may be used in commands by writing $varname
         where the value of the variable is to appear.  The special variables $$
         and $&lt; refer to the process ID of the program and a line of input which
         is read from the terminal when the variable is evaluated, respectively.
         If  a variable has a name of the form $&amp;word, then word is considered a
         vector (see above), and its value is taken to be the value of the vari-
         able.   If  $foo	 is  a	valid  variable, and is of type list, then the
         expression $foo[low-high] represents a range of elements.   Either  the
         upper index or the lower may be left out, and the reverse of a list may
         be obtained with $foo[len-0].  Also, the notation $?foo evaluates to  1
         if the variable foo is defined, 0 otherwise, and $#foo evaluates to the
         number of elements in foo if it is a list, 1  if	 it  is	 a  number  or
         string, and 0 if it is a boolean variable.
  
         History	substitutions,	similar	 to C-shell history substitutions, are
         also available - see the C-shell manual page for all of the details.
  
         The characters ~, {, and } have the same effects as they do in  the  C-
         Shell,  i.e.,  home directory and alternative expansion. It is possible
         to use the wildcard characters *, ?, [, and ] also,  but	 only  if  you
         unset noglob first. This makes them rather useless for typing algebraic
         expressions, so you should set noglob again after  you  are  done  with
         wildcard expansion. Note that the pattern [^abc] will match all charac-
         ters except a, b, and c.
  
         IO redirection is available - the symbols &gt;, &gt;&gt;, &gt;&amp;, &gt;&gt;&amp;,  and  &lt;  have
         the same effects as in the C-shell.
  
         You may type multiple commands on one line, seperated by semicolons.
  
         If  you	want  to use a different mfbcap file than the default (usually
         ~cad/lib/mfbcap), you have  to  set  the	 environment  variable	MFBCAP
         before  you  start  nutmeg.   The  -m option and the mfbcap variable no
         longer work.
  
  VMS NOTES
         Nutmeg can be run under VAX/VMS. Some features like command,  etc  com-
         pletion,	 expansion  of *, ?, and [], backquote substitution, the shell
         command, and so forth do not work. (In  fact  command  completion  only
         works on 4.2 or 4.3 BSD.)
  
         Nutmeg will look for start-up commands in the file spice.rc in the cur-
         rent directory.
  
         The standard suffix for rawspice files in VMS is &quot;.raw&quot;.
  
         You will have to respond to the -more- prompt during plot with  a  car-
         riage return instead of any key as you can do on UNIX.
  
  SEE ALSO
         sconvert(1), spice(1), mfb(3), writedata(3)
  
  AUTHOR
         Wayne Christopher (faustus@xxxxxxxxxxxxxxxx)
  
  BUGS
         The label entry facilities are very primitive - after all, nutmeg isnÃ¢â?¬â?¢t
         a graphics editor (yet).	 You must be careful to type very slowly  when
         entering	 labels	 -- nutmeg checks the X event queue once every second,
         and can get very confused if characters arrive faster than that.
  
         If you redefine colors after creating a plot window with	 X,  and  then
         cause the window to be redrawn, it will not to the right thing.
  
         When defining aliases like
  
  	      alias pdb plot db( Ã¢â?¬â?¢!:1Ã¢â?¬â?¢ - Ã¢â?¬â?¢!:2Ã¢â?¬â?¢ )
  
         you  must  be  careful to quote the argument list substitutions in this
         manner. If you quote the whole argument it might not work properly.
  
         In a user-defined function, the arguments cannot be part of a name that
         uses the plot.vec syntax.  I.e,
  
  	      define poke(duck) cos(tran1.duck)
  
         wonÃ¢â?¬â?¢t do the right thing.
  
         If you type plot all all, or otherwise use a wildcard reference for one
         plot twice in a command, bad things will happen.
  
         The asciiplot command doesnÃ¢â?¬â?¢t deal with log scales or  the  delta  key-
         words.
  
         There are probably some features that nutmeg doesnÃ¢â?¬â?¢t have yet.
  
  CAVEATS
         Often the names of terminals recognised by MFB are different from those
         in /etc/termcap. Thus you may have to reset your terminal type with the
         command
  
  	      set term = termname
  
         where termname is the name in the mfbcap file.
  
         The  hardcopy  command  is useless on VMS and other systems without the
         plot command, unless the user has a program  that  understands  plot(5)
         format.
  
  
  
  
  4th Berkeley Distribution	 27 April 1987			     NUTMEG(1)
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  <h1><a name="ngsconvert_man-page" id="ngsconvert_man-page">ngsconvert man-page</a></h1>
  <div class="level1">
  <pre class="code">SCONVERT(1)							   SCONVERT(1)
  
  
  
  NAME
         sconvert - convert spice formats
  
  SYNOPSIS
         sconvert fromtype fromfile totype tofile
         sconvert fromtype totype
         sconvert
  
  DESCRIPTION
         Sconvert	 translates  spice  output  files among three formats: the old
         binary format, a new binary format, and a new ascii format.   The  for-
         mats  are  specified  by the fromtype and totype arguments: Ã¢â?¬Ë?oÃ¢â?¬â?¢ for the
         old format, Ã¢â?¬Ë?bÃ¢â?¬â?¢ for the new binary format, and Ã¢â?¬Ë?aÃ¢â?¬â?¢ for  the  new	 ascii
         format.	Fromtype specifies the format to be read, and totype specifies
         the format to be written.  If fromfile and tofile are given, then  they
         are  used  as the input and output, otherwise standard input and output
         are used.  (Note that this second option is only available on UNIX sys-
         tems  - on VMS and other systems you must supply the filenames.)	 If no
         arguments are given, the parameters are prompted for.
  
         Binary format is the preferred format for general use,  as  it  is  the
         most  economical	 in  terms  of space and speed of access, and ascii is
         provided to make it easy to modify data files and transfer them between
         machines with different floating-point formats.	The old format is pro-
         vided only for backward compatibility. The three formats	 are  as  fol-
         lows:
  
         Old:
  
  		What	      Size in Bytes
  
  	    title		     80
  	    date		8
  	    time		8
  	    numoutputs		     2
  	    the integer 4	     2
  	    variable names --
  		 char[numoutputs][8] numoutputs * 8
  	    types of output		  numoutputs * 2
  	    node index		     numoutputs * 2
  	    plot title		     numoutputs * 24
  	    the actual data		  numpoints * numoutputs * 8
  
         Ascii:
  
  	    Title: Title Card String
  	    Date: Date
  	    [ Plotname: Plot Name
  	      Flags: complex or real
  	      No. Variables: numoutputs
  	      No. Points: numpoints
  	      Command: nutmeg command
  	      Variables:   0 varname1 typename1
  		      1 varname2 typename2
  		      etc...
  	      Values:
  		0     n	   n	n    n	  ...
  		1     n	   n	n    n	  ...
  		And so forth...
  	    ] repeated one or more times
  
  
         If one of the flags is complex, the points look like r,i where r and i
         are floating point (in %e format). Otherwise they are in %e format.
         Only one of real and complex should appear.
  
         The lines are guaranteed to be less than 80 columns wide (unless the
         plot title or variable names are very long), so this format is safe
         to mail between systems like CMS.
  
         Any number of Command: lines may appear between the No. Points:
         and the Variables: lines, and whenever the plot is loaded into
         nutmeg they will be executed.
  
         Binary:
  
  	    Title Card		  (a NULL terminated string)
  	    Date, Time		  (a NULL terminated string)
  	    [
  	      Plot title	  (a NULL terminated string)
  	      Number of variables   (an int)
  	      Number of data points (an int)
  	      flags	     (a short)
  	      variable header struct (repeated numoutputs times)
  		 variable name	  (a NULL terminated string)
  		 variable type	  (an int)
  	      set of outputs	  (repeated numpoints times)
  	    ] repeated one or more times.
  
  
         A set of outputs is a vector of doubles of length numoutputs, or
         a vector of real-imaginary pairs of doubles if the data is complex.
  
  SEE ALSO
         nutmeg(1), spice(1), writedata(3)
  
  AUTHOR
         Wayne Christopher (faustus@xxxxxxxxxxxxxxxx)
  
  BUGS
         If  variable  names  and	 the  title and plotname strings have trailing
         blanks in them they will be stripped off when the file is read,	if  it
         is in ascii format.
  
         If  a plot title begins with &quot;Title:&quot; nutmeg will be fooled into think-
         ing that this is an ascii format file.  Sconvert	 always	 requires  the
         type to be specified, however.
  
  
  
  
  4th Berkeley Distribution	 20 March 1986			   SCONVERT(1)
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  <h1><a name="ngspice_man-page" id="ngspice_man-page">ngspice man-page</a></h1>
  <div class="level1">
  <pre class="code">SPICE(1)							      SPICE(1)
  
  
  
  NAME
         spice - circuit simulator
  
  SYNOPSIS
         spice [ -n ] [ -t term ] [ -r rawfile] [ -b ] [ -i ] [ input file ... ]
  
  DESCRIPTION
         This manual page describes the commands available for  interactive  use
         of SPICE3. For details of circuit descriptions and the process of simu-
         lating a circuit, see the SPICE3 UserÃ¢â?¬â?¢s Manual.	The commands available
         are a superset of those available for nutmeg - only the additional com-
         mands available in SPICE3 are described here.  You should  be  familiar
         with the manual page for nutmeg(1) before reading this manual page.
  
         Arguments are:
  
         -n (or --no-spiceinit)
  	      DonÃ¢â?¬â?¢t try to source the file &quot;.spiceinit&quot; upon startup. Normally
  	      SPICE3 tries to find the file in the current directory,  and  if
  	      it is not found then in the userÃ¢â?¬â?¢s home directory.
  
         -q (or --completion)
  	      Enable command completion.
  
         -t term (or --term=term)
  	      The program is being run on a terminal with mfb name term.
  
         -b (or --batch)
  	      Run  in  batch  mode. SPICE3 will read the standard input or the
  	      specified input file and do the simulation.  Note	 that  if  the
  	      standard	input  is not a terminal, SPICE3 will default to batch
  	      mode, unless the -i flag is given.
  
         -s (or --server)
  	      Run in server mode. This is like batch mode, except that a  tem-
  	      porary  rawfile is used and then written to the standard output,
  	      preceded by a line with a single &quot;@&quot;, after  the	simulation  is
  	      done. This mode is used by the spice daemon.
  
         -i (or --interactive)
  	      Run in interactive mode. This is useful if the standard input is
  	      not a terminal but interactive mode is desired. Command  comple-
  	      tion  is	not available unless the standard input is a terminal,
  	      however.
  
         -r rawfile (or --rawfile=file)
  	      Use rawfile as the default file into which the  results  of  the
  	      simulation are saved.
  
         -c circuitfile (or --circuitfile=circuitfile)
  	      Use circuitfile as the default input deck.
  
         -h (or --help)
  	      Display  a  verbose  help on the arguments available to the pro-
  	      gram.
  
         -v (or --version)
  	      Display a version number and copyright information of  the  pro-
  	      gram.
  
         Further	arguments  are	taken to be SPICE3 input decks, which are read
         and saved. (If batch mode is requested then they are run	 immediately.)
  
         SPICE3  will  accept  any  SPICE2  input decks, and output ascii plots,
         fourier analyses, and node printouts as specified in .plot, .four,  and
         .print cards.  If a out parameter is given on a .width card, the effect
         is the same as set width = ....	Since SPICE3 ascii plots  do  not  use
         multiple ranges, however, if vectors together on a .plot card have dif-
         ferent ranges they will not provide as much information as  they	 would
         in  SPICE2. The output of SPICE3 is also much less verbose than SPICE2,
         in that the only data printed is that requested by the above cards.
  
         Vector names are the same as in nutmeg, with this addition: a name such
         as  @name[param], where name is either the name of a device instance or
         model, denotes the value of the param parameter of the device or model.
         See  the SPICE3 UserÃ¢â?¬â?¢s Manual for details of what parameters are avail-
         able. The value is a vector of length 1.	 This function is also	avail-
         able  with the show command, and is available with variables for conve-
         nience for command scripts.
  
         SPICE3 commands are as follows (these are only those commands not  also
         available  in  nutmeg  -	 consult  the nutmeg manual page for more com-
         mands):
  
         setcirc [circuit name]
  	      Change the current circuit. The current circuit is the one  that
  	      is  used	for  the  simulation commands below. When a circuit is
  	      loaded with the source command (see below) it becomes  the  cur-
  	      rent circuit.
  
         op [.op card args]
  	      Do an operating point analysis.
  
         tran [.tran card args]
  	      Do a transient analysis.
  
         ac [.ac card args]
  	      Do an ac analysis.
  
         dc [.dc card args]
  	      Do a dc transfer curve analysis.
  
         listing [logical] [physical] [deck] [expand]
  	      Print  a listing of the current circuit. If the logical argument
  	      is given, the listing is with all continuation  lines  collapsed
  	      into  one	 line, and if the physical argument is given the lines
  	      are printed out as they were found in the file. The  default  is
  	      logical.	A  deck	 listing  is  just  like the physical listing,
  	      except without the line numbers it recreates the input file ver-
  	      batim  (except  that  it	does  not preserve case).  If the word
  	      expand is present, the circuit will be printed with all  subcir-
  	      cuits expanded.
  
         edit [file]
  	      Print the current SPICE3 deck into a file, call up the editor on
  	      that file and allow the user to modify it, and then read it back
  	      in,  replacing  the  origonal deck. If a filename is given, then
  	      edit that file and load it, making the circuit the current  one.
  
         resume Resume a simulation after a stop.
  
         show   Show a device parameter.
  
         alter  Alter a device parameter.
  
         state  Print  the state of the circuit.	(This command is largely unim-
  	      plemented.)
  
         save [all] [output ...]	or .save [all] [output ...]
  	      Save a set of outputs, discarding the rest. If a node  has  been
  	      mentioned	 in a save command, it will appear in the working plot
  	      after a run has completed, or in the rawfile if spice is run  in
  	      batch  mode.  If a node is traced or plotted (see below) it will
  	      also be saved. For backward compatibility, if there are no  save
  	      commands given, all outputs are saved.
  
         stop [ after n] [ when something cond something ] ...
  	      Set a breakpoint. The argument after n means stop after n itera-
  	      tion number n, and the argument when  something  cond  something
  	      means  stop  when	 the  first something is in the given relation
  	      with the second something, the possible relations being eq or  =
  	      (equal  to), ne or &lt;&gt; (not equal to), gt or &gt; (greater than), lt
  	      or &lt; (less than), ge or &gt;= (greater than or equal to), and le or
  	      &lt;=  (less than or equal to).  IO redirection is disabled for the
  	      stop command, since the relational operations conflict  with  it
  	      (it  doesnÃ¢â?¬â?¢t  produce  any output anyway).  The somethings above
  	      may be node names in the running circuit, or  real  values.   If
  	      more than one condition is given, e.g.  stop after 4 when v(1) &gt;
  	      4 when v(2) &lt; 2, the conjunction of the conditions is implied.
  
         trace [ node ...]
  	      Trace nodes. Every iteration the value of the node is printed to
  	      the standard output.
  
         iplot [ node ...]
  	      Incrementally plot the values of the nodes while SPICE3 runs.
  
         step [number]
  	      Iterate number times, or once, and then stop.
  
         status Display all of the traces and breakpoints currently in effect.
  
         delete [debug number ...]
  	      Delete  the  specified breakpoints and traces. The debug numbers
  	      are those shown by the status command. (Unless you do  status  &gt;
  	      file, in which case the debug numbers arenÃ¢â?¬â?¢t printed.)
  
         reset  Throw  out  any  intermediate  data in the circuit (e.g, after a
  	      breakpoint  or  after  one  or  more  analyses  have  been  done
  	      already), and re-parse the deck. The circuit can then be re-run.
  	      (Note: this command used to be end in SPICE 3a5 and earlier ver-
  	      sions  -- end is now used for control structures.)  The run com-
  	      mand will take care  of  this  automatically,  so	 this  command
  	      should not be necessary...
  
         run [rawfile]
  	      Run the simulation as specified in the input file. If there were
  	      any of the control cards .ac, .op, .tran, or .dc, they are  exe-
  	      cuted. The output is put in rawfile if it was given, in addition
  	      to being available interactively.
  
         source file
  	      Read the SPICE3 input file file. Nutmeg and SPICE3 commands  may
  	      be  included in the file, and must be enclosed between the lines
  	      .control and .endc.  These  commands  are	 executed  immediately
  	      after  the  circuit  is loaded, so a control line of ac ... will
  	      work the same as the corresponding .ac card.  The first line  in
  	      any  input  file	is  considered a title line and not parsed but
  	      kept as the name of the circuit. The exception to this  rule  is
  	      the  file	 .spiceinit.  Thus, a SPICE3 command script must begin
  	      with a blank line and then with a .control line.	Also, any line
  	      beginning	 with  the characters *# is considered a control line.
  	      This makes it possible to imbed commands in SPICE3  input	 files
  	      that  will  be  ignored  by earlier versions of SPICE.  Note: in
  	      spice3a7 and before, the	.control  and  .endc  lines  were  not
  	      needed, and any line beginning with the name of a front-end com-
  	      mand would be executed.
  
         linearize vec ...
  	      Create a new plot with all of the vectors in the	current	 plot,
  	      or only those mentioned if arguments are given.  The new vectors
  	      will be interpolated onto a linear time scale, which  is	deter-
  	      mined by the values of tstep, tstart, and tstop in the currently
  	      active transient	analysis.   The	 currently  loaded  deck  must
  	      include a transient analysis (a tran command may be run interac-
  	      tively before the last reset, alternately), and the current plot
  	      must  be	from  this transient analysis.	This command is needed
  	      because SPICE3 doesnÃ¢â?¬â?¢t output the results from a transient anal-
  	      ysis in the same manner that SPICE2 did.
  
         There  are  several set variables that SPICE3 uses but nutmeg does not.
         They are:
  
  		       editor
  		       The editor to use for the edit command.
  
  		       modelcard
  		       The name of the model card (normally .model).
  
  		       noaskquit
  		       Do not check to make sure that there  are  no  circuits
  		       suspended  and  no plots unsaved.  Normally SPICE3 will
  		       warn the user when he tries to  quit  if	 this  is  the
  		       case.
  
  		       nobjthack
  		       Assume that BJTÃ¢â?¬â?¢s have 4 nodes.
  
  		       noparse
  		       DonÃ¢â?¬â?¢t  attempt  to  parse  decks	 when they are read in
  		       (useful for debugging). Of course, they cannot  be  run
  		       if they are not parsed.
  
  		       nosubckt
  		       DonÃ¢â?¬â?¢t expand subcircuits.
  
  		       renumber
  		       Renumber input lines when a deck has .includeÃ¢â?¬â?¢s.
  
  		       subend
  		       The card to end subcircuits (normally .ends).
  
  		       subinvoke
  		       The prefix to invoke subcircuits (normally x).
  
  		       substart
  		       The card to begin subcircuits (normally .subckt).
  
         There  are  a number of rusage parameters available, in addition to the
         ones available in nutmeg:
  
  
  
         If there are subcircuits in the input file, SPICE3 expands instances of
         them.   A  subcircuit  is  delimited by the cards .subckt and .ends, or
         whatever the value of the variables substart  and  subend  is,  respec-
         tively.	An  instance of a subcircuit is created by specifying a device
         with type Ã¢â?¬â?¢xÃ¢â?¬â?¢ - the device line is written
  
  	      xname node1 node2 ... subcktname
  
         where the nodes are the node names that replace the  formal  parameters
         on  the	.subckt	 line.	All  nodes  that are not formal parameters are
         prepended with the name given to the instance and a  Ã¢â?¬â?¢:Ã¢â?¬â?¢,  as  are  the
         names  of  the  devices	in the subcircuit. If there are several nested
         subcircuits, node and device names look like  subckt1:subckt2:...:name.
         If  the	variable  subinvoke is set, then it is used as the prefix that
         specifies instances of subcircuits, instead of Ã¢â?¬â?¢xÃ¢â?¬â?¢.
  
  VMS NOTES
         The standard suffix for rawspice files in VMS is &quot;.raw&quot;.
  
         You may have to redefine the value EDITOR if you wish to use  the  edit
         command, since the default for VMS is &quot;vi&quot;.
  
  SEE ALSO
         nutmeg(1),  sconvert(1),	 spice(1),  mfb(3), writedata(3) SPICE3 UserÃ¢â?¬â?¢s
         Guide
  
  AUTHORS
         SPICE3:	Tom Quarles (quarles@xxxxxxxxxxxxxxxx)
         nutmeg / User interface: Wayne Christopher (faustus@xxxxxxxxxxxxxxxx)
  
  BUGS
         SPICE3 will recognise all the notations used in SPICE2 .plot cards, and
         will translate vp(1) into ph(v(1)), and so forth. However, if there are
         spaces in these names it wonÃ¢â?¬â?¢t work. Hence v(1, 2) and (-.5, .5) arenÃ¢â?¬â?¢t
         recognised.
  
         BJTÃ¢â?¬â?¢s  can  have	 either 3 or 4 nodes, which makes it difficult for the
         subcircuit expansion routines to decide what to rename. If  the	fourth
         parameter  has  been  declared as a model name, then it is assumed that
         there are 3 nodes, otherwise it is considered a node. To	 disable  this
         kludge, you can set the variable &quot;nobjthack&quot;, which will force BJTÃ¢â?¬â?¢s to
         have 4 nodes (for the purposes of subcircuit expansion, at least).
  
         The @name[param] notation might not work with trace, iplot, etc.	  yet.
  
         The  first  line	 of  a	command	 file (except for the .spiceinit file)
         should be a comment.  Otherwise	SPICE  may  create  an	empty  circuit
         structure.
  
  CAVEATS
         SPICE3 files specified on the command line are read in before the .spi-
         ceinit file is read. Thus if you define aliases there that you call  in
         a  SPICE3  source  file	mentioned  on  the command line, they wonÃ¢â?¬â?¢t be
         recognised.
  
  
  
  
  4th Berkeley Distribution	 20 March 1986			      SPICE(1)
  </pre>
  
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  <h1><a name="olib_orcad_tm_converter_readme" id="olib_orcad_tm_converter_readme">olib (OrCAD (TM) converter) README</a></h1>
  <div class="level1">
  <pre class="code">###############################################################
  README and release notes for olib2geda - 1 settembre 2002
  OrCAD (TM) lib ASCII dump to gEDA .sym converter
  ###############################################################
  
  
  What it olib2geda?
  It's a simple automated converter from OrCAD v4 (in SDT version 1.10) parts
  library (in ASCII dump format, through &quot;decomp&quot; utility) to gEDA component 
  definition in .sym format file.
  It allow an initial dumb conversion file to file, with one lib converted in 
  multiple .sym file, one per component in library.
  The converted component file needs little editing to become usable, but in some
  case needs no editing at all.
  
  
  What olib do.
  * Convert box shaped component in OrCAD (TM) lib in .sym file in gEDA format
  * Place pin, pin name, pin type, pin number
  * Place logic bubble when needed (DOT attribute in OrCAD (TM), for logic nega-
      tion)
  * Place clock arrow when needed (CLK attribute)
  * Place reference, from REFERENCE statement in OrCAD (TM)
  * Place Part name as label and device name as attribute
  * Parse and draw non-box component, with LINE, ARC, CIRCLE and TEXT
  * Add power pin as invisible net=name:pin attribute when detected (in OrCAD (TM)
      invisible pin has tipically T0 and B0 coords)
  * Through command line switch, hides pin name in VECTOR drawed symbols, allowing
      better appearance
  * Write both new (20020825) and old (20020209) file format for .sym files 
      through a switch on the command line
  
  
  What olib do not.
  * Do not parse and store alternate component drawing (statement CONVERT in 
      OrCAD (TM))
  * Do not handle drawing part using VECTOR list from another part (statement
      VECTOR 'partname' in OrCAD (TM))
  * Do not handle FILL statement in VECTOR statement (incompatible with gEDA, but
      for what i know is used only for &quot;better&quot; part drawing)
  * Do not handle multiple part in one package (slots in gEDA)
  
  
  Bugs.
  More and more. But for the use that I do bugs aren't so critical.
  If you find a bug or want improvements to the program, feel free to contact me
  at the e-mail address at the end of this text.
  
  
  How to obtain last version.
  Open the URL:
  http://digilander.libero.it/tailchaser
  in section &quot;Linux&quot; you can see the main page of olib.
  
  
  Compile and install. 
  [[ Ales here, I have incorperated olib into the ./configure build mechanism,
     so these instructions only apply if you build from Mario's distribution ]]
  
  To compile program go in directory 'src' of the unpacked tarball, and type
  'make'. This produces the binary executable, named 'olib'.
  Compilation process uses the flex scanner generator to generate the file
  'olib.c' from the 'olib.lex', and link the library math to the code. The binary
  included in the distribution is compiled on a P266-MMX with RedHat 7.2, with gcc
  version 2.96 and flex 2.5.4, but the program don't require any special feature
  or critical function, as far as I know. At the end of compilation phase, you can
  see two warnings:
  * warning, -s option given but default rule can be matched
  * warning: `yyunput' defined but not used
  this is normal, don't affect program functionality, and you can safely ignore
  it.
  Installation is not needed for normal operations, but if you want you can copy
  only the executable (olib) on a directory in the PATH.
  
  
  Use of olib.
  To convert library, first convert it to ASCII dump with 'decomp' utility
  included in the OrCAD (TM) distribution. After that invoke the lib converter:
  olib path/to/file/file_ascii prefix where 'prefix' is used to generate file name
  of every symbol, like: 
  prefix-partname-1.sym 
  During the process, you can see a lot of ugly text scrolling in the terminal,
  that show the progress of the conversion. If you want to read this text, you can
  redirect the stderr output to a file: 
  olib path/to/file/file_ascii prefix 2&gt; logfile.txt
  where '2&gt;' instruct the shell to redirect stderr output to logfile.txt. 
  The converter write one file per part, in the current directory. At the end of
  the execution you can see a lot of file in the directory, extracted from OrCAD
  library.
  In the (not so improbable) case of incomplete conversion of a part (i.e. because
  of unsupported VECTOR 'partname' statement), the file of the incomplete part
  will be named 'prefix-partname-1.sym.part', stand for partial conversion.
  If the conversion process stops with the message: &quot;flex scanner jammed&quot;, the
  converter has encountered an unknown statement, an incompatible version of
  library, or a bug. If you can, please report the complete log and the library
  dump, to allow corrections or improvements.
  
  
  Mario Pascucci
  &lt;m.pas@xxxxxxxxx&gt;
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_pcb-quick_reference.html
  
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  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#pcbquick_reference" class="toc">PCB: Quick Reference</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#key_mapping" class="toc">Key Mapping</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#pcb_keystrokes" class="toc">PCB Keystrokes</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#viewport_keystrokes" class="toc">Viewport Keystrokes</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#footprint_reference" class="toc">Footprint Reference</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#general_syntax" class="toc">General syntax</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#elements" class="toc">Elements</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#pads" class="toc">Pads</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#pins" class="toc">Pins</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#examples" class="toc">Examples</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="pcbquick_reference" id="pcbquick_reference">PCB: Quick Reference</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-35] -->
  <h2><a name="key_mapping" id="key_mapping">Key Mapping</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [36-59] -->
  <h3><a name="pcb_keystrokes" id="pcb_keystrokes">PCB Keystrokes</a></h3>
  <div class="level3">
  <table class="inline">
  	<tr>
  		<th class="centeralign">  KEY 	</th><th class="centeralign">  MNEMONIC  </th><th class="centeralign">  DESCRIPTION  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  space  </td><td class="centeralign">  select  </td><td class="leftalign">enter select mode  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  esc  </td><td class="centeralign">  panner  </td><td class="leftalign">enter panning mode  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  tab  </td><td class="centeralign">  flip view  </td><td class="leftalign">view: flip board  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-del  </td><td class="centeralign">  del-cu  </td><td class="leftalign">deletes electrically connected copper (including power and signal planes)  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  \  </td><td class="centeralign">  thin-draw on/off  </td><td class="leftalign">toggles thin draw mode  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-alt-a  </td><td class="centeralign">  unselect  </td><td class="leftalign">clear selection  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  b  </td><td class="centeralign">  to other side  </td><td class="leftalign">flip object to the other side of the board  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-b  </td><td class="centeralign">  flip view  </td><td class="leftalign">view: flip board  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  c  </td><td class="centeralign">  center  </td><td class="leftalign">view: center display at cursor position  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  ctrl-c  </td><td class="centeralign">  copy to buffer  </td><td class="leftalign">copy selection to buffer and unselect  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  d  </td><td class="centeralign">  display name  </td><td class="leftalign">display pin or pad name  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-d  </td><td class="centeralign">  pinout dialog  </td><td class="leftalign">open pinout window for element under mouse cursor  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  e  </td><td class="centeralign">  extinguish rats  </td><td class="leftalign">delete all rats  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-e  </td><td class="centeralign">  eliminate some rats  </td><td class="leftalign">delete selected rats  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  f  </td><td class="centeralign">  find connections  </td><td class="leftalign">highlight connections to object under mouse cursor  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-f  </td><td class="centeralign">  no find-connections  </td><td class="leftalign">un-highlight found connections  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  g  </td><td class="centeralign">  increase grid  </td><td class="leftalign">increment grid by configured grid increment  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-g  </td><td class="centeralign">  decrease grid  </td><td class="leftalign">decrement grid by configured grid increment  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  h  </td><td class="centeralign">  hide  </td><td class="leftalign">toggle the visiblity of the refdes or value attached to the current component  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  ctrl-h  </td><td class="centeralign">  holeplate  </td><td class="leftalign">toggle plating of a via. Used to produce non metalized mounting holes  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  k  </td><td class="centeralign">  klearance  </td><td class="leftalign">increment clearance (soldermask to copper edge)  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-k  </td><td class="centeralign">  klear (-)  </td><td class="leftalign">decrement clearance (soldermask to copper edge (NOTE: can go negative!))  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  m  </td><td class="centeralign">  move to layer  </td><td class="leftalign">move the object under the cursor to the current layer  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-m  </td><td class="centeralign">  move selection to layer  </td><td class="leftalign">move selected objects to the current working layer (see <a href="http://geda.seul.org/wiki/geda:pcb_tips#how_do_i_move_one_set_of_layer_tracks_to_another_layer"; class="wikilink1" title="geda:pcb_tips">pcb tip</a>)  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  n  </td><td class="centeralign">  name  </td><td class="leftalign">show object refdes / pin number (depends on whatâ??s selected)  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-p  </td><td class="centeralign">  polygon close  </td><td class="leftalign">connect the first point of a polygon with the last  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  q  </td><td class="centeralign">  square toggle  </td><td class="leftalign">toggle square/round corners on pads  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  ctrl-r  </td><td class="centeralign">  report  </td><td class="leftalign">show object report  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  s  </td><td class="centeralign">  size  </td><td class="leftalign">increment size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-s  </td><td class="centeralign">  size (-)  </td><td class="leftalign">decrement size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  alt-s  </td><td class="centeralign">  sizehole  </td><td class="leftalign">increase the hole size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  alt-shift-s  </td><td class="centeralign">  sizehole (-)  </td><td class="leftalign">decrease the hole size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  ctrl-s  </td><td class="centeralign">  sizehole  </td><td class="leftalign">increase the hole size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  ctrl-shift-s  </td><td class="centeralign">  sizehole (-)  </td><td class="leftalign">decrease the hole size  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  v  </td><td class="centeralign">  view extents  </td><td class="leftalign">global view of working area  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  z  </td><td class="centeralign">  zoom  </td><td class="leftalign">view: zoom in  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-z  </td><td class="centeralign">  un-zoom  </td><td class="leftalign">view: zoom out  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F1  </td><td class="rightalign">    </td><td class="leftalign">via	tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F2  </td><td class="centeralign">  line  </td><td class="leftalign">tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F3  </td><td class="centeralign">  arc  </td><td class="leftalign">tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F4  </td><td class="centeralign">  text  </td><td class="leftalign">tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F5  </td><td class="centeralign">  rectangle  </td><td class="leftalign">tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F6  </td><td class="centeralign">  polygon  </td><td class="leftalign">tool  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F7  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F8  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F9  </td><td class="centeralign">  rotate  </td><td class="leftalign">rotate mode  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F10  </td><td class="centeralign">  file menu  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F11  </td><td class="centeralign">  select  </td><td class="leftalign">enter select mode (same as [space])  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  F12  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [60-2923] -->
  <h2><a name="viewport_keystrokes" id="viewport_keystrokes">Viewport Keystrokes</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<th class="centeralign">  KEY  </th><th class="centeralign">  MNEMONIC  </th><th class="centeralign">  DESCRIPTION  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  esc  </td><td class="centeralign">  panner  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  v  </td><td class="centeralign">  view extents  </td><td>global view of working area</td>
  	</tr>
  	<tr>
  		<td class="centeralign">  c  </td><td class="centeralign">  center  </td><td>centers view on cursor</td>
  	</tr>
  	<tr>
  		<td class="centeralign">  z  </td><td class="centeralign">  zoom  </td><td>zoom in</td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-z  </td><td class="centeralign">  un-zoom  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  \  </td><td class="centeralign">  thin-draw on/off  </td><td>toggles thin draw mode</td>
  	</tr>
  	<tr>
  		<td class="centeralign">  tab  </td><td class="centeralign">  flip view  </td><td>flip board</td>
  	</tr>
  	<tr>
  		<td class="centeralign">  shift-b  </td><td class="centeralign">  flip view  </td><td>flip board</td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [2924-3297] -->
  <h1><a name="footprint_reference" id="footprint_reference">Footprint Reference</a></h1>
  <div class="level1">
  
  <p>
  The Master document for footprint creation is the <a href="http://pcb.sourceforge.net/index.html#dir"; class="urlextern" title="http://pcb.sourceforge.net/index.html#dir";  rel="nofollow">PCB Manual</a>. There is also Stuart Brorsonâ??s <a href="http://www.brorson.com/gEDA/land_patterns_20050129.pdf"; class="urlextern" title="http://www.brorson.com/gEDA/land_patterns_20050129.pdf";  rel="nofollow">Footprint Creation for the Open-Source Layout Program PCB</a>.
  </p>
  
  </div>
  <!-- SECTION [3298-3591] -->
  <h2><a name="general_syntax" id="general_syntax">General syntax</a></h2>
  <div class="level2">
  
  <p>
  A pcb footprint file may contain any of the following commands:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong><code>Element [element_flags, description, pcb-name, value, mark_x, mark_y, text_x, text_y, text_direction, text_scale, text_flags]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>Pad [x1 y1 x2 y2 thickness clearance mask name pad_number flags]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>Pin [x y thickness clearance mask drillholedia name number flags]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>ElementArc [x y r1 r2 startangle sweepangle thickness]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>ElementLine [x1 y1 x2 y2 thickness] â??&gt; thickness != 1000 = 10 mils almost for all footprints</code></strong></div>
  </li>
  <li class="level1"><div class="li"> Comment lines start with the â??<strong><code>#</code></strong>â??-sign</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3592-4204] -->
  <h2><a name="elements" id="elements">Elements</a></h2>
  <div class="level2">
  
  <p>
  <strong><code>Element [element_flags, description, pcb-name, value, mark_x, mark_y, text_x, text_y, text_direction, text_scale, text_flags]</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th class="centeralign">  item  </th><th class="centeralign">  allowed value  </th><th class="centeralign">  explanation  </th><th class="centeralign">  comment  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  element_flags  </td><td class="centeralign">  unsigned hex value  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  description  </td><td class="centeralign">  string  </td><td class="centeralign">  text description of footprint  </td><td class="leftalign">written by footprint author  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  pcb name  </td><td class="centeralign">  string  </td><td class="centeralign">  refdes used on this particular pcb  </td><td class="leftalign">xxx  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  value  </td><td class="centeralign">  string  </td><td class="centeralign">  value of component on this particular pcb layout  </td><td class="leftalign">xxx  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  mark_x  </td><td class="centeralign">  1/100th mils  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  mark_y  </td><td class="centeralign">  1/100th mils  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  text_x  </td><td class="centeralign">  1/100th mils  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  text_y  </td><td class="centeralign">  1/100th mils  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  text direction  </td><td class="centeralign">  decimal integer  </td><td class="centeralign">  0=horiz; 1=ccw90; 2=180; 3=cw90  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  text_scale  </td><td class="centeralign">  decimal integer  </td><td class="rightalign">  </td><td class="leftalign">usu. set 100  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  text_flags  </td><td class="centeralign">  unsigned hex  </td><td class="rightalign">  </td><td class="rightalign">  </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [4205-5032] -->
  <h2><a name="pads" id="pads">Pads</a></h2>
  <div class="level2">
  
  <p>
  <strong><code>Pad[x1 y1 x2 y2 thickness clearance mask name pad_number flags]</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th class="centeralign">  Item  </th><th class="centeralign">  Allowed Value  </th><th class="centeralign">  Explanation  </th><th class="centeralign">  Comment  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  x1  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  x(1st point)  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  y1  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  y(1st point)  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  x2  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  x(2nd point)  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  y2  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  y(2nd point)  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  thickness  </td><td class="centeralign">  1/100 mils  </td><td class="centeralign">  width of metal surrounding line segment  </td><td class="leftalign">see Brorson .pdf  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  clearance  </td><td class="centeralign">  1/100 mils  </td><td class="centeralign">  distance to any other copper on any layer  </td><td class="leftalign">actually 1/2 of this number is used!  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  mask  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  width of mask relief  </td><td class="leftalign">actual width of the mask centered on pad copper  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  name  </td><td class="centeralign">  string  </td><td class="centeralign">  name of pad (arb. string)  </td><td class="leftalign">e.g. â??pad_1â?? or â??positiveâ?? or any other string  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  pad_number  </td><td class="centeralign">  string  </td><td class="centeralign">  pad #  </td><td class="leftalign">used for nets. it MUST be consistent with the definitions on the netlist.  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  flags  </td><td class="centeralign">  hex value  </td><td class="centeralign">  xxx  </td><td class="rightalign">  </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [5033-5937] -->
  <h2><a name="pins" id="pins">Pins</a></h2>
  <div class="level2">
  
  <p>
  <strong><code>Pin[x y thickness clearance mask drillholedia name number flags]</code></strong> 
  </p>
  <table class="inline">
  	<tr>
  		<th class="centeralign">  Item  </th><th class="leftalign"> Allowed Value  </th><th class="centeralign">  Explanation  </th><th class="centeralign">  Comment  </th>
  	</tr>
  	<tr>
  		<td class="centeralign">  x  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  pin x coord.  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  y  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  pin y coord.  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  thickness  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  copper diameter  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  clearance  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  2*(cu to cu clearance)  </td><td class="leftalign">if you want a 10 mil clearance, put 2000 (20 mils) here  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  mask  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  diameter of mask aperture  </td><td class="leftalign">actual dia. of hole in mask  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  drillholedia  </td><td class="centeralign">  1/100th mils  </td><td class="centeralign">  dia. of hole  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  name  </td><td class="centeralign">  string  </td><td class="centeralign">  arb. pin name  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  number  </td><td class="centeralign">  decimal integer  </td><td class="centeralign">  pin number used by nets/rats  </td><td class="rightalign">  </td>
  	</tr>
  	<tr>
  		<td class="centeralign">  flags  </td><td class="centeralign">  hex  </td><td class="centeralign">  xxx  </td><td class="rightalign">  </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [5938-6636] -->
  <h2><a name="examples" id="examples">Examples</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <strong><code>Pad[-24606 14760 -19538 14760 1181 2000 3181 â??â?? â??16â?? â??squareâ??]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>Pad[-14760 19538 -14760 24606 1181 2000 3181 â??â?? â??17â?? â??square,edge2â??]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>Pin[0 0 12000 2000 12500 6400 â??â?? â??1â?? 0Ã?00000001]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>ElementArc [0 0 6800 6800 0 360 1000]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>ElementLine [-26696 -26696 26696 -26696 1000]</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code># notes within PCB Footprints go after the pound sign</code></strong></div>
  </li>
  </ul>
  
  <p>
   <span class="hilited">This page is new, it is not complete, post comments/additions to geda-user w/ title â??PCB Quick Referenceâ??. Remember, subscribe to geda-user before you post to the geda-user e-mail list.</span>
  </p>
  
  </div>
  <!-- SECTION [6637-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_pcb.html
  
  Index: geda_pcb.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/geda_pcb_mp.html
  
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  <h1><a name="pcb_man-page" id="pcb_man-page">PCB man-page</a></h1>
  <div class="level1">
  <pre class="code">PCB(1)									PCB(1)
  
  
  
  NAME
         pcb - Printed circuit board layout tool
  
  
  SYNOPSIS
         pcb [options] [pcb file]
  
  
  DESCRIPTION
         The  pcb	 program  is  a tool for the layout of printed circuit boards.
         The complete manual for pcb is provided in a GNU texinfo format as well
         as HTML and PDF.	 The texinfo version of the manual is typically viewed
         with the info program or alternatively with emacs or a  graphical  info
         viewer	  such	  as	tkinfo	  /usr/local/share/pcb/pcb.html	   and
         /usr/local/share/pcb/pcb.pdf.  The prefix &quot;/usr/local&quot; may vary at your
         site.
  
  
  
  
  
  
  
  									PCB(1)</pre>
  
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  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#pcb_tools" class="toc">PCB Tools</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#where_can_i_read_about_the_basics_of_using_pcb" class="toc">Where can I read about the basics of using pcb?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_found_a_bug_what_can_i_do_about_it" class="toc">I found a bug! What can I do about it?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_can_i_set_the_manufacturing_rules_to_use_i.e._drill_diameters_trace_width_space_specs" class="toc">How can I set the manufacturing rules to use (i.e. drill diameters, trace width/space specs)?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#footprint_issues" class="toc">Footprint issues</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_pcb_s_footprints_work" class="toc">How do PCB's footprints work?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#where_can_i_get_pre-drawn_footprints_for_pcb" class="toc">Where can I get pre-drawn footprints for PCB?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_want_to_use_pcb_to_do_layout._how_do_i_know_what_value_to_use_for_the_footprint_attribute" class="toc">I want to use PCB to do layout. How do I know what value to use for the footprint attribute?</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#newlib" class="toc">Newlib</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#m4_library" class="toc">M4 library</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_is_the_recommended_way_to_deal_with_different_footprints_for_the_same_sort_of_device" class="toc">What is the recommended way to deal with different footprints for the same sort of device?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_draw_a_new_footprint" class="toc">How do I draw a new footprint?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_edit_change_an_existing_footprint" class="toc">How do I edit/change an existing footprint?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_add_a_footprint_library_to_pcb" class="toc">How do I add a footprint library to PCB?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#pcb_is_not_finding_my_footprints._why" class="toc">PCB is not finding my footprints. Why?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#now_that_i_have_all_of_these_footprints_where_do_i_put_them" class="toc">Now that I have all of these footprints where do I put them?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#component_placement" class="toc">Component placement</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_rotate_a_selection_i.e._of_more_than_one_item" class="toc">How do I rotate a selection (i.e. of more than one item)?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_the_size_of_a_graphical_object_such_as_text_silkscreen_lines_etc" class="toc">How do I change the size of a graphical object (such as text, silkscreen lines, etc)?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_put_components_on_both_faces_in_pcb" class="toc">How do I put components on both faces in PCB?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_set_the_origin_in_pcb" class="toc">How do I set the origin in pcb?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#routing" class="toc">Routing</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_route_a_connection_from_solder_to_component_side_and_back" class="toc">How do I route a connection from solder to component side and back?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_the_routing_style" class="toc">How do I change the routing style?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_got_stuck_how_do_i_go_back" class="toc">I got stuck! How do I go back?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_move_one_set_of_layer_tracks_to_another_layer" class="toc">How do I move one set of layer tracks to another layer?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_the_soldermask_clearance_around_a_hole_via" class="toc">How do I change the soldermask clearance around a hole/via?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_the_size_of_my_tracks" class="toc">How do I change the size of my tracks?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_drive_a_via_to_connect_a_track_to_a_ground_plane_on_a_different_layer" class="toc">How do I drive a via to connect a track to a ground plane on a different layer?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_want_to_draw_a_track_between_two_segments_on_the_same_net_but_pcb_won_t_let_me_why" class="toc">I want to draw a track between two segments on the same net, but PCB won't let me! Why?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#beyond_tracks_and_footprints" class="toc">Beyond tracks and footprints</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#i_can_t_copy_component_pads_in_a_layout._what_gives" class="toc">I can't copy component pads in a layout.  What gives?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_fill_areas_with_copper" class="toc">How do I fill areas with copper?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#the_polygons_are_shorting_my_tracks_what_can_i_do_about_it" class="toc">The polygons are shorting my tracks! What can I do about it?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_change_polygon_clearance" class="toc">How do I change polygon clearance?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_hide_the_polygons_while_i_edit_the_layout" class="toc">How do I hide the polygons while I edit the layout?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_edit_polygons" class="toc">How do I edit polygons?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_place_vias_that_connect_to_a_polygon_for_full_thermal_dissipation_or_full_shielding_integrity" class="toc">How do I place vias that connect to a polygon for full thermal dissipation or full shielding integrity?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#can_polygons_be_un-masked_can_a_polygon_be_made_bare-copper_with_no_solder_mask" class="toc">Can polygons be un-masked? (Can a polygon be made bare-copper with no solder mask?)</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_place_mounting_holes" class="toc">How do I place mounting holes?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#why_is_it_possible_to_make_a_thermal_for_pin_but_not_for_a_pad" class="toc">Why is it possible to make a thermal for pin, but not for a pad?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#can_pcb_be_used_to_make_single_layer_boards" class="toc">Can PCB be used to make single layer boards?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_resources_exist_to_process_pcb_files_using_scripts" class="toc">What resources exist to process PCB files using scripts?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_import_external_vector_graphics" class="toc">How do I import external vector graphics?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#auto_router" class="toc">Auto Router</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_force_the_autorouter_to_only_put_traces_on_a_particular_layer" class="toc">How do I force the autorouter to only put traces on a particular layer?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_force_the_autorouter_to_route_only_within_my_pcb_outline" class="toc">How do I force the autorouter to route only within my pcb outline?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_route_power_and_ground_planes_with_the_autorouter" class="toc">How do I route power and ground planes with the autorouter?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#the_layout_produced_by_the_autorouter_is_inefficient" class="toc">The layout produced by the autorouter is inefficient!</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#the_layout_produced_by_the_autorouter_is_ugly" class="toc">The layout produced by the autorouter is ugly!</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#gerber_generation_and_file_i_o_issues" class="toc">Gerber generation and file I/O issues</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker" class="toc">How do I make a board outline to go with my gerbers to the board maker?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#i_m_done_with_my_layout._how_should_i_check_my_design" class="toc">I'm done with my layout. How should I check my design?</a></span></div></li>
  </ul>
  </li>
  <li class="level1"><div class="li"><span class="li"><a href="#you_didn_t_answer_my_question._what_other_resources_exist_for_pcb_information" class="toc">You didn't answer my question. What other resources exist for PCB information?</a></span></div></li></ul>
  </div>
  </div>
  
  <h1><a name="pcb_tools" id="pcb_tools">PCB Tools</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-25] -->
  <h2><a name="where_can_i_read_about_the_basics_of_using_pcb" id="where_can_i_read_about_the_basics_of_using_pcb">Where can I read about the basics of using pcb?</a></h2>
  <div class="level2">
  
  <p>
  The <a href="http://pcb.sourceforge.net/manual.html"; class="urlextern" title="http://pcb.sourceforge.net/manual.html";  rel="nofollow">pcb manual</a> contains a concise description of the user interface in the section â??Getting Startedâ??(<a href="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Getting%20Started"; class="urlextern" title="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Getting%20Started";  rel="nofollow">version 20060422</a>)
  </p>
  
  </div>
  <!-- SECTION [26-323] -->
  <h2><a name="i_found_a_bug_what_can_i_do_about_it" id="i_found_a_bug_what_can_i_do_about_it">I found a bug! What can I do about it?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Start by reading <a href="http://pcb.sourceforge.net/bugs.html"; class="urlextern" title="http://pcb.sourceforge.net/bugs.html";  rel="nofollow">the pcb bug reporting page</a>.</div>
  </li>
  <li class="level1"><div class="li"> Check, what it needs to reproduce the bug.</div>
  </li>
  <li class="level1"><div class="li"> Ask on the <a href="http://www.geda.seul.org/mailinglist/index.html"; class="urlextern" title="http://www.geda.seul.org/mailinglist/index.html";  rel="nofollow">geda-user mailing</a> list if there is a work around, or has been dealt with in the bleading edge version of pcb. Note that you must subscribe to the geda-user e-mail list before you can post to this list.</div>
  </li>
  <li class="level1"><div class="li"> Check, wether the issue is already in the <a href="http://sourceforge.net/tracker/?group_id=73743&atid=538811"; class="urlextern" title="http://sourceforge.net/tracker/?group_id=73743&amp;atid=538811";  rel="nofollow">bug tracking system of pcb</a>. If not, file a bug report. Make sure to give every information necessary to reproduce the bug and add the version of pcb that contains the bug.</div>
  </li>
  <li class="level1"><div class="li"> Finally, as with all open source projects, you may flex your programming muscles and try to squish the bug yourself. Please file a patch of the changes you had to make to the <a href="http://sourceforge.net/tracker/?group_id=73743&atid=538811"; class="urlextern" title="http://sourceforge.net/tracker/?group_id=73743&amp;atid=538811";  rel="nofollow">BTS of pcb</a>. The patch will be gladly accepted to improve the next release of pcb.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [324-1386] -->
  <h2><a name="how_can_i_set_the_manufacturing_rules_to_use_i.e._drill_diameters_trace_width_space_specs" id="how_can_i_set_the_manufacturing_rules_to_use_i.e._drill_diameters_trace_width_space_specs">How can I set the manufacturing rules to use (i.e. drill diameters, trace width/space specs)?</a></h2>
  <div class="level2">
  
  <p>
  This topic is covered <a href="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Vendor%20drill%20mapping"; class="urlextern" title="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Vendor%20drill%20mapping";  rel="nofollow">in the documentation available at the PCB website</a>.
  </p>
  
  </div>
  <!-- SECTION [1387-1644] -->
  <h1><a name="footprint_issues" id="footprint_issues">Footprint issues</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1645-1676] -->
  <h2><a name="how_do_pcb_s_footprints_work" id="how_do_pcb_s_footprints_work">How do PCB's footprints work?</a></h2>
  <div class="level2">
  
  <p>
  PCB supports two entirely separate footprint library mechanisms:
  </p>
  <ol>
  <li class="level1"><div class="li"> The first is referred to as the â??oldlibâ??, â??pcblibâ??, or the â??M4 libraryâ??. This system is historic; it relies upon using the macro language M4 to generate footprints on the fly. The M4 library is fairly large, and has some bugs. Nonetheless, it can come in handy, and is distributed along with PCB itself.  A powerful feature of the m4 library is that an entire family of footprints can quickly be defined by defining an appropriate base macro.</div>
  </li>
  <li class="level1"><div class="li"> The second footprint library for PCB is called the â??newlibâ??. Newlib footprints are defined using <acronym title="American Standard Code for Information Interchange">ASCII</acronym> text files which call out each graphical primitive which makes up an entire footprint.  Newlib footprints can either be created graphically using PCB or via any other method which can produce a text file (text editor, awk/perl/ruby script, etc.).  </div>
  </li>
  </ol>
  
  <p>
   Therefore, during layout, you can use footprints which are distributed with PCB, you can find footprints via a web search, or you can create your own, and put them in a dedicated directory. The <a href="http://pcb.sourceforge.net/manual.html"; class="urlextern" title="http://pcb.sourceforge.net/manual.html";  rel="nofollow">pcb manual</a> has complete and up to date documentation for the element file format.  A somewhat incomplete but useful tutorial is available on the web at: <a href="http://www.brorson.com/gEDA/"; class="urlextern" title="http://www.brorson.com/gEDA/";  rel="nofollow">http://www.brorson.com/gEDA/</a> (search for the term &ldquo;newlib&rdquo;).
  </p>
  
  </div>
  <!-- SECTION [1677-3059] -->
  <h2><a name="where_can_i_get_pre-drawn_footprints_for_pcb" id="where_can_i_get_pre-drawn_footprints_for_pcb">Where can I get pre-drawn footprints for PCB?</a></h2>
  <div class="level2">
  
  <p>
  Currently, the best place to get footprints (besides in the PCB distribution) is the <a href="http://www.gedasymbols.org/"; class="urlextern" title="http://www.gedasymbols.org";  rel="nofollow">gEDA Symbols website</a>.  <a href="http://www.luciani.org/geda/pcb/pcb-footprint-list.html"; class="urlextern" title="http://www.luciani.org/geda/pcb/pcb-footprint-list.html";  rel="nofollow">John Luciani's website</a> has a large number of footprints and tools. Also, Darrell Harmon provides a nice footprint generating script <a href="http://www.dlharmon.com/geda/footgen.html"; class="urlextern" title="http://www.dlharmon.com/geda/footgen.html";  rel="nofollow">on his website</a>.  You are welcome to contribute to the project and share your footprints. Finally, you can ask on the geda-user list, and somebody might take pity on you and send you a symbol. Note that you must subscribe to the geda-user e-mail list before you can post an e-mail to the geda-user list.
  </p>
  
  </div>
  <!-- SECTION [3060-3798] -->
  <h2><a name="i_want_to_use_pcb_to_do_layout._how_do_i_know_what_value_to_use_for_the_footprint_attribute" id="i_want_to_use_pcb_to_do_layout._how_do_i_know_what_value_to_use_for_the_footprint_attribute">I want to use PCB to do layout. How do I know what value to use for the footprint attribute?</a></h2>
  <div class="level2">
  
  <p>
  This question is a common one amongst new gEDA users. Indeed, helping newbies determine the appropriate footprint names lies at the core of the ongoing <a href="http://geda.seul.org/wiki/geda:faq-gschem#what_s_this_business_about_heavy_vs._light_symbols"; class="wikilink1" title="geda:faq-gschem">light vs. heavy symbol</a> debate. In the current, light symbol gEDA/gaf distribution, you need to attach the footprint attribute at the schematic level (i.e. using either gschem or gattrib). The name of the footprint to use depends upon whether you are using the newlib or the M4 library (pcblib).
  </p>
  
  </div>
  <!-- SECTION [3799-4422] -->
  <h3><a name="newlib" id="newlib">Newlib</a></h3>
  <div class="level3">
  
  <p>
  The newlib stores one footprint per file, and the footprint names used by the newlib are the file names of the footprint files.
  </p>
  
  <p>
  There are several ways to determine the newlib footprint names to use:
  </p>
  <ul>
  <li class="level1"><div class="li"> You can browse the available footprints by running pcb and opening the footprint library window (available from the menu bar via â??Window â?? libraryâ??). Click on the â??newlibâ?? library group, and then select a sublibrary to browse its symbols. The name of each footprint appears in the â??Elementsâ?? window on the right hand side of the footprint library browser. Use the name exactly as it appears in the browser for the footprint attribute in gschem or gattrib.</div>
  </li>
  <li class="level1"><div class="li"> The newlib footprints distributed with PCB are stored in the directories under <strong><code>${PREFIX}/share/pcb/newlib</code></strong>. (<strong><code>${PREFIX}</code></strong> is the install directory you specified when configuring/building PCB.) The name to stick in the â??footprintâ?? attribute is the filename of the footprint you wish to use.<br/>
   For example, on my machine I installed gEDA with the prefix <strong><code>/usr/local/geda/</code></strong>. The 0805 package (for SMT resistors or caps) lives in a file with absolute path<br/>
   <strong><code>/usr/local/geda/share/pcb/newlib/generic_SMD_packages/0805_reflow_solder</code></strong> <br/>
   Therefore, to use this footprint on a component I set its â??footprintâ?? attribute to <strong><code>0805_reflow_solder</code></strong> using gschem or gattrib.<br/>
   Note that if the newlib symbol you want to use lives in a non-standard directory, gsch2pcb needs you to specify a path to that directory, either within your project.rc file (if you use one) or using the <strong><code>â??elements-dir</code></strong> flag (from the command line).</div>
  </li>
  <li class="level1"><div class="li"> Finally, since each new design typically requires you to draw at least a couple of new footprints, itâ??s likely you will have a local â??footprintsâ?? directory. As previously, the footprint name to use is the filename you assign to each of your new footprints. Again, donâ??t forget to add a line to your project.rc file telling gsch2pcb where to find your local footprints. Alternately, you can run gsch2pcb with the <strong><code>â??elements-dir</code></strong> flag set to point to your local footprint directory.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4423-6577] -->
  <h3><a name="m4_library" id="m4_library">M4 library</a></h3>
  <div class="level3">
  
  <p>
  The M4 library stores the footprints as M4 macros; there are usually several (many) footprints contained in each footprint file. The different footprints in a single file are generally variations on a single pattern (e.g. DIP-8, DIP-14, DIP-16, etc.)  The easiest way to find the correct footprint attribute name is by browsing through the &ldquo;pcblib&rdquo; library in the PCB library window.  The footprint attribute is given in square brackets in the description.  Also you can view the list of footprints from pcblib at the <a href="http://www.gedasymbols.org/footprints/"; class="urlextern" title="http://www.gedasymbols.org/footprints/";  rel="nofollow">gEDA Symbols webpage</a>.
  </p>
  
  <p>
  The following m4 libraries have received more attention and improvements than the others:
  </p>
  <ul>
  <li class="level1"><div class="li"> ~amp for Amp connectors</div>
  </li>
  <li class="level1"><div class="li"> ~amphenol for Amphenol connectors</div>
  </li>
  <li class="level1"><div class="li"> ~geda for many diverse parts used in basic design using gEDA (resistors, caps, etc).</div>
  </li>
  <li class="level1"><div class="li"> ~bourns for products like trim pots from Bourns</div>
  </li>
  <li class="level1"><div class="li"> ~cts for products like resistor packs from CTS</div>
  </li>
  <li class="level1"><div class="li"> ~johnstech for Johnstech sockets</div>
  </li>
  <li class="level1"><div class="li"> ~minicircuits for Minicircuits specific footprints</div>
  </li>
  <li class="level1"><div class="li"> ~panasonic for some Panasonic specific footprints</div>
  </li>
  </ul>
  
  <p>
   Finally, for both the newlib and the M4 lib, it is extremely important that you verify that the footprint name you use instantiates *exactly* the footprint you want when you place it in PCB. Therefore, it is critical to inspect the footprint before you use it. You can verify the footprint you want to use by clicking on it in the â??footprint libraryâ?? window, and then placing it onto an empty spot in PCBâ??s drawing area. Manually inspect the footprint to ensure that it has the correct number of pins/pads, correct dimensions, etc.
  </p>
  
  <p>
  Also, once you generate Gerber files, make sure you <span class="curid"><a href="http://geda.seul.org/wiki/geda:pcb_tips#i_m_done_with_my_layout._how_should_i_check_my_design"; class="wikilink1" title="geda:pcb_tips">inspect all footprints instantiated in your Gerbers</a></span> using gerbv (or an equivalent Gerber viewer) before you send your design out for fabrication.
  </p>
  
  </div>
  <!-- SECTION [6578-8487] -->
  <h2><a name="what_is_the_recommended_way_to_deal_with_different_footprints_for_the_same_sort_of_device" id="what_is_the_recommended_way_to_deal_with_different_footprints_for_the_same_sort_of_device">What is the recommended way to deal with different footprints for the same sort of device?</a></h2>
  <div class="level2">
  
  <p>
  For example, an opamp may be DIP8 or SO8. A resistor may be 0603, 0805, 1208, or through-hole. How do I know what package and footprint to use, and how do I manage the choices?
  </p>
  
  <p>
  First off, the footprint you should use is a decision for you to make, not your CAD tool. It is up to you to choose your preferred package type/footprint, and then attach the correct footprint attribute to the component in the schematic. Once you have choosen which package (and footprint) you wish to use, then either <span class="curid"><a href="http://geda.seul.org/wiki/geda:pcb_tips#where_can_i_get_pre-drawn_footprints_for_pcb"; class="wikilink1" title="geda:pcb_tips">find an appropriate footprint</a></span>, or <span class="curid"><a href="http://geda.seul.org/wiki/geda:pcb_tips#how_do_i_draw_a_new_footprint"; class="wikilink1" title="geda:pcb_tips">draw one yourself</a></span> and save it in a local directory.
  </p>
  
  <p>
  As far as managing the footprint choices (and indeed the large number of component attributes you are likely to have): Use <a href="http://geda.seul.org/wiki/geda:faq-attribs#help_my_design_has_hundreds_of_components_and_it_s_a_pain_to_use_gschem_to_attach_all_my_attributes"; class="wikilink1" title="geda:faq-attribs">gattrib</a>. Thatâ??s what itâ??s for.
  </p>
  
  </div>
  <!-- SECTION [8488-9565] -->
  <h2><a name="how_do_i_draw_a_new_footprint" id="how_do_i_draw_a_new_footprint">How do I draw a new footprint?</a></h2>
  <div class="level2">
  
  <p>
  Everybody does this a little differently. Some people draw the footprint entirely using PCB. Some people first draw a preliminary footprint in PCB, and then finish it off by hand editing it (e.g. using emacs). Some people write <acronym title="Practical Extraction and Report Language">Perl</acronym> scripts to autogenerate footprints.
  </p>
  
  <p>
  Karel Kulhavy prefers to draw the footprint entirely using PCB, which might be the most non-threatening method for newbies to use. He maintains a <a href="http://ronja.twibright.com/guidelines/footprints.php"; class="urlextern" title="http://ronja.twibright.com/guidelines/footprints.php";  rel="nofollow">HOWTO describing his footprint creation prodedure</a> on his Ronja website.
  </p>
  
  </div>
  <!-- SECTION [9566-10154] -->
  <h2><a name="how_do_i_edit_change_an_existing_footprint" id="how_do_i_edit_change_an_existing_footprint">How do I edit/change an existing footprint?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Select element</div>
  </li>
  <li class="level1"><div class="li"> Copy into buffer</div>
  </li>
  <li class="level1"><div class="li"> Break buffer into pieces</div>
  </li>
  <li class="level1"><div class="li"> Paste buffer</div>
  </li>
  <li class="level1"><div class="li"> Do change</div>
  </li>
  <li class="level1"><div class="li"> Select everything</div>
  </li>
  <li class="level1"><div class="li"> Copy into buffer</div>
  </li>
  <li class="level1"><div class="li"> Convert buffer into element</div>
  </li>
  <li class="level1"><div class="li"> Paste buffer</div>
  </li>
  <li class="level1"><div class="li"> Go over every pad and press q. (This squares off the rounded pad edges.)</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [10155-10480] -->
  <h2><a name="how_do_i_add_a_footprint_library_to_pcb" id="how_do_i_add_a_footprint_library_to_pcb">How do I add a footprint library to PCB?</a></h2>
  <div class="level2">
  
  <p>
  Adding footprint libraries to PCB is easy: <strong><em>File</em></strong> menu â??&gt; <strong><em>Preferences</em></strong> â??&gt; <strong><em>Library</em></strong> â??&gt; <strong>FOOTPRINTDIRECTORY</strong>
  </p>
  
  <p>
  Donâ??t forget to include the new directory into your gsch2pcb resource file (if you are using gsch2pcb, that is).
  </p>
  
  </div>
  <!-- SECTION [10481-10785] -->
  <h2><a name="pcb_is_not_finding_my_footprints._why" id="pcb_is_not_finding_my_footprints._why">PCB is not finding my footprints. Why?</a></h2>
  <div class="level2">
  
  <p>
  The footprint path that PCB uses is defined using the <strong><code>Pcb.elementPath</code></strong> variable in the app-defaults file named <strong><code>PCB</code></strong>. The path for the <strong><code>PCB</code></strong> file is set using the <strong><code>XAPPLRESDIR</code></strong> environment variable which is typically set from within the wrapper script named <strong><code>pcb</code></strong>.
  </p>
  
  </div>
  <!-- SECTION [10786-11133] -->
  <h2><a name="now_that_i_have_all_of_these_footprints_where_do_i_put_them" id="now_that_i_have_all_of_these_footprints_where_do_i_put_them">Now that I have all of these footprints where do I put them?</a></h2>
  <div class="level2">
  
  <p>
  I prefer to place all â??production-readyâ?? footprints in a single directory that is not in the gEDA/PCB install tree. When a new version of gEDA/PCB comes out I do not make any changes to project files or libraries. If there are newlib footprints in the PCB library that I want to use I copy them to the â??production-readyâ?? footprint directory.
  </p>
  
  <p>
  Rather than change configuration files to get gsch2pcb to find the footprints I create a wrapper script called <strong><code>sch2pcb</code></strong> that contains the footprint path. All users use the same script and access the same production footprints.
  </p>
  
  <p>
  To use the <strong><code>sch2pcb</code></strong> script that is listed below replace the string <strong><code>FOOTPRINT_DIR</code></strong> with your footprint directory: 
  </p>
  <pre class="code">#!/bin/bash
  gsch2pcb ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½elements-dir FOOTPRINT_DIR $@</pre>
  
  </div>
  <!-- SECTION [11134-12011] -->
  <h1><a name="component_placement" id="component_placement">Component placement</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [12012-12046] -->
  <h2><a name="how_do_i_rotate_a_selection_i.e._of_more_than_one_item" id="how_do_i_rotate_a_selection_i.e._of_more_than_one_item">How do I rotate a selection (i.e. of more than one item)?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Select the items</div>
  </li>
  <li class="level1"><div class="li"> Buffer â?? Cut selection to buffer</div>
  </li>
  <li class="level1"><div class="li"> Buffer â?? Rotate buffer 90 deg CCW (or CW)</div>
  </li>
  <li class="level1"><div class="li"> Click anywhere on the board and the selection is pasted on the design again.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [12047-12306] -->
  <h2><a name="how_do_i_change_the_size_of_a_graphical_object_such_as_text_silkscreen_lines_etc" id="how_do_i_change_the_size_of_a_graphical_object_such_as_text_silkscreen_lines_etc">How do I change the size of a graphical object (such as text, silkscreen lines, etc)?</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> Mouse over the object and hit [<strong><code>s</code></strong>]. This will increase the size of the object you are mousing over.</div>
  </li>
  <li class="level1"><div class="li"> Mouse over the object and hit [<strong><code>&lt;shift&gt;-S</code></strong>]. This will decrease the size of the object you are mousing over.</div>
  </li>
  </ul>
  
  <p>
   You can alter the increase/decrease quantum using the <strong><em>file</em></strong> â?? <strong><em>preferences</em></strong> â?? <strong><em>increments</em></strong> menu.
  </p>
  
  </div>
  <!-- SECTION [12307-12756] -->
  <h2><a name="how_do_i_put_components_on_both_faces_in_pcb" id="how_do_i_put_components_on_both_faces_in_pcb">How do I put components on both faces in PCB?</a></h2>
  <div class="level2">
  
  <p>
  There are two ways to do it:
  </p>
  <ul>
  <li class="level1"><div class="li"> Pressing the tab key will alternate the active side between the component and solder sides. When you place components, they will go on the active side.</div>
  </li>
  <li class="level1"><div class="li"> If you are viewing one side of the board, place a component there and (with the cursor over it) press the [<strong><code>b</code></strong>] key (wich means, send the component to the Back side) the component go to the other side of the board.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [12757-13225] -->
  <h2><a name="how_do_i_set_the_origin_in_pcb" id="how_do_i_set_the_origin_in_pcb">How do I set the origin in pcb?</a></h2>
  <div class="level2">
  
  <p>
  The absolute origin is always in the upper left corner of the accessible area. This cannot be set to some other place. However, coordinates of objects can also be given relative to the current grid. In the GTK2 version of pcb coordinates are shown in the upper right corner of the main window. The right pair is the absolute position, while the left pair reflects the position relative to an arbitrary marker. This marker is set to the current position of the mouse by the key sequence [<strong><code>ctrl-m</code></strong>]. You may want to set the marker to a grid point or a specific pin.
  </p>
  
  </div>
  <!-- SECTION [13226-13840] -->
  <h1><a name="routing" id="routing">Routing</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [13841-13862] -->
  <h2><a name="how_do_i_route_a_connection_from_solder_to_component_side_and_back" id="how_do_i_route_a_connection_from_solder_to_component_side_and_back">How do I route a connection from solder to component side and back?</a></h2>
  <div class="level2">
  
  <p>
  While using the line tool, use the number keys on top of the keyboard to switch layers. A via will be placed automatically at the endpoint of the last complete segment.
  </p>
  
  </div>
  <!-- SECTION [13863-14112] -->
  <h2><a name="how_do_i_change_the_routing_style" id="how_do_i_change_the_routing_style">How do I change the routing style?</a></h2>
  <div class="level2">
  
  <p>
  There is a set of predefined sizes for routing. The sets bear suggestive names (Signal, Power, Fat and Skinny), but the actual value of the sizes can be configured to your needs. The line tool knows about different styles to deal with transversal connections:
  </p>
  <ol>
  <li class="level1"><div class="li"> 45Â° plus vertical/horizontal (status line: â??\_â??)</div>
  </li>
  <li class="level1"><div class="li"> vertical plus 45Â° (status line: â??_/â??)</div>
  </li>
  <li class="level1"><div class="li"> arbitrary angle (status line: â??allâ??)</div>
  </li>
  </ol>
  
  <p>
   The way to access these modes differs among the pcb <acronym title="Graphical User Interface">GUI</acronym> versions. The current GTK snapshot (v20050609) is hard wired to â??_/â?? but can be temporarily turned to â??\_â?? with the shift key. For arbitrary angles, choose â??enable all line directionsâ?? in the setting menu.
  </p>
  
  </div>
  <!-- SECTION [14113-14845] -->
  <h2><a name="i_got_stuck_how_do_i_go_back" id="i_got_stuck_how_do_i_go_back">I got stuck! How do I go back?</a></h2>
  <div class="level2">
  
  <p>
  The universal undo key [<strong><code>U</code></strong>] works even while in the middle of track layout actions. It will remove the last segment but keep the line tool attached to the mouse. So you can immediately go on routing and find a better way.
  </p>
  
  </div>
  <!-- SECTION [14846-15118] -->
  <h2><a name="how_do_i_move_one_set_of_layer_tracks_to_another_layer" id="how_do_i_move_one_set_of_layer_tracks_to_another_layer">How do I move one set of layer tracks to another layer?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Select the tracks. Itâ??s easiest to do this if you shut off everything but that layer first (i.e. silk, pins, other layers, etc).</div>
  </li>
  <li class="level1"><div class="li"> Now set the current layer to be the new layer. Yes, the layer might get displayed; not a problem as youâ??ve already selected the tracks you want.</div>
  </li>
  <li class="level1"><div class="li"> Press [<strong><code>shift-M</code></strong>] to move all the selected tracks to the current layer.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [15119-15555] -->
  <h2><a name="how_do_i_change_the_soldermask_clearance_around_a_hole_via" id="how_do_i_change_the_soldermask_clearance_around_a_hole_via">How do I change the soldermask clearance around a hole/via?</a></h2>
  <div class="level2">
  
  <p>
  You can increase the soldermask clearance from any hole/via by positioning the cursor over the object and typing the [<strong><code>k</code></strong>] key. You can decrease the clearance by using the [<strong><code>&lt;shift&gt;-K</code></strong>] key.
  </p>
  
  </div>
  <!-- SECTION [15556-15831] -->
  <h2><a name="how_do_i_change_the_size_of_my_tracks" id="how_do_i_change_the_size_of_my_tracks">How do I change the size of my tracks?</a></h2>
  <div class="level2">
  
  <p>
  There are a number of ways to change the size of already laid down tracks:
  </p>
  <ol>
  <li class="level1"><div class="li"> Use [<strong><code>s</code></strong>] and [<strong><code>shift-s</code></strong>] to increase and decrease the size of the track currenty under the mouse cursor.</div>
  </li>
  <li class="level1"><div class="li"> choose <strong><code>Select/Change_size_of_selected_objects/Decrement_lines_by_4mil</code></strong> from the <strong><code>Select</code></strong> menu. The actual amount of change can be set in <strong><code>File/Preferences/Sizes</code></strong>. This only acts on the tracks. So the selection may contain components, text, vias and the like.</div>
  </li>
  <li class="level1"><div class="li"> Select the tracks to be changed and type <strong><code>:ChangeSize(SelectedLines,+4,mils)</code></strong>. The colon gets you to the command line and <strong><code>ChangeSize()</code></strong> is the command version of the previously described action. Replace â??<strong><code>+4</code></strong>â?? by the amount you want to increase the track size. Use the minus sign to decrease the tracksize. If you omit the sign the command sets the track size to the value given.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [15832-16769] -->
  <h2><a name="how_do_i_drive_a_via_to_connect_a_track_to_a_ground_plane_on_a_different_layer" id="how_do_i_drive_a_via_to_connect_a_track_to_a_ground_plane_on_a_different_layer">How do I drive a via to connect a track to a ground plane on a different layer?</a></h2>
  <div class="level2">
  <ol>
  <li class="level1"><div class="li"> Set the GND plane layer as the active layer.</div>
  </li>
  <li class="level1"><div class="li"> Select the â??viaâ?? tool.</div>
  </li>
  <li class="level1"><div class="li"> Place the via where you want it to live (left click to place).</div>
  </li>
  <li class="level1"><div class="li"> Now select the â??thermalâ?? tool.</div>
  </li>
  <li class="level1"><div class="li"> Left click on the via you just placed.</div>
  </li>
  <li class="level1"><div class="li"> Now change the active layer to your desired routing layer.</div>
  </li>
  <li class="level1"><div class="li"> Select the â??lineâ?? tool.</div>
  </li>
  <li class="level1"><div class="li"> Route the track on the active layer to or from the via as usual.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [16770-17255] -->
  <h2><a name="i_want_to_draw_a_track_between_two_segments_on_the_same_net_but_pcb_won_t_let_me_why" id="i_want_to_draw_a_track_between_two_segments_on_the_same_net_but_pcb_won_t_let_me_why">I want to draw a track between two segments on the same net, but PCB won't let me! Why?</a></h2>
  <div class="level2">
  
  <p>
  You are likely drawing tracks with auto-DRC on. To connect the two segments, here are some suggestions:
  </p>
  <ul>
  <li class="level1"><div class="li"> DRC enforcement uses the ratsnest to determine where a track is allowed to go. Thus, you must have the ratsnest drawn in order to make connections in auto-DRC mode. Otherwise you will not be allowed to connect (or approach) any copper that is not already connected to your net. (If the rat visibility bothers you, you can hide the rats layer â?? but the rats must exist).</div>
  </li>
  <li class="level1"><div class="li"> You should also refresh the rats regularly when drawing. Hit [<strong><code>o</code></strong>] to redraw/re-optimize the rats. Make sure a rat is visibly connecting the two pieces of metal you want to connect.</div>
  </li>
  <li class="level1"><div class="li"> It is also possible that you will experience this situation when drawing tracks between pins in a connector. In this case, it is possible that your track width violates the clearance requirements of the pin field. Try decreasing the pin-to-metal clearance, or use a narrower track width.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [17256-18320] -->
  <h1><a name="beyond_tracks_and_footprints" id="beyond_tracks_and_footprints">Beyond tracks and footprints</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [18321-18363] -->
  <h2><a name="i_can_t_copy_component_pads_in_a_layout._what_gives" id="i_can_t_copy_component_pads_in_a_layout._what_gives">I can't copy component pads in a layout.  What gives?</a></h2>
  <div class="level2">
  
  <p>
  <strong>Question:</strong>  I want to copy a section of my existing layout to another spot.  
  </p>
  
  <p>
  I can select the existing area.  Everything turns pretty blue.
  </p>
  
  <p>
  &ldquo;Buffer&rdquo;&ndash;&gt;&rdquo;Copy Selection To Buffer&rdquo; seems to succeed (no complaints).
  </p>
  
  <p>
  Then I go to paste the copied area... and all that moves are a couple of traces and some vias.  The pads I&rsquo;ve painstakingly created aren&rsquo;t copied.   What gives!?!?!?
  </p>
  
  <p>
  <strong>Answer:</strong>  If the silk layer is off, you can&rsquo;t copy elements through the paste buffer.  Weird, but that&rsquo;s how it works.  Therefore, turn on the silk layer before trying to copy a section of a layout.
  </p>
  
  </div>
  <!-- SECTION [18364-19019] -->
  <h2><a name="how_do_i_fill_areas_with_copper" id="how_do_i_fill_areas_with_copper">How do I fill areas with copper?</a></h2>
  <div class="level2">
  
  <p>
  Use rectangles and polygon planes. These items will always avoid vias, pads and pins. Tracks are also avoided, if they have the clear polygons flag set. (menu: Settings/Enable_new_lines_clear_polygons)
  </p>
  
  </div>
  <!-- SECTION [19020-19267] -->
  <h2><a name="the_polygons_are_shorting_my_tracks_what_can_i_do_about_it" id="the_polygons_are_shorting_my_tracks_what_can_i_do_about_it">The polygons are shorting my tracks! What can I do about it?</a></h2>
  <div class="level2">
  
  <p>
  You didnâ??t have â??Enable_new_lines_clear_polygonsâ?? checked in the settings menu when you layed down the tracks. Enter â??changejoin(selection)â?? in the command window to toggle this flag for all tracks that are currently selected. The keyboard shortcut to this action is [<strong><code>shift-j</code></strong>].
  </p>
  
  </div>
  <!-- SECTION [19268-19637] -->
  <h2><a name="how_do_i_change_polygon_clearance" id="how_do_i_change_polygon_clearance">How do I change polygon clearance?</a></h2>
  <div class="level2">
  
  <p>
  Press [<strong><code>k</code></strong>] to increase the clearence of the object under the cursor. Use [<strong><code>ctrl-k</code></strong>] to increase the clearence of selected objects. Add the [<strong><code>shift</code></strong>] modifier to decrease the clearence. To change a whole track press [<strong><code>f</code></strong>] to find all segments that are connected to the object under the cursor and apply the action â??select(connection)â??.
  </p>
  
  <p>
  The amount of the increment can be configured in the dialog File/Preference/Increments.
  </p>
  
  </div>
  <!-- SECTION [19638-20138] -->
  <h2><a name="how_do_i_hide_the_polygons_while_i_edit_the_layout" id="how_do_i_hide_the_polygons_while_i_edit_the_layout">How do I hide the polygons while I edit the layout?</a></h2>
  <div class="level2">
  
  <p>
  Put the polygons (and rectangles) on a separate layer. Use the preference to make sure, this layer is not in the same group as the tracks. Disable the layer by a click on the corresponding layer button in the main window. After you are finished with the changes, use the preference dialog to let the polygon layer join the layer of the tracks.
  </p>
  
  </div>
  <!-- SECTION [20139-20547] -->
  <h2><a name="how_do_i_edit_polygons" id="how_do_i_edit_polygons">How do I edit polygons?</a></h2>
  <div class="level2">
  
  <p>
  There are four basic ways to edit polygon outlines. You can move and delete vertices and you can insert vertices using two techniques. Polygons can be edited equally well in â??thin line drawâ?? mode (settings â??&gt; enable thin line draw) or in normal mode. Moving a vertex is easily accomplished by un-selecting your polygon and then clicking and dragging that vertex to a new location. To delete a vertex, a corner in your polygon, put your crosshairs over the point and hit â??deleteâ?? on the keyboard. To insert a vertex, youâ??ll use the insert tool (â??insertâ?? keystroke). Start by clicking the edge you want to split with a new point. Click and drag a new point into the polygon. A variation on this technique is 1) click to select, followed by 2) click to place new vertex.
  </p>
  
  <p>
  (NOTE: Inserting points into polygon will generally work ONLY with â??all direction linesâ?? enabled (â??settings â??&gt; enable all direction linesâ??). This is because PCB has a powerful 45/90 degree constraints system. If you try to insert new vertices into a polygon that donâ??t fall onto lines of proper 45 and 90 degree constraints, PCB disallows the action!)
  </p>
  
  </div>
  <!-- SECTION [20548-21733] -->
  <h2><a name="how_do_i_place_vias_that_connect_to_a_polygon_for_full_thermal_dissipation_or_full_shielding_integrity" id="how_do_i_place_vias_that_connect_to_a_polygon_for_full_thermal_dissipation_or_full_shielding_integrity">How do I place vias that connect to a polygon for full thermal dissipation or full shielding integrity?</a></h2>
  <div class="level2">
  
  <p>
  Often itâ??s useful to have vias connect completely to a polygon (a field of copper) for heat transferâ?? the apparent problem is that PCB polygons have only a single â??clear pins/viasâ?? flag for the entire polygon (toggled by the [<strong><code>s</code></strong>] key). Our goal is to only connect some of the pins/vias to the polygon, but to connect them better than a thermal does. Here are a few ways to do this:
  </p>
  
  <p>
  One way, youâ??ll make an object thatâ??s almost just like a thermal in that it goes between your via and the polygonâ??the difference is that youâ??ll actually create an annulus to completely fill the space between the hole and polygon (which because itâ??s clearance is turned on, is not connected to the pin). This annulus is four arc segments. You can copy these four items to the buffer to create a â??zero-clearance thermal toolâ??. The drawback of this trick is that when you change via size, youâ??ll also have to modify the size of these filler parts.
  </p>
  
  <p>
  The arcs allow you to use this fill trick in tight places by only placing, say two of the four arcs.
  </p>
  
  <p>
  Another trick is to make a zero-length line. Take a single line segment and move the end-point on top of the start-point. Now you have a â??single point lineâ?? (a circle) with the diameter equal to the line thickness. Move to different layers ([<strong><code>m</code></strong>] key) as you see fit. Place this object centered on your via to connect it to a polygon.
  </p>
  
  <p>
  Power-users may want to keep a small custom library of these parts by saving them as elements. Itâ??s also handy to put these â??partsâ?? in one of your PCB buffers so theyâ??re at your fingertips.
  </p>
  
  <p>
  You can also add another polygon on-top of the polygon to which you want to connect you vias. Youâ??ll un-set the â??clear pins/viasâ?? flag and the vias will be connected to the larger polygon underneath.
  </p>
  
  </div>
  <!-- SECTION [21734-23663] -->
  <h2><a name="can_polygons_be_un-masked_can_a_polygon_be_made_bare-copper_with_no_solder_mask" id="can_polygons_be_un-masked_can_a_polygon_be_made_bare-copper_with_no_solder_mask">Can polygons be un-masked? (Can a polygon be made bare-copper with no solder mask?)</a></h2>
  <div class="level2">
  
  <p>
  Currently this is not possible in PCB. The usual workaround (for example if you want to leave a bare area to attach a heatsink or shielding) is to make an element that is a single pad. This pad should be as small as possible (0 x 0) but with a large clearance. Itâ??s the soldermask clearance from this part you will use to un-mask the polygon. PCB internally limits the size of the pad to 250 mils. For larger exposed areas you will need to use multiple pads.
  </p>
  
  </div>
  <!-- SECTION [23664-24221] -->
  <h2><a name="how_do_i_place_mounting_holes" id="how_do_i_place_mounting_holes">How do I place mounting holes?</a></h2>
  <div class="level2">
  
  <p>
  Use a footprint for the mounting hole or place a via.
  </p>
  
  <p>
  If the pads surrounding the mounting hole need to be electrically connected then you should show the connection in your schematic. Add a symbol for the mounting hole and change its footprint attribute.
  </p>
  
  <p>
  My preference is to create PCB footprints for the various types of mounting hardware. I have a variety of silkscreens for various hardware combinations (hex nut, hex nut with washer, etc.) The silkscreen provides a convenient placement reference during PCB layout.
  </p>
  
  <p>
  For footprint examples see <a href="http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Hardware"; class="urlextern" title="http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Hardware";  rel="nofollow">http://www.luciani.org/geda/pcb/pcb-footprint-list.html#Hardware</a>.
  </p>
  
  </div>
  <!-- SECTION [24222-24886] -->
  <h2><a name="why_is_it_possible_to_make_a_thermal_for_pin_but_not_for_a_pad" id="why_is_it_possible_to_make_a_thermal_for_pin_but_not_for_a_pad">Why is it possible to make a thermal for pin, but not for a pad?</a></h2>
  <div class="level2">
  
  <p>
  The reason is that pins usually have sufficient spacing that the plane surrounding them remains intact on all sides and pads usually are so tightly spaced that they do not. Because of this you must manually draw the thermal â??fingersâ?? to connect the pad to the ground plane. Be sure that you have the settings such that new lines connect to planes when you draw them. If you need to make several such thermals, spend a little time making the first one just the way you want then copy the fingers to the buffer and paste it where you want the others.
  </p>
  
  </div>
  <!-- SECTION [24887-25517] -->
  <h2><a name="can_pcb_be_used_to_make_single_layer_boards" id="can_pcb_be_used_to_make_single_layer_boards">Can PCB be used to make single layer boards?</a></h2>
  <div class="level2">
  
  <p>
  Yes. Just plot your gerbers and toss any layers that are not needed. You can just draw the layout as you want (freestyle). If you want to verify connectivity, you have two choices:
  </p>
  <ol>
  <li class="level1"><div class="li"> Assuming your copper is on the bottom side, use the top side in layout to put down traces where jumpers will be. This is probably the easiest. Then just fab the bottom side and put jumpers wherever you have top side copper.</div>
  </li>
  <li class="level1"><div class="li"> Create a â??jumperâ?? symbol in the schematic and put that in places where you need a jumper. This is likely to be a major pain, but you can enforce dimensions of the jumpers this way if you care.</div>
  </li>
  </ol>
  
  <p>
   If youâ??re trying to use the autorouter, just turn off all but the bottom layer when you route and it will stick to that layer.
  </p>
  
  </div>
  <!-- SECTION [25518-26315] -->
  <h2><a name="what_resources_exist_to_process_pcb_files_using_scripts" id="what_resources_exist_to_process_pcb_files_using_scripts">What resources exist to process PCB files using scripts?</a></h2>
  <div class="level2">
  
  <p>
  One of PCB&rsquo;s great features is that it uses an easily understood <acronym title="American Standard Code for Information Interchange">ASCII</acronym> file format.  Therefore, many people use scripts (commonly <acronym title="Practical Extraction and Report Language">Perl</acronym>) to process their boards in various ways.  You can use these scripts either as they are, or modify them to suit your own goals.  Here are some links to available scripts: 
  </p>
  <ol>
  <li class="level1"><div class="li"> John Luciani has a large number of <a href="http://www.luciani.org/geda/pcb/pcb-perl-library.html"; class="urlextern" title="http://www.luciani.org/geda/pcb/pcb-perl-library.html";  rel="nofollow">scripts</a> available on <a href="http://www.luciani.org/"; class="urlextern" title="http://www.luciani.org";  rel="nofollow"> his website</a>.  Included in his collection are scripts for generating footprints, as well as </div>
  </li>
  <li class="level1"><div class="li"> David Rowe has scripts for updating elements as well as adding/subtracting PCB files from each other on <a href="http://www.rowetel.com/perl4pcb.html"; class="urlextern" title="http://www.rowetel.com/perl4pcb.html";  rel="nofollow">his website.</a></div>
  </li>
  <li class="level1"><div class="li"> Stuart Brorson wrote a simple script which generates footprints for two terminal SMT passives.  A gzipped tarball is available <a href="http://www.brorson.com/gEDA/Smtgen.pl.gz"; class="urlextern" title="http://www.brorson.com/gEDA/Smtgen.pl.gz";  rel="nofollow"> here </a>.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [26316-27279] -->
  <h2><a name="how_do_i_import_external_vector_graphics" id="how_do_i_import_external_vector_graphics">How do I import external vector graphics?</a></h2>
  <div class="level2">
  
  <p>
  There is a third party open source utility called <a href="http://www.pstoedit.net/"; class="urlextern" title="http://www.pstoedit.net/";  rel="nofollow">pstoedit</a> that converts postscript data to pcb format. It is included in most major linux distributions. You can use your favorite vector graphics utility to produce a logo or any kind of fancy layout. Export as eps if you can and make sure that your logo fits into the bounding box (check with a postscript viewer such as ggv). If there is no eps export available, you can produce postscript by printing to a file. In this case you may add a bounding   box with <a href="http://www.cs.wisc.edu/~ghost/doc/gnu/6.53/Ps2epsi.htm"; class="urlextern" title="http://www.cs.wisc.edu/~ghost/doc/gnu/6.53/Ps2epsi.htm";  rel="nofollow">ps2epsi</a>. Call pstoedit with the option &ldquo;<code>-f pcb</code>&rdquo; to produce a valid pcb file that contains the graphics as tracks on layer 1. Load this file to pcb. The graphics will sit somewhere on the lower left of the view port. You may have to zoom out to get it on the screen.
  </p>
  
  <p>
  Import of external vector graphics is usefull if an irregular shape of the pcb is required. Use the cut buffer to copy the shape to your actual design. 
  </p>
  
  </div>
  <!-- SECTION [27280-28358] -->
  <h1><a name="auto_router" id="auto_router">Auto Router</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [28359-28384] -->
  <h2><a name="how_do_i_force_the_autorouter_to_only_put_traces_on_a_particular_layer" id="how_do_i_force_the_autorouter_to_only_put_traces_on_a_particular_layer">How do I force the autorouter to only put traces on a particular layer?</a></h2>
  <div class="level2">
  
  <p>
  Just unselect the layers you donâ??t want (usually green and blue) by clicking on the name of the layer. then press autoroute.
  </p>
  
  </div>
  <!-- SECTION [28385-28596] -->
  <h2><a name="how_do_i_force_the_autorouter_to_route_only_within_my_pcb_outline" id="how_do_i_force_the_autorouter_to_route_only_within_my_pcb_outline">How do I force the autorouter to route only within my pcb outline?</a></h2>
  <div class="level2">
  
  <p>
  You can have the autorouter work only within a given area by drawing a copper polygon conforming to your boardâ??s boundary and placing it in each layer youâ??re trying to autoroute. You can also use this trick to autoroute only with small areas. Of course, if you accidentally have a net touching the polygon, all routes will get shorted to that net.
  </p>
  
  </div>
  <!-- SECTION [28597-29028] -->
  <h2><a name="how_do_i_route_power_and_ground_planes_with_the_autorouter" id="how_do_i_route_power_and_ground_planes_with_the_autorouter">How do I route power and ground planes with the autorouter?</a></h2>
  <div class="level2">
  
  <p>
  Connect the polygon that will become your power planes to a net and the autorouter will figure it all out. You may need some trick polygon clearances to get power routing _and_ routing within a board outline.
  </p>
  
  </div>
  <!-- SECTION [29029-29310] -->
  <h2><a name="the_layout_produced_by_the_autorouter_is_inefficient" id="the_layout_produced_by_the_autorouter_is_inefficient">The layout produced by the autorouter is inefficient!</a></h2>
  <div class="level2">
  
  <p>
  This is a technological limitation of the current auto router. It is gridless and uses geometric rectangles only.
  </p>
  
  </div>
  <!-- SECTION [29311-29491] -->
  <h2><a name="the_layout_produced_by_the_autorouter_is_ugly" id="the_layout_produced_by_the_autorouter_is_ugly">The layout produced by the autorouter is ugly!</a></h2>
  <div class="level2">
  
  <p>
  You are more than welcome to contribute a topological autorouter.
  </p>
  
  </div>
  <!-- SECTION [29492-29617] -->
  <h1><a name="gerber_generation_and_file_i_o_issues" id="gerber_generation_and_file_i_o_issues">Gerber generation and file I/O issues</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [29618-29670] -->
  <h2><a name="how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker" id="how_do_i_make_a_board_outline_to_go_with_my_gerbers_to_the_board_maker">How do I make a board outline to go with my gerbers to the board maker?</a></h2>
  <div class="level2">
  
  <p>
  You can add an outline layer to your pcb projects. PCB interprets any layer called â??outlineâ?? (edit â??&gt; edit name of â??&gt; active layer) as though it is the absolute edge of the pcb. PCB prints gerber files that rigidly represent this.
  </p>
  
  <p>
  You can enter your outline layer thru PCBâ??s <acronym title="Graphical User Interface">GUI</acronym>. You just draw the lines of the board outline. You can generate boards of any shape this way.
  </p>
  
  <p>
  Itâ??s also possible to edit the native .pcb file format of your layout. I usually use Layer 8 for outlines: 
  </p>
  <pre class="code">Layer(8 &quot;outline&quot;)
  (
  	Line[x1 y1 x2 y2 1000 2000 0x00000000]
  	Line[x2 y2 x3 y3 1000 2000 0x00000000]
  	Line[x3 y3 x4 y4 1000 2000 0x00000000]
  	Line[x4 y4 x1 y1 1000 2000 0x00000000]
  	Line[&lt;more points go here for non-square boards&gt; 1000 2000 0x00000000]
  )</pre>
  
  </div>
  <!-- SECTION [29671-30517] -->
  <h2><a name="i_m_done_with_my_layout._how_should_i_check_my_design" id="i_m_done_with_my_layout._how_should_i_check_my_design">I'm done with my layout. How should I check my design?</a></h2>
  <div class="level2">
  
  <p>
  Besides running the DRC checker in PCB, it is essential to check your Gerber files. The gEDA Suite includes the program â??gerbvâ?? for this task. Here are some things to check/verify:
  </p>
  <ul>
  <li class="level1"><div class="li"> Check that all trace widths are the correct size. Also make sure your trace widths and metal-metal separations are above the minimum specified by your PCB vendor.</div>
  </li>
  <li class="level1"><div class="li"> Check that all hole diameters are called out at the correct size.</div>
  </li>
  <li class="level1"><div class="li"> Check that metal annular rings around holes/vias are large enough. The annular ring is the distance between the holeâ??s edge and the outer diameter of the metallization. The annular ring must be large enough to accomodate drill location + layer registration + other manufacturing inaccuracy. This information should be available from your PCB fabrication house; they normally publish the minimum annular ring requirements in their manufacturing rules document.</div>
  </li>
  <li class="level1"><div class="li"> Check that your antipads (clearance around holes/vias) are large enough. This information should be available from your PCB fabrication house; ask them for their manufacturing rules document.</div>
  </li>
  <li class="level1"><div class="li"> Verify that no soldermask or silkscreen overlays a copper pad or through-hole.</div>
  </li>
  <li class="level1"><div class="li"> On plane layers, verify that at least some vias connect to it (yes, I have seen a board where the entire ground plane was floating â?? not done in pcb btw)</div>
  </li>
  <li class="level1"><div class="li"> On plane layers, verify that at least some vias _donâ??t_ connect to it.</div>
  </li>
  <li class="level1"><div class="li"> Do a visual sanity check of all layers. Nothing detailed, just does it look approximately like you think it should.</div>
  </li>
  <li class="level1"><div class="li"> Are all layers negative/positive as they should be? Note that some fab houses want positive layers only. PCB will automatically create negative Gerbers on outer layer planes with no tracks. If you want an all-plane layer to be output as a positive layer, draw a single track somewhere in an unused part of the plane. This will trigger PCB to render that layer as a positive layer.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [30518-32494] -->
  <h1><a name="you_didn_t_answer_my_question._what_other_resources_exist_for_pcb_information" id="you_didn_t_answer_my_question._what_other_resources_exist_for_pcb_information">You didn't answer my question. What other resources exist for PCB information?</a></h1>
  <div class="level1">
  
  <p>
  <a href="http://www.luciani.org/geda/pcb/faq-pcb-footprint.html"; class="urlextern" title="http://www.luciani.org/geda/pcb/faq-pcb-footprint.html";  rel="nofollow">http://www.luciani.org/geda/pcb/faq-pcb-footprint.html</a><br/>
   <a href="http://pcb.sourceforge.net/faq.html"; class="urlextern" title="http://pcb.sourceforge.net/faq.html";  rel="nofollow">http://pcb.sourceforge.net/faq.html</a><br/>
   <a href="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Top"; class="urlextern" title="http://pcb.sourceforge.net/pcb-20060422/pcb.html#Top";  rel="nofollow">http://pcb.sourceforge.net/pcb-20060422/pcb.html#Top</a>
  </p>
  
  <p>
  You can get fast responses from the geda-user email list. If you havenâ??t found an answer to your question about PCB on this page, or in the other documentation, then post to the list! Note that you must subscribe to the geda-user e-mail list before you can post to the list. The gEDA e-mail lists, and their archives, are at: <a href="http://geda.seul.org/mailinglist/index.html"; class="urlextern" title="http://geda.seul.org/mailinglist/index.html";  rel="nofollow">http://geda.seul.org/mailinglist/index.html</a> 
  </p>
  
  </div>
  <!-- SECTION [32495-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_pcb_ug.html
  
  Index: geda_pcb_ug.html
  ===================================================================
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  1.1                  eda/geda/gaf/docs/wiki/geda_scg.html
  
  Index: geda_scg.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gaf_symbol_creation_document" class="toc">gEDA/gaf Symbol Creation Document</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#component_symbol_creation" class="toc">Component symbol creation</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#requirements" class="toc">Requirements</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#style" class="toc">Style</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#text" class="toc">Text</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#attributes" class="toc">Attributes</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#graphics" class="toc">Graphics</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#pins" class="toc">Pins</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#electrical" class="toc">Electrical</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#footprint_naming_conventions" class="toc">Footprint naming conventions</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#notes" class="toc">Notes</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#integrated_circuit_packages" class="toc">Integrated circuit packages</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#integrated_circuit_smt_packages" class="toc">Integrated circuit SMT packages</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#basic_semiconductors" class="toc">Basic semiconductors</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#basic_smt_semiconductors" class="toc">Basic SMT semiconductors</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#passive_components" class="toc">Passive components</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#passive_smt_components" class="toc">Passive SMT components</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#hints_and_tips" class="toc">Hints and Tips</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#example" class="toc">Example</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_revision_history" class="toc">Document Revision History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gaf_symbol_creation_document" id="geda_gaf_symbol_creation_document">gEDA/gaf Symbol Creation Document</a></h1>
  <div class="level1">
  
  <p>
  by: Ales V. Hvezda / July 6th, 2004
  </p>
  
  <p>
  The latest version of this document may be found at: <a href="http://www.someplace.come/some-page.html"; class="urlextern" title="http://www.someplace.come/some-page.html";  rel="nofollow">http://www.someplace.come/some-page.html</a>
  </p>
  
  <p>
  This document is released under the <a href="geda_gfdl.html" class="wikilink1" title="geda:gfdl">GNU Free Documentation License (GFDL)</a>.
  </p>
  
  </div>
  <!-- SECTION [1-270] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  This document describes the creation of component symbols, including style conventions, and hints/tips and things to look out for when drawing symbols for the gEDA/gaf system.
  </p>
  
  </div>
  <!-- SECTION [271-468] -->
  <h2><a name="component_symbol_creation" id="component_symbol_creation">Component symbol creation</a></h2>
  <div class="level2">
  
  <p>
  Component symbols (from here on known as &ldquo;symbols&rdquo;) are drawn using gschem just like drawing a schematic sheet. Here are the steps in a symbol in the gEDA/gaf system:<br/>
   1. Run gschem and find a blank page or run: gschem filename-1.sym<br/>
   2. Draw the symbol (see the style guide below for some conventions).<br/>
   3. Translate the symbol to the origin using Edit/Symbol Translate...<br/>
  
  </p>
  <ul>
  <li class="level1"><div class="li"> Zoom in at least one step.</div>
  </li>
  <li class="level1"><div class="li"> Make sure the snap is ON (this is critical).</div>
  </li>
  <li class="level1"><div class="li"> Make sure grid snap size is set to 100 (this is critical).</div>
  </li>
  <li class="level1"><div class="li"> Select &ldquo;Symbol Translate...&rdquo; or the press equivalent hotkey.</div>
  </li>
  <li class="level1"><div class="li"> Enter 0 into the entry field and press OK.<br/>
  </div>
  </li>
  </ul>
  
  <p>
  Translating the symbol to the origin is a required step. To translate a symbol elsewhere, enter a offset (in mils) which is a even multiple of 100. Make sure all pins are snapped to a 100 mil grid point.
  </p>
  
  <p>
  4. Save the symbol using Save or SaveAs... Here are some symbol naming conventions:<br/>
  
  </p>
  <ul>
  <li class="level1"><div class="li"> Symbols are named: symbolname-#.sym</div>
  </li>
  <li class="level1"><div class="li"> Symbols end with a .sym extension.</div>
  </li>
  <li class="level1"><div class="li"> Symbols have a -# where # is a number. Typically # is 1 but if there are multiple symbols for a device then this number simply increments.</div>
  </li>
  <li class="level1"><div class="li"> Symbol names are typically lowercase but letters which are part of a part number are uppercase.</div>
  </li>
  <li class="level1"><div class="li"> The above case rule can be broken if the filename looks incorrect or wrong.</div>
  </li>
  </ul>
  
  <p>
   5. Place the symbol in one of the directories specified by the componentlibrary keyword in the system-gafrc file. Once this is done, the symbol should be visible immediately and can be selected and placed with the &ldquo;Add/Select Component...&rdquo; menu item.
  </p>
  
  </div>
  <!-- SECTION [469-2088] -->
  <h2><a name="requirements" id="requirements">Requirements</a></h2>
  <div class="level2">
  
  <p>
  This section describes the various requirements which must be met in order to create a valid symbol which will display and netlist in the gEDA/gaf system. Most of the requirements center around having certain attributes attached or inside the symbol.<br/>
   Running gsymcheck will check that all of these requirements are met. gsymcheck will output fatal errors which are quite serious and must be corrected. gsymcheck will also output warnings on things which should be fixed but are not fatal.<br/>
   For more information on the attributes presented here, please see the Master Attribute Document.
  </p>
  <ul>
  <li class="level1"><div class="li"> device=DEVICENAME should be placed somewhere in the symbol and made invisible. device= is the device name and is required. Typically the devicename is in all caps (capital letters). This attribute should not be used as a label. Use a separate text object for the label. If the object is a graphic then device= should be set to none (device=none). It is no longer required to attach this attribute anything; just having it exist as device=DEVICENAME is good enough.</div>
  </li>
  <li class="level1"><div class="li"> graphical=1 should exist somewhere in a symbol which is purely graphical (such as a title block or decon symbol). Symbols which have this attribute have no electrical or circuit significance. Don&rsquo;t forget to set device=none.</div>
  </li>
  <li class="level1"><div class="li"> description=text should exist somewhere in the symbol. This attribute provides an one line description of the symbol.</div>
  </li>
  <li class="level1"><div class="li"> All pins should have a pair of attributes attached to them: pinseq=# and pinnumber=#. The first attribute, pinseq=# is just a sequence number and increments sequentially starting at 1. The second attribute pinnumber=# is the number of the pin. When a symbol is netlisted, the pin numbers are output in order of pin sequence. The pin number can be alphanumeric (i.e. like E or C).</div>
  </li>
  <li class="level1"><div class="li"> All pins should also have pinlabel=value attached to them. This attribute is the name or label of the pin (vs the pin number). This attribute is also used when a symbol is used in a hierarchical schematic. Please make this attribute green (instead of the default attribute yellow).</div>
  </li>
  <li class="level1"><div class="li"> All pins should also have pintype=value attached to them. This attribute describes the kind of a pin. Possible values are: in, out, io, oc, oe, pas, tp, tri, clk, pwr. Please see the Master Attribute Document for more info.</div>
  </li>
  <li class="level1"><div class="li"> If a component has multiple slots in a package (such as a 7400 (NAND) which has 4 NANDs per package) then you need a numslots=# attribute. The # is the number of slots the device has. numslots= should be exist somewhere in the symbol and made invisible. Additional slot related required attributes are described below.</div>
  </li>
  <li class="level1"><div class="li"> If a component has multiple slots in a physical package then you also need to include a slotdef=#:#,#,#... for every slot. The first # corresponds to the slot number. If a device has 4 slots then there should be slotdef=1:..., slotdef=2:..., slotdef=3:..., and slotdef=4:..., attributes existing somewhere in the symbol and made invisible. The subsequent # have a one-to-one correspondence to pinseq=# attributes and specify what corresponding pinnumber=# should be when that slot is set. See The attached 7400-1.sym as an example of how this should all work.</div>
  </li>
  <li class="level1"><div class="li"> It is recommended that all symbols which have slots have a slot=1 attribute inside the symbol.</div>
  </li>
  <li class="level1"><div class="li"> footprint=PACKAGENAME should exist somewhere in the symbol which might be used with the PCB netlister. PACKAGENAME is the PCB footprint or package type like DIP14 or DIP40. Please see the Footprint naming conventions chapter for further detail. See also the PCB documentation and gnetlist/docs/README.pcb for more info on this attribute.</div>
  </li>
  <li class="level1"><div class="li"> You should put a refdes=U? attribute inside the symbol. Make only the value visible and it will be promoted (attached to the outside of the symbol (so it can be edited) when the symbol is placed in a schematic.</div>
  </li>
  <li class="level1"><div class="li"> The label= attribute should not be attached anywhere in the symbol. It is obsolete.</div>
  </li>
  <li class="level1"><div class="li"> The name= attribute should not be attached anywhere in the symbol.</div>
  </li>
  <li class="level1"><div class="li"> The netname= attribute should not be attached anywhere in the symbol. It is only used in schematics.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2089-6229] -->
  <h2><a name="style" id="style">Style</a></h2>
  <div class="level2">
  
  <p>
  This section describes the style in which is used in the standard gEDA/gaf symbol library.
  </p>
  
  </div>
  <!-- SECTION [6230-6339] -->
  <h3><a name="text" id="text">Text</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> All Text labels should all be 10 pt in size.</div>
  </li>
  <li class="level1"><div class="li"> Text (labels not attributes) should be color number 9 (text | green).</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6340-6478] -->
  <h3><a name="attributes" id="attributes">Attributes</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Pin numbers (which are attributes) should all be 8 pt in size.</div>
  </li>
  <li class="level1"><div class="li"> Attached attributes should be yellow. The color is set automatically to yellow if the text item is attached.</div>
  </li>
  <li class="level1"><div class="li"> The only exception to this is pinlabel= attributes, those should be color number 9 (text | green). If every text item within a symbol is yellow, the symbol looks too yellow.</div>
  </li>
  <li class="level1"><div class="li"> Attributes can be attached to some part of the symbol. Toplevel attributes (like the device= or net= attributes) used to be required to be attached to something to be attributes, but now they just have to exist in the symbol file as name=value.</div>
  </li>
  <li class="level1"><div class="li">  Expanding a bit on the last sentence, as long as the text item has the format name=value, it is considered an attribute. Attributes inside a symbol do not have to be attached to anything. In order to see hidden attributes in gschem select Edit/Show/Hide Inv Text.</div>
  </li>
  <li class="level1"><div class="li"> There is a symbol content versioning system in libgeda which is based on the symversion= attribute. Please see the Master Attribute Document for more information on using this versioning scheme.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6479-7575] -->
  <h3><a name="graphics" id="graphics">Graphics</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Lines, boxes, arcs, and any other graphics should be color number 3 (graphic | green).</div>
  </li>
  <li class="level1"><div class="li"> Polarity bubbles should be color number 6 (logic bubble | cyan)</div>
  </li>
  <li class="level1"><div class="li"> If you are unsure on how to make a new symbol look or how big to make a new symbol, look at the existing symbols to get a feel for the appropriate appearance and size.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [7576-7926] -->
  <h3><a name="pins" id="pins">Pins</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Pins should all be 300 mils (3 grid spaces) long.</div>
  </li>
  <li class="level1"><div class="li"> For pins which are next to a logic bubble, make the pins 200 mils (2 grid spaces) long and then make the logic bubble 100 mils in diameter. In order to draw a 100 mil diameter circle, you will need to change the snap spacing to 50.</div>
  </li>
  <li class="level1"><div class="li"> A pin has two ends: one end has a red endpoint and one end that does not. The red endpoint is where nets can be connected. You can either rotate the pin so that this active end is in the right place or manually edit the symbol file changing the &ldquo;whichend&rdquo; parameter on the pin object. See the File Format document for more info.</div>
  </li>
  <li class="level1"><div class="li"> Be that all endpoints of pins which are meant to be connected to are on the 100 mil grid. The endpoint which is not active can be off the grid if necessary.</div>
  </li>
  <li class="level1"><div class="li"> Pins should be color number 1 (pins | white).</div>
  </li>
  <li class="level1"><div class="li"> Leave 400 mils (4 grid spaces) between (vertically) pins, unless you are drawing a special symbol, then just try to make it look good.</div>
  </li>
  <li class="level1"><div class="li"> Pin number attributes should be 50 mils above (or below; which ever makes the most sense) the pin which they are attached to.</div>
  </li>
  <li class="level1"><div class="li"> Input pins belong on the left and output pins belong on the right of the symbol.</div>
  </li>
  <li class="level1"><div class="li"> Please do not mix inputs and outputs on the same side of the symbol, unless absolutely necessary.</div>
  </li>
  <li class="level1"><div class="li"> You can have pins on the top or bottom of a symbol.</div>
  </li>
  <li class="level1"><div class="li"> The order for rows of pins (buses) should be LSB (least significant bit) to MSB (most significant bit). When drawing pins which are part of a bus, make sure the LSB of the bus is at the top (or for pins on top/bottom of a symbol, left of the rest of the other pins). Look at 74/74181-1.sym for a correct example of this order (A0 on top through A3 and B0 on top through B3). Violating this rule will make connecting buses much more diffcult.</div>
  </li>
  <li class="level1"><div class="li"> When placing pins on logic gates, be sure to place the smallest pin numbers toward the top (or left) and then increment going down (or across).</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [7927-9882] -->
  <h3><a name="electrical" id="electrical">Electrical</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Do not draw power and ground pins. That information will be conveyed using attributes (see the netattrib document).</div>
  </li>
  <li class="level1"><div class="li"> The above rule can be broken if necessary, but keep in mind most of the standard library does not have power pins showing.</div>
  </li>
  <li class="level1"><div class="li"> Keep in mind, symbols are supposed to be symbolic, they do not represent the physical package that the device comes in.</div>
  </li>
  <li class="level1"><div class="li"> There is some disagreement on above, so this is okay too: Arrange the pins on a symbol logically so that they promote an uncluttered schematic. Note that this is frequently not the same pin arrangement as the physical device.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [9883-10505] -->
  <h2><a name="footprint_naming_conventions" id="footprint_naming_conventions">Footprint naming conventions</a></h2>
  <div class="level2">
  
  <p>
  This section describes the conventions for naming of footprints used in gEDA/gaf.<br/>
   The purpose of the naming convention is to establish a standard to maintain the same naming convention through the different phases of the CAD chain. This helps in ensuring that the collaborative effort of gEDA/gaf is not lost.
  </p>
  
  </div>
  <!-- SECTION [10506-10859] -->
  <h3><a name="notes" id="notes">Notes</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Unless otherwise noted, numerical pin names will be used, starting from 1.</div>
  </li>
  <li class="level1"><div class="li"> n is for the pin count.</div>
  </li>
  <li class="level1"><div class="li"> m is for the pin spacing in mils.</div>
  </li>
  <li class="level1"><div class="li"> x is for the x dimension of the package (excluding pins). In particular this is used for the QFP package family.</div>
  </li>
  <li class="level1"><div class="li"> SMT means surface mount, other components are through-hole.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [10860-11202] -->
  <h3><a name="integrated_circuit_packages" id="integrated_circuit_packages">Integrated circuit packages</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Dual in line packages with up to 22 100 mil spaced pins and 300 mil row spacing are called DIPn.</div>
  </li>
  <li class="level1"><div class="li"> Dual in line packages with 24 or more 100 mil spaced pins and 300 mil row spacing are called DIPnN.</div>
  </li>
  <li class="level1"><div class="li"> Dual in line packages with 100 mil spaced pins and 400 mil row spacing are called DIPnH.</div>
  </li>
  <li class="level1"><div class="li"> Dual in line packages with 24 or more 100 mil spaced pins and 600 mil row spacing are called DIPn.</div>
  </li>
  <li class="level1"><div class="li"> Shrink dual in line packages with up to 24 70 mil spaced pins and 300 mil row spacing are called SDIPn.</div>
  </li>
  <li class="level1"><div class="li"> Shrink dual in line packages with more than 24 70 mil spaced pins and 400 mil row spacing are called SDIPn.</div>
  </li>
  <li class="level1"><div class="li"> Single in line packages with 100 mil spaced pins are called SIPnN. See also JUMPER, below.</div>
  </li>
  <li class="level1"><div class="li"> Zig-zag in-line package are called ZIPn.</div>
  </li>
  <li class="level1"><div class="li"> Plastic leadless chip carrier with pin socket are called PLCCnX.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [11203-12071] -->
  <h3><a name="integrated_circuit_smt_packages" id="integrated_circuit_smt_packages">Integrated circuit SMT packages</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Small outline SMT packages with up to 16 50 mil spaced pins and 150 mil total width are called SOn.</div>
  </li>
  <li class="level1"><div class="li"> Small outline SMT packages with more than 16 50 mil spaced pins and 150 mil total width are called SOnN.</div>
  </li>
  <li class="level1"><div class="li"> Small outline SMT packages with 50 mil spaced pins and 200 mil total width are called SOnM.</div>
  </li>
  <li class="level1"><div class="li"> Small outline SMT packages with up to 20 50 mil spaced pins and 300 mil total width are called SOnW.</div>
  </li>
  <li class="level1"><div class="li"> Small outline SMT packages with more than 20 50 mil spaced pins and 300 mil total width are called SOn.</div>
  </li>
  <li class="level1"><div class="li"> Small outline SMT packages with 44 or more 50 mil spaced pins and 525 mil total width are called SOn.</div>
  </li>
  <li class="level1"><div class="li"> Metric shrink small outline SMT packages with 0.65 mm spaced pins and 323 mil total width are called MSSOPn. NOTE: To be confirmed.</div>
  </li>
  <li class="level1"><div class="li"> Metric shrink small outline SMT packages with up to 44 0.65 mm spaced pins and 420 mil total width are called MSSOPnW.</div>
  </li>
  <li class="level1"><div class="li"> Metric shrink small outline SMT packages with over 44 0.65 mm spaced pins and 545 mil total width are called MSSOPnW.</div>
  </li>
  <li class="level1"><div class="li"> Shrink small outline SMT packages with 25 mil spaced pins and 420 mil total width are called SSOPnW.</div>
  </li>
  <li class="level1"><div class="li"> Quarter size small outline SMT packages with 25 mil spaced pins and 244 mil total width are called SSOPn.</div>
  </li>
  <li class="level1"><div class="li"> Thin small outline SMT packages with 21.65 mil spaced pins and 535 mil total width are called TSOPn.</div>
  </li>
  <li class="level1"><div class="li"> Thin small outline SMT packages with 20 mil spaced pins and 795 mil total width are called TSOPnA.</div>
  </li>
  <li class="level1"><div class="li"> Thin small outline SMT packages with 20 mil spaced pins and 559 mil total width are called TSOPnB.</div>
  </li>
  <li class="level1"><div class="li"> Thin shrink small outline SMT packages with up to 28 26 mil spaced pins and 260 mil total width are called TSSOPn.</div>
  </li>
  <li class="level1"><div class="li"> Thin shrink small outline SMT packages with over 28 20 mil spaced pins and 319 mil total width are called TSSOPn.</div>
  </li>
  <li class="level1"><div class="li"> Ultra Super Mini SMT packages with up to 16 0.5 mm spaced pins are called USn.</div>
  </li>
  <li class="level1"><div class="li"> Plastic leadless chip carrier SMT are called PLCCn.</div>
  </li>
  <li class="level1"><div class="li"> Square quad-side at pack SMT are called QFPn x.</div>
  </li>
  <li class="level1"><div class="li"> Rectangular quad-side at pack SMT are called QFPn R.</div>
  </li>
  <li class="level1"><div class="li"> Square low profile quad-side at pack SMT are called LQFPn x.</div>
  </li>
  <li class="level1"><div class="li"> Square thin quad-side at pack SMT are called TQFPn x.</div>
  </li>
  <li class="level1"><div class="li"> Square Quad-side at no-lead SMT without exposed paddle (back side contact) are called QFNn x. Pin count is n and package size is x mm.</div>
  </li>
  <li class="level1"><div class="li"> Square Quad-side at no-lead SMT with exposed paddle (back side contact) are called QFNn x EP. Pin count is n and package size is x mm.</div>
  </li>
  <li class="level1"><div class="li"> Thin profile square Quad-side at no-lead SMT without exposed paddle (back side contact) are called TQFNn x. Pin count is n and package size is x mm.</div>
  </li>
  <li class="level1"><div class="li"> Thin profile square Quad-side at no-lead SMT with exposed paddle (back side contact) are called TQFNn x EP. Pin count is n and package size is x mm.</div>
  </li>
  <li class="level1"><div class="li"> Dual in line style crystal oscillators are OSC8 and OSC14.</div>
  </li>
  <li class="level1"><div class="li"> 5 pin SOT SMT packages are SOT25 and SOT325.</div>
  </li>
  <li class="level1"><div class="li"> 6 pin SOT SMT packages are SOT26 and SOT326.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [12072-15002] -->
  <h3><a name="basic_semiconductors" id="basic_semiconductors">Basic semiconductors</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Axial diodes are called ALFm. Pin 1 is the cathode.</div>
  </li>
  <li class="level1"><div class="li"> Conventional through hole LED is LED3 and LED5 for 3 and 5 mm respectively. Pin 1 is plus. NOTE: Should probably be changed to be in line with diode convention.</div>
  </li>
  <li class="level1"><div class="li"> TO transistors are TO5, TO92, TO126, TO220 etc. Suxes may apply, e.g. TO126W is for wide, TO126S is for standing, TO126SW is for standing, wide.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [15003-15405] -->
  <h3><a name="basic_smt_semiconductors" id="basic_smt_semiconductors">Basic SMT semiconductors</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> SOD diode SMT packages use their standard package name, e.g. SOD80, SOD87, SOD106A, SOD110. There are also SOD123, SOD323 with narrow pads.</div>
  </li>
  <li class="level1"><div class="li"> SOT transistor SMT packages use their standard package name, e.g. SOT23, SOT323. There is also an SC90.</div>
  </li>
  <li class="level1"><div class="li"> SOT transistor SMT packages with numbering as for diodes (pin 1 is cathode, pin 2 anode) are SOT23D, SOT323D.</div>
  </li>
  <li class="level1"><div class="li"> 4 pin SOT SMT packages are SOT89, SOT143, SOT223.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [15406-15861] -->
  <h3><a name="passive_components" id="passive_components">Passive components</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Axial non-polar components (typically resistor, capacitor) are called ACYm.</div>
  </li>
  <li class="level1"><div class="li"> Bottom lead (radial) non-polar circular component (typically capacitor) is RCYm.</div>
  </li>
  <li class="level1"><div class="li"> Bottom lead non-polar rectangular component (typically capacitor) is BREm.</div>
  </li>
  <li class="level1"><div class="li"> A standard crystal is HC49, or other HC designations as required.</div>
  </li>
  <li class="level1"><div class="li"> Single row 100 mil pin spacing jumpers are JUMPERn. The main difference compared to single in line package is the hole size.</div>
  </li>
  <li class="level1"><div class="li"> Dual row 100 mil spacing headers with DIP pin numbering are HEADERn 1. Note that n is an even number.</div>
  </li>
  <li class="level1"><div class="li"> Dual row 100 mil spacing headers with ribbon cable numbering are HEADERn 2. Note that n is an even number.</div>
  </li>
  <li class="level1"><div class="li"> Angled full header connectors with latches are DIN41651 n.</div>
  </li>
  <li class="level1"><div class="li"> Standing full header connectors with latches are DIN41651 nS.</div>
  </li>
  <li class="level1"><div class="li"> DSUB connectors female are DBnF.</div>
  </li>
  <li class="level1"><div class="li"> DSUB connectors male are DBnM.</div>
  </li>
  <li class="level1"><div class="li"> Female DIN card-to-card connectors are DIN41612CnF. Add S suffix for standing.</div>
  </li>
  <li class="level1"><div class="li"> Male DIN card-to-card connectors are DIN41612CnM. Add S suffix for standing.</div>
  </li>
  <li class="level1"><div class="li"> AMP modular RJ connectors with screen are RJ11, RJ12 and RJ45.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [15862-16983] -->
  <h3><a name="passive_smt_components" id="passive_smt_components">Passive SMT components</a></h3>
  <div class="level3">
  <ul>
  <li class="level1"><div class="li"> Standard SMT resistors, inductors, capacitors etc are 0201, 0402, 0603, 0805, 1206, 1210, 1806, 1812, 1825, 2020, 2706.</div>
  </li>
  <li class="level1"><div class="li"> Tantalum SMT capacitors are EIA3216, EIA3528, EIA6032, and EIA7343. Pin 1 is plus.</div>
  </li>
  <li class="level1"><div class="li"> SMT electrolytics are designated by can diameter in 1/10 mm: SME33, SME43, SME53, SME66, SME84, SME104.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [16984-17336] -->
  <h2><a name="hints_and_tips" id="hints_and_tips">Hints and Tips</a></h2>
  <div class="level2">
  
  <p>
  This section describes some hints and tips which will make your symbol creation experience easier.<br/>
  
  </p>
  <ul>
  <li class="level1"><div class="li"> Avoid drawing things off of the grid. If you do, you cannot move the object(s) using the move command (if the grid is on) since the object will be snapped to the grid. [This was an old bug, which I think has been fixed, but avoid doing this anyway]. Use the symbol translate command instead (or move the object with grid snap off)</div>
  </li>
  <li class="level1"><div class="li"> If you need a finer grid then use Options/Snap Grid Spacing... to set a finer grid snap spacing. Just remember to set this back to 100 once you are ready to translate the symbol to the origin.</div>
  </li>
  <li class="level1"><div class="li"> If you want to translate a symbol from the origin to elsewhere, then use the &ldquo;Symbol translate&rdquo; command and enter a non zero number. Make sure this number is a multiple of 100 (ie 1000, or 1100).</div>
  </li>
  <li class="level1"><div class="li"> Pins MUST be snapped on the 100 spaced grid (at least the end which will have nets connected to it).</div>
  </li>
  <li class="level1"><div class="li"> Pins MUST be snapped on the 100 spaced grid (at least the end which will have nets connected to it). Yes this is line a duplicate. I can&rsquo;t stress this point enough.</div>
  </li>
  <li class="level1"><div class="li"> Remember that pins are special objects; if you want to add a pin, make sure it is a pin and not a line or net. Use the Add/Pin command to place a pin.</div>
  </li>
  <li class="level1"><div class="li"> Don&rsquo;t include nets or buses inside symbols. That is not supported and doesn&rsquo;t make much sense anyway.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [17337-18732] -->
  <h2><a name="example" id="example">Example</a></h2>
  <div class="level2">
  
  <p>
  This section provides a simple example which tries to follow all of the above rules. This symbol is of a 7400 (NAND gate).<br/>
  
  </p>
  
  <p>
  <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">v 20020825
  L 300 200 300 800 3 0 0 0 -1 -1
  T 300 0 9 8 1 0 0 0
  7400
  L 300 800 700 800 3 0 0 0 -1 -1
  T 500 900 5 10 0 0 0 0
  device=7400
  T 500 1100 5 10 0 0 0 0
  slot=1
  T 500 1300 5 10 0 0 0 0
  numslots=4
  T 500 1500 5 10 0 0 0 0
  slotdef=1:1,2,3
  T 500 1700 5 10 0 0 0 0
  slotdef=2:4,5,6
  T 500 1900 5 10 0 0 0 0
  slotdef=3:9,10,8
  T 500 2100 5 10 0 0 0 0
  slotdef=4:12,13,11
  L 300 200 700 200 3 0 0 0 -1 -1
  A 700 500 300 270 180 3 0 0 0 -1 -1
  V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
  P 1100 500 1300 500 1
  {
  T 1100 550 5 8 1 1 0 0
  pinnumber=3
  T 1100 450 5 8 0 1 0 2
  pinseq=3
  T 950 500 9 8 0 1 0 6
  pinlabel=Y
  T 950 500 5 8 0 1 0 8
  pintype=out
  }
  P 300 300 0 300 1
  {
  T 200 350 5 8 1 1 0 6
  pinnumber=2
  T 200 250 5 8 0 1 0 8
  pinseq=2
  T 350 300 9 8 0 1 0 0
  pinlabel=B
  T 350 300 5 8 0 1 0 2
  pintype=in
  }
  P 300 700 0 700 1
  {
  T 200 750 5 8 1 1 0 6
  pinnumber=1
  T 200 650 5 8 0 1 0 8
  pinseq=1
  T 350 700 9 8 0 1 0 0
  pinlabel=A
  T 350 700 5 8 0 1 0 2
  pintype=in
  }
  T 300 900 8 10 1 1 0 0
  refdes=U?
  T 500 2250 5 10 0 0 0 0
  footprint=DIP14
  T 500 2450 5 10 0 0 0 0
  description=4 NAND gates with 2 inputs
  T 500 2650 5 10 0 0 0 0
  documentation=http://www-s.ti.com/sc/ds/sn74ls00.pdf
  T 500 2850 5 10 0 0 0 0
  net=Vcc:14
  T 500 3050 5 10 0 0 0 0
  net=GND:7</font></pre>
  </p>
  
  <p>
  This example produces the following (using gschem):
  </p>
  
  <p>
  NOTE: This version of Dokuwiki does not support image file references. The Dokuwiki software will be updated shortly.
  </p>
  
  <p>
  This is the same symbol with all the hidden text visible (via Edit/Show/Hide Inv Text):
  </p>
  
  <p>
  NOTE: This version of Dokuwiki does not support image file references. The Dokuwiki software will be updated shortly.
  </p>
  
  </div>
  <!-- SECTION [18733-20500] -->
  <h2><a name="document_revision_history" id="document_revision_history">Document Revision History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td> September 14th, 2002</td><td>Created symbol.tex from symbols.html </td>
  	</tr>
  	<tr>
  		<td> October 31st, 2002</td><td>Fixed bad example symbol </td>
  	</tr>
  	<tr>
  		<td> February 11th, 2003</td><td>Footprint naming conventions added </td>
  	</tr>
  	<tr>
  		<td> September 27th, 2003</td><td>Applied Dan McMahill&rsquo;s QFP and QFN patch </td>
  	</tr>
  	<tr>
  		<td> July 6th, 2004</td><td>Added a bunch more details/hints to the pin section </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [20501-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_sdb_howto.html
  
  Index: geda_sdb_howto.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#spice_on_geda_howto" class="toc">SPICE on gEDA HOWTO</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#introduction" class="toc">Introduction</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#spice-sdb_netlister_installation_and_configuration" class="toc">Spice-sdb netlister installation and configuration</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#design_simulation_flow_summary" class="toc">Design/simulation flow summary</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#preliminary_notes_about_symbols_and_spice_model_files" class="toc">Preliminary notes about symbols and SPICE model files</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#symbol_creation_for_spice_netlisting" class="toc">Symbol creation for SPICE netlisting.</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#spice_file_configuration" class="toc">SPICE file configuration</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#schematic_capture" class="toc">Schematic capture</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#gschem_attributes_for_spice_netlisting" class="toc">Gschem attributes for spice netlisting</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#handling_hierarchical_models" class="toc">Handling hierarchical models</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#spice_netlist_generation" class="toc">SPICE netlist generation</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#creating_the_netlist" class="toc">Creating the netlist</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#common_netlisting_problems" class="toc">Common netlisting problems</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#spice_simulation" class="toc">SPICE simulation</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#ltspice" class="toc">LTSpice</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#ngspice_and_tclspice" class="toc">Ngspice and tclspice</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#appendix" class="toc">Appendix</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#component_attribute_summary" class="toc">Component attribute summary</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#valid_type_values" class="toc">Valid &quot;type&quot; values</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_history" class="toc">Document History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="spice_on_geda_howto" id="spice_on_geda_howto">SPICE on gEDA HOWTO</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-34] -->
  <h2><a name="introduction" id="introduction">Introduction</a></h2>
  <div class="level2">
  
  <p>
  The purpose of this document is to explain how to use the gEDA tools (running on Linux) to perform SPICE simulations. In particular, this HOWTO documents the usage of spice-sdb, which is an advanced backend for the gEDA netlister (gnetlist) used to create SPICE netlists. This HOWTO also provides advice about using LTSpice and/or ngspice to simulate a circuit netlisted with spice-sdb. I assume that you are already familiar with electronic design, the mechanics of schematic capture using EDA tools, and SPICE simulation in general. I also assume that you are reasonably familiar with the Linux operating system and its development environment.   
  </p>
  
  </div>
  <!-- SECTION [35-708] -->
  <h3><a name="overview" id="overview">Overview</a></h3>
  <div class="level3">
  
  <p>
  From the top level, SPICE simulation in gEDA proceeds via the following steps:
  </p>
  <ol>
  <li class="level1"><div class="li"> Creation and gathering of schematic symbols and SPICE model files. Oftentimes, the SPICE model files are obtained from the component vendor.</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture using symbols and SPICE models created in step 1.</div>
  </li>
  <li class="level1"><div class="li"> Netlist generation from the schematic created in step 2.</div>
  </li>
  <li class="level1"><div class="li"> SPICE simulation of the circuit described by the netlist created in step 3.</div>
  </li>
  </ol>
  
  <p>
   To create a SPICE netlist, the netlister (gnetlist) iterates through the entire schematic and looks at several parts of each component&rsquo;s symbol in order to create a blob of SPICE code. In general, each component can generate one or more lines of SPICE code. Component information needed by the netlister is held in two places:
  </p>
  <ol>
  <li class="level1"><div class="li"> The symbol itself, in the &ldquo;device&rdquo; attribute, which is attached when the symbol is created, and is typically accessed through the symbol editor.</div>
  </li>
  <li class="level1"><div class="li"> In attributes manually attached to the component during schematic capture using gschem.</div>
  </li>
  </ol>
  
  <p>
   Since there are two places the netlister looks for information, you must make sure that the required information is available in both places.
  </p>
  
  </div>
  <!-- SECTION [709-1877] -->
  <h3><a name="spice-sdb_netlister_installation_and_configuration" id="spice-sdb_netlister_installation_and_configuration">Spice-sdb netlister installation and configuration</a></h3>
  <div class="level3">
  
  <p>
  This document was originally written around gEDA/gaf 20030223, and the SPICE netlister spice-SDB. Starting with gEDA/gaf 20030525, my netlister was incorporated into the main gEDA distribution, and renamed spice-sdb (lower case sdb). <strong>For smoothest operation, you are best off just downloading and installing the latest version of gEDA.</strong> However, if you have a gEDA version predating 20030525, and you want to hack, you can download and install spice-SDB using the instructions provided on <a href="http://www.brorson.com/gEDA/SPICE/SPICEonLinux.html"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/SPICEonLinux.html";  rel="nofollow">http://www.brorson.com/gEDA/SPICE/SPICEonLinux.html</a>. In any event, it&rsquo;s a good idea to make sure that the file gnet-spice-sdb.scm is present in your scheme directory (usually <strong><code>${prefix}/geda/share/gEDA/scheme</code></strong>) if you are interested in performing SPICE simulations with gEDA as described in this HOWTO.
  </p>
  
  </div>
  <!-- SECTION [1878-2744] -->
  <h3><a name="design_simulation_flow_summary" id="design_simulation_flow_summary">Design/simulation flow summary</a></h3>
  <div class="level3">
  
  <p>
  The detailed steps required to create a circuit and simulate it with gEDA look like this:
  </p>
  <ol>
  <li class="level1"><div class="li"> Schematic symbol creation with correct &ldquo;device&rdquo; attribute. (Usually, the symbols have already been created with the correct &ldquo;device&rdquo; attribute, but if you are having problems, it doesn&rsquo;t hurt to check them.)</div>
  </li>
  <li class="level1"><div class="li"> Schematic capture using gschem.</div>
  </li>
  <li class="level1"><div class="li"> Assignment of SPICE attributes (value, model, file, type, etc.) to components using gschem.</div>
  </li>
  <li class="level1"><div class="li"> Assignment of <strong><code>refdes</code></strong> using e.g. refdes_renum.</div>
  </li>
  <li class="level1"><div class="li"> Creation of netlist using &ldquo;gnetlist -g spice-sdb&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> Check netlist for correctness (manually open and inspect netlist).</div>
  </li>
  <li class="level1"><div class="li"> Run spice using a simulator such as LTSpice or ngspice.</div>
  </li>
  <li class="level1"><div class="li"> Plot/analyze results (often plotting/analysis tools are incorporated in the simulator).</div>
  </li>
  </ol>
  
  <p>
   The purpose of this HOWTO is to provide the detailed understanding necessary to successfully navigate this process.
  </p>
  
  </div>
  <!-- SECTION [2745-3673] -->
  <h2><a name="preliminary_notes_about_symbols_and_spice_model_files" id="preliminary_notes_about_symbols_and_spice_model_files">Preliminary notes about symbols and SPICE model files</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [3674-3739] -->
  <h3><a name="symbol_creation_for_spice_netlisting" id="symbol_creation_for_spice_netlisting">Symbol creation for SPICE netlisting.</a></h3>
  <div class="level3">
  
  <p>
  The SPICE netlister recognizes a particular symbol in two ways:
  </p>
  <ol>
  <li class="level1"><div class="li"> The symbol&rsquo;s &ldquo;device&rdquo; attribute</div>
  </li>
  <li class="level1"><div class="li"> The symbol&rsquo;s <strong><code>refdes</code></strong>. Both of these attributes are attached to the symbol when the symbol is created.</div>
  </li>
  </ol>
  
  <p>
   Each symbol has a <strong><code>device</code></strong> attribute attached to it. The <strong><code>device</code></strong> attribute is the first thing the netlister examines when processing the symbol. There are a number of devices which are native to the netlister, meaning that the netlister knows exactly how to deal with these types of devices. Native device types include RESISTOR, CAPACITOR, NPN_TRANSISTOR, etc. The entire list of native devices is present in the <a href="#appendix" title="geda:sdb_howto &crarr;" class="wikilink1">Appendix</a>.<br/>
   The <strong><code>device</code></strong> attribute is hidden during normal use of gschem. Most often, the symbol&rsquo;s creator has already given the symbol the correct <strong><code>device</code></strong> attribute. However, because the <strong><code>device</code></strong> attribute is hidden from the ordinary user, it can sometimes cause problems with SPICE netlist creation when it is set to an unexpected value. To view the <strong><code>device</code></strong> attribute, go into the symbol editor (select the symbol to edit, and do &ldquo;Hierarchy&rdquo; &rarr; &ldquo;down symbol&rdquo;), and turn on invisible attributes (Edit &rarr; show/hide inv text). If the <strong><code>device</code></strong> attribute is incorrect, you may change it by editing the symbol itself using a text editor.<br/>
   If a symbol is not native (i.e. the netlister doesn&rsquo;t recognize it as a built-in type), the netlister relies upon the first letter of the <strong><code>refdes</code></strong> to determine how to process the symbol. The <strong><code>refdes</code></strong> prefix is also built into the symbol when it is created. Example <strong><code>refdes</code></strong> prefixes are R for resistors, C for capacitors, Q for transistors, etc. <strong><code>refdes</code></strong> prefixes correct for SPICE are listed in the <a href="#appendix" title="geda:sdb_howto &crarr;" class="wikilink1">Appendix</a>. Note that relying upon the <strong><code>refdes</code></strong> to identify the component for SPICE is not foolproof &ndash; for example, the netlister cannot distinguish between NPN and PNP transistors based upon the <strong><code>refdes</code></strong>. Therefore, it is always best to use a native &ldquo;device&rdquo; in your symbols.
  </p>
  
  </div>
  <!-- SECTION [3740-5819] -->
  <h3><a name="spice_file_configuration" id="spice_file_configuration">SPICE file configuration</a></h3>
  <div class="level3">
  
  <p>
  Files holding complicated SPICE models or other SPICE code may be incorporated into the final SPICE netlist by including appropriate symbols into the schematic. SPICE model files are usually obtained from component vendors. Dealing with these files is straightforward. However, some issues should be kept in mind when preparing models for use during schematic capture:
  </p>
  <ul>
  <li class="level1"><div class="li"> It is usually prudent to place these files into a dedicated directory distinct from the symbol directories.</div>
  </li>
  <li class="level1"><div class="li"> Make sure that the SPICE files pin assignments correctly correspond to the pins as defined in the component&rsquo;s symbol.</div>
  </li>
  <li class="level1"><div class="li"> Make sure that the last character in a SPICE model file is a carriage return. If no carriage return exists, then the next component listed in the netlist may be placed on the same line as the last line of the SPICE model file.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5820-6689] -->
  <h2><a name="schematic_capture" id="schematic_capture">Schematic capture</a></h2>
  <div class="level2">
  
  <p>
  Schematic capture is the process by which one uses a special-purpose drawing program to draw a schematic diagram of the circuit under design. In the gEDA environment, the schematic capture program is called &ldquo;gschem&rdquo;. I assume you already know how to use gschem. For the purposes of creating SPICE netlists, you must use gschem to attach attributes to components, and possibly also incorporate other SPICE directives into your netlist. After you are done with schematic capture, you create the SPICE netlist by running gEDA&rsquo;s netlister &ldquo;gnetlist&rdquo; on your design.
  </p>
  
  </div>
  <!-- SECTION [6690-7282] -->
  <h3><a name="gschem_attributes_for_spice_netlisting" id="gschem_attributes_for_spice_netlisting">Gschem attributes for spice netlisting</a></h3>
  <div class="level3">
  
  <p>
  There are several ways that spice attributes may be associated with a component using gschem. The way you choose to do this depends upon many factors, including the type of component, and the size and format of the SPICE model.
  </p>
  
  </div>
  
  <h4><a name="component_attributes_and_meanings" id="component_attributes_and_meanings">Component attributes and meanings</a></h4>
  <div class="level4">
  
  <p>
  The following attributes are meaningful for SPICE netlisting, and may be attached from within gschem: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>The reference designator of the component. Valid values depend upon the component type and are given in the appendix.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>For passives, this is the component value. For actives, this is the type (model no) of the component (e.g. 2N3904, uA741). When a model for an active is instantiated separately from the component itself, the &ldquo;value&rdquo; attribute holds the name of the spice model.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model</code></strong></td><td>This holds a one line spice model for the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>file</code></strong></td><td>This holds the name of a file. Typically, this is a file holding e.g. a SPICE .MODEL, .SUBCKT, or other SPICE code.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model-name</code></strong></td><td>This holds the name of the spice model referred to in a .MODEL or .SUBCKT statement. &ldquo;model-name&rdquo; is mainly used to identify the spice model name in the symbol &ldquo;spice-model-1.sym&rdquo;. Active components should call out this name in the &ldquo;device&rdquo; attribute to associate the component with its particular spice model or subcircuit.</td>
  	</tr>
  	<tr>
  		<td><strong><code>type</code></strong></td><td>This specifies the type of component and is used by spice when interpreting the model parameters. Valid values depend upon the device being modeled.</td>
  	</tr>
  </table>
  <br />
  
  </div>
  
  <h4><a name="refdes_conventions" id="refdes_conventions">refdes conventions</a></h4>
  <div class="level4">
  
  <p>
  As a prerequisite to handling SPICE-related attributes, the SPICE netlister requires that all components must have a refdes attached to them. The refdes may be attached either by hand (which is laborious), or using the program refdes_renum included in the gEDA distribution.<br/>
   Note that the first letter of the refdes must correspond to the appropriate letter for spice simulation. The refdes convention is given in the <a href="#appendix" title="geda:sdb_howto &crarr;" class="wikilink1">Appendix</a>.
  </p>
  
  </div>
  
  <h4><a name="passives" id="passives">Passives</a></h4>
  <div class="level4">
  
  </div>
  
  <h5><a name="basic_passives" id="basic_passives">Basic passives</a></h5>
  <div class="level5">
  
  <p>
  The most basic components which one encounters in spice are passive components like resistors and capacitors which have numeric values, but no other modeling attributes. In this case the following attributes must be filled in: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>The correct <strong><code>refdes</code></strong> for the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>For passives, this is the numeric value of the component (e.g. 100pF). For actives, this attribute may be filled in, but if no model attribute is available elsewhere in the schematic, the value is not used (in SPICE netlisting, anyway).</td>
  	</tr>
  </table>
  <br />
  
  <p>
   If only a <strong><code>refdes</code></strong> and value attribute are encountered, the netlister will write a single line into the output file.<br/>
   Example resistor: 
  </p>
  <pre class="code">refdes = R2
  value = 220
  SPICE line generated: R2 0 4 220</pre>
  
  <p>
  Note that &ldquo;0&rdquo; and &ldquo;4&rdquo; correspond to the net nodes connected to the component, and are generated automatically by gnetlist.<br/>
   Example capacitor: 
  </p>
  <pre class="code">refdes = C22
  value = 1UF
  SPICE line generated: C22 4 23 1UF</pre>
  
  </div>
  
  <h5><a name="passives_with_additional_attributes" id="passives_with_additional_attributes">Passives with additional attributes</a></h5>
  <div class="level5">
  
  <p>
  Oftentimes, passive components have additional attributes attached to them for spice simulation. Examples of such attributes are temperature coefficients (for resistors) and initial conditions (for reactive components). These additional components may be incorporated into the SPICE file by simply attaching them to the component&rsquo;s &ldquo;model&rdquo; attribute. Specifically, the required attributes are: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>Correct component <strong><code>refdes</code></strong>.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>Numerical component value, as always.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model</code></strong></td><td>One line string holding additional parameters, formatted as a valid SPICE string.</td>
  	</tr>
  </table>
  <br />
  
  <p>
   This string is placed after the component value in the line generated by gnetlist. Therefore, it is important to format the string placed in the <strong><code>model</code></strong> line to be valid SPICE code. Otherwise, you will risk causing the SPICE simulator to barf.<br/>
   Example resistor: 
  </p>
  <pre class="code">refdes = R5
  value = 1MEG
  model = TC=0.001,0.015
  SPICE line generated: R2 0 4 220 TC=0.001,0.015</pre>
  
  </div>
  
  <h4><a name="transistors_and_diodes" id="transistors_and_diodes">Transistors and diodes</a></h4>
  <div class="level4">
  
  <p>
  Transistors and diodes are generally accompanied by a device-specific model &ndash; otherwise, SPICE simulation is pointless. The SPICE model may be either a short, one-line string of parameters, or a multi-line set of SPICE parameters. A typical one-line parameter string is a short list of parameters describing a small-signal diode. Typical multi-line models come from component vendors, who often provide models for their components in a text file. Since there are two broad formats of SPICE information, there are two approaches to incorporating these parameters into the schematic:
  </p>
  
  </div>
  
  <h5><a name="one_line_string_of_spice_parameters" id="one_line_string_of_spice_parameters">One line string of SPICE parameters</a></h5>
  <div class="level5">
  
  <p>
  To incorporate a one line string of SPICE parameters into the netlist, the following attributes must be attached to the component: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>Correct component refdes.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>The model number or part number of the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model-name</code></strong></td><td>The name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a &ldquo;value&rdquo; attribute to the component, this parameter is optional.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model</code></strong></td><td>One line string holding additional parameters. Do not place the model parameters in parentheses &ndash; gnetlist will do this for you.</td>
  	</tr>
  </table>
  <br />
  
  <p>
   Example diode: 
  </p>
  <pre class="code">refdes = D5
  model-name = 1N1004
  model = IS=0.5UA RS=6 BV=5.20
  SPICE lines generated:
  D5 2 6 1N1004
  MODEL 1N1004 D (IS=0.5UA RS=6 BV=5.20)</pre>
  
  </div>
  
  <h5><a name="spice_model_file" id="spice_model_file">SPICE model file</a></h5>
  <div class="level5">
  
  <p>
  To incorporate a file-full of SPICE parameters into the netlist, the following attributes must be attached to the component: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>Correct component refdes.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>The model number or part number of the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model-name</code></strong></td><td>The name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a &ldquo;value&rdquo; attribute to the component, this parameter is optional.</td>
  	</tr>
  	<tr>
  		<td><strong><code>file</code></strong></td><td>The file name of the SPICE model which you wish to incorporate into the netlist. This file name may specify either a relative or an absolute path, but it is probably better to use an absolute path to avoid problems if you ever move your schematic directory.</td>
  	</tr>
  </table>
  <br />
  
  <p>
   Note that you need to make sure that the model name held in your SPICE model file is the same as the <strong><code>value</code></strong> or <strong><code>model-name</code></strong> attributes you attached to the component. It is also a good idea to verify that the pin assignments in the model file correspond to the pin assignments made by the component symbol.
  </p>
  
  </div>
  
  <h4><a name="actives_--_integrated_circuits" id="actives_--_integrated_circuits">Actives -- integrated circuits</a></h4>
  <div class="level4">
  
  <p>
  Integrated circuits are incorporated into the netlist similarly to transistors and diodes. As such, you may incorporate the spice information either as a one-line parameter string, or as a model file.
  </p>
  
  </div>
  
  <h5><a name="one_line_string_of_spice_parameters1" id="one_line_string_of_spice_parameters1">One line string of SPICE parameters</a></h5>
  <div class="level5">
  
  <p>
  To incorporate a one line string of SPICE parameters into the netlist, the following attributes must be attached to the component: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>Correct component refdes.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>The model number or part number of the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model-name</code></strong></td><td>the name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a &ldquo;value&rdquo; attribute to the component, this parameter is optional.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model</code></strong></td><td>One line string holding additional parameters. Do not place the model parameters in parentheses &ndash; gnetlist will do this for you.</td>
  	</tr>
  </table>
  <br />
  
  </div>
  
  <h5><a name="spice_.model_or_.subckt_file" id="spice_.model_or_.subckt_file">SPICE .MODEL or .SUBCKT file</a></h5>
  <div class="level5">
  
  <p>
  To incorporate a file-full of SPICE parameters into the netlist, the following attributes must be attached to the component: 
  </p>
  <table class="inline">
  	<tr>
  		<td><strong><code>refdes</code></strong></td><td>Correct component refdes. <strong>Note that if the file holds a .MODEL, the refdes should start with U; if the file holds a .SUBCKT, the refdes should start with X.</strong> The netlister checks for the file type and tries to &ldquo;do the right thing&rdquo;, but problems can arise if you don&rsquo;t follow this rule.</td>
  	</tr>
  	<tr>
  		<td><strong><code>value</code></strong></td><td>The model number or part number of the component.</td>
  	</tr>
  	<tr>
  		<td><strong><code>model-name</code></strong></td><td>The name you wish to give the SPICE model. This is usually the model number or part number of the component. If you have already attached a &ldquo;value&rdquo; attribute to the component, this parameter is optional.</td>
  	</tr>
  	<tr>
  		<td><strong><code>file</code></strong></td><td>The name of the file holding the SPICE .MODEL or .SUBCKT which you wish to incorporate into the netlist. This file name may specify either a relative or an absolute path, but it is probably better to use an absolute path to avoid problems if you ever move your schematic directory.</td>
  	</tr>
  </table>
  <br />
  
  </div>
  
  <h4><a name="independent_sources" id="independent_sources">Independent sources</a></h4>
  <div class="level4">
  
  <p>
  There are two independent sources: voltage sources and current sources. For incorporation into a SPICE netlist, they both work the same way. To incorporate an independent source into your SPICE netlist, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Place the independent source on your schematic. (Do &ldquo;Add&rdquo; &rarr; &ldquo;Component&rdquo; &rarr; &ldquo;spice&rdquo; &rarr; &ldquo;&lt;independent source name&gt;.sym&rdquo;)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: V? or I?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>value</code></strong>: A one line string in SPICE format describing the source.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="dependent_sources" id="dependent_sources">Dependent sources</a></h4>
  <div class="level4">
  
  <p>
  There are four dependent sources:
  </p>
  <ul>
  <li class="level1"><div class="li"> This section remains TBD.</div>
  </li>
  </ul>
  
  </div>
  
  <h4><a name="spice_components" id="spice_components">SPICE components</a></h4>
  <div class="level4">
  
  </div>
  
  <h5><a name="spice_model_block" id="spice_model_block">Spice model block</a></h5>
  <div class="level5">
  
  <p>
  In certain situations, you may wish to embed a spice model block directly into your schematic. This is done when you have several devices with a &ldquo;value&rdquo; attribute calling out for a spice model. Depending upon whether the spice block is one line or multi-line, you may embed the code in one of two ways:
  </p>
  <ol>
  <li class="level1"><div class="li"> One line SPICE model:</div>
  <ol>
  <li class="level2"><div class="li"> Place a spice model block on your schematic. (Do &ldquo;Add&rdquo; &rarr; &ldquo;Component&rdquo; &rarr; &ldquo;spice&rdquo; &rarr; &ldquo;spice-model-1.sym&rdquo;)</div>
  </li>
  <li class="level2"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level3"><div class="li"> <strong><code>refdes</code></strong>: a?</div>
  </li>
  <li class="level3"><div class="li"> <strong><code>model</code></strong>: model name (i.e. the model name used in the components being modeled.)</div>
  </li>
  <li class="level3"><div class="li"> <strong><code>type</code></strong>: One of the valid spice component types defined in the spice <acronym title="specification">spec</acronym>.</div>
  </li>
  <li class="level3"><div class="li"> <strong><code>value</code></strong>: The corresponding one-line spice model</div>
  </li>
  </ul>
  </li>
  </ol>
  </li>
  <li class="level1"><div class="li"> Multi-line SPICE model:</div>
  <ol>
  <li class="level2"><div class="li"> Place a spice model block on your schematic.(Do &ldquo;Add&rdquo; &rarr; &ldquo;Component&rdquo; &rarr; &ldquo;spice&rdquo; &rarr; &ldquo;spice-model-1.sym&rdquo;)</div>
  </li>
  <li class="level2"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level3"><div class="li"> <strong><code>refdes</code></strong>: a?</div>
  </li>
  <li class="level3"><div class="li"> <strong><code>model-name</code></strong>: model name</div>
  </li>
  <li class="level3"><div class="li"> <strong><code>file</code></strong>: Name of file holding SPICE model code (i.e. .MODEL or .SUBCKT).</div>
  </li>
  </ul>
  </li>
  </ol>
  </li>
  </ol>
  
  </div>
  
  <h5><a name="include_block" id="include_block">Include block</a></h5>
  <div class="level5">
  
  <p>
  The include block places a .INCLUDE directive into your netlist.
  </p>
  <ol>
  <li class="level1"><div class="li"> Place a spice model block on your schematic. (Do &ldquo;Add&rdquo; &rarr; &ldquo;Component&rdquo; &rarr; &ldquo;spice&rdquo; &rarr; &ldquo;spice-include-1.sym&rdquo;)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: a?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>file</code></strong>: The name of the file to include.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  
  <h5><a name="spice_directive_block" id="spice_directive_block">SPICE directive block</a></h5>
  <div class="level5">
  
  <p>
  Placing a SPICE directive block into your schematic creates an arbitrary block of SPICE code in the netlist. The directive may be either statements held in a file, or a one-line string held in the &ldquo;model&rdquo; attribute. Examples of situations where this is useful include:
  </p>
  <ul>
  <li class="level1"><div class="li"> .TEMP statement</div>
  </li>
  <li class="level1"><div class="li"> .IC statement</div>
  </li>
  <li class="level1"><div class="li"> Other SPICE statements for which gschem has no symbol.</div>
  </li>
  </ul>
  
  <p>
   To place a SPICE directive on your schematic, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Place a SPICE directive block on your schematic. (Do &ldquo;Add&rdquo; &rarr; &ldquo;Component&rdquo; &rarr; &ldquo;spice&rdquo; &rarr; &ldquo;spice-directive-1.sym&rdquo;)</div>
  </li>
  <li class="level1"><div class="li"> Double click on the block and add/edit the following attributes:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>refdes</code></strong>: a?</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>file</code></strong>: The name of the file to include.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [7283-18697] -->
  <h3><a name="handling_hierarchical_models" id="handling_hierarchical_models">Handling hierarchical models</a></h3>
  <div class="level3">
  
  <p>
  In SPICE modeling, there are often situations where you wish to create a schematic representation of some particular component as a .SUBCKT, and then embed that component&rsquo;s model in a higher level schematic. A common example might be as follows: You are doing a microwave simulation, and want to use a capacitor model which includes parasitic inductances and resistances, as well as the capacitance. Capacitor manufacturers often supply a printed schematic showing a circuit topology incorporating parasitics, and specify values for the parasitics. You would like to draw the capacitor model using gschem, netlist it to create a .SUBCKT, and then use the .SUBCKT to model capacitors in a higher lever schematic.<br/>
   Since this kind of task is very common in SPICE simulation, gnet-spice-sdb now supports it (starting with rev 20030331). To create a lower level .SUBCKT and use it in a higher level schematic, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Draw the schematic of the lower level component (e.g. the capacitor + parasitics) using gschem.</div>
  </li>
  <li class="level1"><div class="li"> On the lower level schematic, place a spice-subcircuit-LL block (spice-subcircuit-LL-1.sym). This alerts the netlister that the schematic is a Lower Level .SUBCKT. Attach the following attributes to the symbol:<br/>
   <br/>
   <strong><code>model-name</code></strong> = cap_with_parasitics<br/>
   <br/>
   (Of course, &ldquo;cap_with_parasitics&rdquo; is the example we use here. Use your own model name in your schematic.) Upon netlisting, this schematic symbol will cause the netlist to insert &ldquo;.SUBCKT cap_with_parasitics &quot; into the first line of the netlist file.</div>
  </li>
  <li class="level1"><div class="li"> On the lower level schematic, attach a spice-subcircuit-IO symbol (spice-subcircuit-IO-1.sym) to each IO net (i.e. connection to the upper level). Number the refdeses of the IO symbols in the same order as you would like the IO nets to be listed in the .SUBCKT line in the output file. (i.e. P1 = first, P2 = second, etc.)</div>
  </li>
  <li class="level1"><div class="li"> When you are done with the lower level schematic, netlist it in the usual way. For example, if your schematic is called cap_with_parasitics.sch, netlist it by saying:<br/>
   <br/>
   <strong><code>gnetlist -g spice-sdb -o cap_with_parasitics.cir cap_with_parasitics.sch</code></strong><br/>
   <br/>
   This will dump the SPICE netlist into the file called &ldquo;cap_with_parasitics.cir&rdquo;. Visually inspect the .cir file to make sure that netlisting worked correctly.</div>
  </li>
  <li class="level1"><div class="li"> Next, create a symbol for the upper level schematic which will point to the .SUBCKT. Note that the symbol must have a refdes starting with the letter &ldquo;X&rdquo;. To ensure that this happens, do the following:</div>
  <ul>
  <li class="level2"><div class="li"> Use gschem to draw the symbol. I usually draw a box around a model symbol to distinguish it from a normal component. Make any other annotations desired.</div>
  </li>
  <li class="level2"><div class="li"> In the symbol, make sure that the pins are ordered identically to the order in which you have placed the pins in the .SUBCKT. This is done by editing the symbol with a text editor and setting the &ldquo;PINSEQ&rdquo; attribute. The netlister will output the pins in the order determined by the &ldquo;PINSEQ&rdquo; attribute.</div>
  </li>
  <li class="level2"><div class="li"> Using a text editor, give the symbol a &ldquo;DEVICE&rdquo; attribute like &ldquo;capacitor-model&rdquo;. Do not assign the symbol one of the native device types listed in the appendix! The goal is to create a symbol whose refdes starts with &ldquo;X&rdquo;, and if the &ldquo;DEVICE&rdquo; is a recognized type, this will not happen.</div>
  </li>
  <li class="level2"><div class="li"> Using a text editor, give the symbol the &ldquo;REFDES&rdquo; attribute &ldquo;X?&rdquo;</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> Create the upper level schematic. Place your newly created symbol on the schematic as many times as required &amp; wire up the schematic in the usual way.</div>
  </li>
  <li class="level1"><div class="li"> To point your symbol to the lower level .SUBCKT, double click on the symbol and set the following attributes:<br/>
   <br/>
   <strong><code>file</code></strong> = cap_with_parasitics.cir<br/>
   <strong><code>model-name</code></strong> = cap_with_parasitics<br/>
   <br/>
   as well as any other attributes required (e.g. refdes).</div>
  </li>
  <li class="level1"><div class="li"> Now netlist your upper level schematic the usual way. The contents of each .SUBCKT file is dumped into the main netlist. Inspect your netlist visually using a text editor to ensure that it is correct. It is a good idea to pay particular attention to the following:</div>
  <ul>
  <li class="level2"><div class="li"> Verify that the ordering of the nets connecting the upper level netlist to the lower level .SUBCKT is correct.</div>
  </li>
  <li class="level2"><div class="li"> Make sure that the upper level model-name and the lower level model name (on the .SUBCKT declaration line) are the same.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  <p>
   Once the netlist is created, you may simulate your design using any SPICE simulator desired.<br/>
  
  </p>
  
  <p>
  One final note: The netlister writes the contents of the lower level .SUBCKT file into the main netlist <strong>every time</strong> it encounters a component with &ldquo;FILE&rdquo; attribute pointing to that file. Therefore, if you use the same component with the same model more than once in a design you should instantiate the model file using a &ldquo;spice-model&rdquo; symbol and point to it with each component. This is described in the &ldquo;multi-line SPICE model block&rdquo; section above.
  </p>
  
  </div>
  <!-- SECTION [18698-23545] -->
  <h2><a name="spice_netlist_generation" id="spice_netlist_generation">SPICE netlist generation</a></h2>
  <div class="level2">
  
  <p>
  Once the schematic is captured, a SPICE netlist can be generated running the gEDA utility &ldquo;gnetlist&rdquo; on the schematic files. Gnetlist is built to be customizable, and is able to generate a netlist of any desired format using a Scheme back-end, which does the real heavy-lifting of creating the netlist. The back-end Scheme file which implements SPICE netlisting is called gnet-spice-sdb.scm, and it lives in the ${PREFIX}/geda/share/gEDA/scheme directory.
  </p>
  
  </div>
  <!-- SECTION [23546-24039] -->
  <h2><a name="creating_the_netlist" id="creating_the_netlist">Creating the netlist</a></h2>
  <div class="level2">
  
  <p>
  Creating a netlist from a schematic is easy. To generate a SPICE netlist, just do the following:
  </p>
  <ul>
  <li class="level1"><div class="li"> Save your schematic to &lt;filename.sch&gt;</div>
  </li>
  <li class="level1"><div class="li"> Create the SPICE netlist by doing &ldquo;gnetlist â??g spice-sdb &lt;filename.sch&gt;&rdquo;. The output is a netlist held in the file output.net. Alternatively, if you wish to give your output file a different name, set the output name using the -o switch. For example:<br/>
   <br/>
   <strong><code>gnetlist -g spice-sdb -o amplifier.cir amplifier.sch</code></strong> <br/>
   <br/>
   takes the design schematic called &ldquo;amplifier.sch&rdquo; and outputs a SPICE netlist named &ldquo;amplifier.cir&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> Inspect your SPICE netlist using a text editor. Verify that there are no missing attributes or other netlist problems.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [24040-24765] -->
  <h2><a name="common_netlisting_problems" id="common_netlisting_problems">Common netlisting problems</a></h2>
  <div class="level2">
  
  <p>
  It is important to manually inspect your SPICE netlist prior to using it in simulation. Please remember that the netlister is still &ldquo;alpha&rdquo; quality, and some problems may still exist in netlist generation. The following list attempts to catalog common problems with the netlist and the associated fixes.
  </p>
  <ul>
  <li class="level1"><div class="li"> ERROR_INVALID_<acronym title="Personal Identification Number">PIN</acronym>: This can happen if the symbolâ??s PINSEQ attributes donâ??t start at 1, or have gaps in the numbering. This must be fixed by editing the symbol itself in a text editor.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [24766-25301] -->
  <h2><a name="spice_simulation" id="spice_simulation">SPICE simulation</a></h2>
  <div class="level2">
  
  <p>
  There are several options for doing SPICE simulations under Linux; I will highlight two:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>LTSpice</strong>, which is a freeware SPICE simulator originally released by Linear Technologies as a component selection/design tool running under Windows. Because its SPICE engine is very fast and powerful, it has become a popular SPICE simulator amongst hobbyists and design engineers who prefer to use free tools. LTSpice has been tweaked to run under Linux using wine; I recommend using it if you need a robust, <strong>professional-quality</strong> SPICE simulator.</div>
  <ul>
  <li class="level2"><div class="li"> <strong>Ngspice/tclspice</strong>, which is a component of the gEDA distribution. Ngspice provides a simulation engine, a command-line driven front-end, and the capability to plot simulation results graphically under X. The main branch of ngspice development has been arrested since late 2001. However, a fork of the development tree, called &ldquo;tclspice&rdquo;, remains under active development. Tclspice is the package I recommend if you want to use a <strong>Linux-native</strong> SPICE simulator. </div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   There is also a <acronym title="GNU General Public License">GPL</acronym>&lsquo;ed simulator called &ldquo;gnucap&rdquo;, which is based upon (or is the descendent of) Al&rsquo;s Circuit Simulator (ACS). I haven&rsquo;t used it at all; information about gnucap is therefore TBD.
  </p>
  
  </div>
  <!-- SECTION [25302-26547] -->
  <h3><a name="ltspice" id="ltspice">LTSpice</a></h3>
  <div class="level3">
  
  <p>
  LTSpice was written by Mike Englehardt at Linear Technologies, and was originally given away by LinearTech as a design aid for engineers wishing to simulate the performance of LinearTech&rsquo;s switch mode power supply controllers. The package incorporates a schematic capture front end, fast and powerful SPICE engine, and the capability for plotting the results of many different types of SPICE analysis. Personally, I think the schematic capture front-end is hard to use and clunky; gschem knocks its socks off for ease of use and features. However, the SPICE engine and analysis stuff in LTSpice is simply great.<br/>
   LTSpice was originally developed to run under Windows, but Mike has tweaked it so that it runs fairly well on Linux under wine. (Only the help menu system is broken &ndash; the rest of the package runs well.) Another good feature of LTSpice is that it is well supported &ndash; Mike reads the newsgroup sci.electronics.cad regularly and is generally happy to help people who experience problems with it. Therefore, despite its Windoze heritage, I recommend LTSpice as a powerful, professional-quality simulation and analysis back end for gEDA. 
  </p>
  
  </div>
  
  <h4><a name="installation_and_configuration_of_ltspice" id="installation_and_configuration_of_ltspice">Installation and configuration of LTSpice</a></h4>
  <div class="level4">
  
  <p>
  To install and configure LTSpice, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Download and install wine. I have had success using Wine-20030219.</div>
  </li>
  <li class="level1"><div class="li"> Download LTSpice. It is available under <a href="http://www.linear.com/software"; class="urlextern" title="http://www.linear.com/software";  rel="nofollow">http://www.linear.com/software</a> under the name SwitcherCAD-III.</div>
  </li>
  <li class="level1"><div class="li"> Run the LTSpice installer under wine.</div>
  </li>
  </ol>
  
  </div>
  
  <h4><a name="running_ltspice_with_geda_designs" id="running_ltspice_with_geda_designs">Running LTSpice with gEDA designs</a></h4>
  <div class="level4">
  
  <p>
  LTSpice can read a file holding a gEDA SPICE netlist. I have had success doing LTSpice sumulations in the following way:
  </p>
  <ol>
  <li class="level1"><div class="li"> First of all, make sure that you are logged in as a normal user &ndash; Wine doesn&rsquo;t like to run when invoked by root.</div>
  </li>
  <li class="level1"><div class="li"> Create a file in your project directory called &ldquo;Simulation.cmd&rdquo;. In this file place your spice analysis commands (e.g. .OP, .AC, .DC, etc.)</div>
  </li>
  <li class="level1"><div class="li"> Place a SPICE include block into your schematic. For the file attribute, type in &ldquo;Simulation.cmd&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> Netlist your design.</div>
  </li>
  <li class="level1"><div class="li"> Create a link from your netlist &ldquo;output.net&rdquo; and a netlist in the directory in which SwCADIII lives. Make the netlist suffix .cir. For example: ln -s ${DESIGN_HOME}/output.net ${WINE_HOME}/.wine/fake_windows/Program Files/LTC/SwCADIII/MyDesign.cir</div>
  </li>
  <li class="level1"><div class="li"> Run LTSpice: cd into the directory where SwCADIII lives and say &ldquo;wine scad3.exe&rdquo;</div>
  </li>
  <li class="level1"><div class="li"> From the SwCADIII <acronym title="Graphical User Interface">GUI</acronym>, do: File &rarr; Open &rarr; (files of type netlist [.cir]), and select your file.</div>
  </li>
  <li class="level1"><div class="li"> Run the simulator by clicking on the run button, or doing: Simulate &rarr; Run.</div>
  </li>
  <li class="level1"><div class="li"> Select the variables to graph, and then click OK. SwCADIII does the rest of the work.</div>
  </li>
  </ol>
  
  <p>
   Naturally, it is very important to play around with LTSpice to understand how to use it effectively, but the above description should suffice to get you started.
  </p>
  
  </div>
  <!-- SECTION [26548-29363] -->
  <h3><a name="ngspice_and_tclspice" id="ngspice_and_tclspice">Ngspice and tclspice</a></h3>
  <div class="level3">
  
  <p>
  Ngspice was started at the University of Rome by Paolo Nenzi as an attempt to create a <acronym title="GNU General Public License">GPL</acronym>&lsquo;ed version of the standard Berkeley SPICE version 3 by re-writing the entire SPICE package. Plans were also laid to create better, more robust computational algorithms for the simulation engine. More information is available at the <a href="http://ngspice.sourceforge.net/"; class="urlextern" title="http://ngspice.sourceforge.net/";  rel="nofollow">ngspice website</a>. Unfortunately, development on ngspice seems to have ceased at the end of 2001. Moreover, my initial experiences with ngspice were not good &ndash; it crashed and burned when run on many of my netlists, and it couldn&rsquo;t deal with SPICE 2&rsquo;s POLY construct in dependent sources. Dependent sources with PLOY attributes are common in vendor models, so this represents a real deficiency.
  </p>
  
  <p>
  Fortunately, some friendly people at <a href="http://www.multigig.com/"; class="urlextern" title="http://www.multigig.com";  rel="nofollow">MultiGig Ltd.</a> were busy developing a branch of ngspice which they called &ldquo;tclspice&rdquo;. The purpose of tclspice is to enable SPICE commands to be embedded into TCL scripts, thereby enabling automated circuit optimization. The project homepage is at <a href="http://tclspice.sourceforge.net/"; class="urlextern" title="http://tclspice.sourceforge.net/";  rel="nofollow">http://tclspice.sourceforge.net/</a>. Since the tclspice branch of the code was alive, I decided to work on it, instead of the seemingly dead main ngspice branch. During spring 2003, I fixed tclspice in three useful (IMNSHO) ways:
  </p>
  <ol>
  <li class="level1"><div class="li"> I fixed the parser so that it would handle netnames with non-numeric/non-alphabetic characters like &ldquo;+&rdquo; or &ldquo;-&rdquo; which are common in real netlists (e.g. &ldquo;Vin+&rdquo;, or &ldquo;Vout1_pull-up&rdquo;).</div>
  </li>
  <li class="level1"><div class="li"> I fixed the parser so that it would correctly handle hierarchical schematics, and correctly deal with the netnames inside the blocks.</div>
  </li>
  <li class="level1"><div class="li"> I got the POLY translation code (which exists in XSPICE) working so that one can now run SPICE 2 netlists with tclspice.</div>
  </li>
  </ol>
  
  <p>
   Tclspice seems to work nicely now (although there are still some issues with memory leaks). Moreover, because the tclspice code is a superset of ngspice, <strong>if you build tclspice, you will also build the command-line driven ngspice program</strong>. Therefore, I recommend getting and installing tclspice if you want to do Linux-native SPICE simulations.
  </p>
  
  </div>
  
  <h4><a name="installation_and_configuration_of_ngspice_and_tclspice" id="installation_and_configuration_of_ngspice_and_tclspice">Installation and configuration of ngspice and tclspice</a></h4>
  <div class="level4">
  
  <p>
  To install ngspice and tclspice, do the following:
  </p>
  <ol>
  <li class="level1"><div class="li"> Get the latest tclspice distribution from <a href="http://tclspice.sourceforge.net/"; class="urlextern" title="http://tclspice.sourceforge.net/";  rel="nofollow">http://tclspice.sourceforge.net/</a>. As of this writing, the latest version is tclspice-0.2.12. This version incorporates the fixes I mentioned above, as well as other improvements made by the hard-working people at MultiGig, so make sure that your version is equal or greater than 0.2.12.</div>
  </li>
  <li class="level1"><div class="li"> Do the usual &ldquo;gunzip ; tar -xvf&rdquo; dance to create a source directory for tclspice.</div>
  </li>
  <li class="level1"><div class="li"> First build ngspice. Do &ldquo;./configure &ndash;enable-xspice &ndash;prefix=/usr/local/geda&rdquo; in the source directory. Of course, &ldquo;&ndash;prefix=&rdquo; should point to the place where you put your geda stuff. Note that you also must do &ldquo;&ndash;enable-xspice&rdquo; to be able to use SPICE 2 POLYs (and other XSpice goodies).</div>
  </li>
  <li class="level1"><div class="li"> Do &ldquo;make &amp;&amp; make install&rdquo; to compile and install ngspice. As always, you will probably need to be root in order to install the packages in a public directory.</div>
  </li>
  <li class="level1"><div class="li"> At this point, you should be able to use ngspice. You can test your installation by trying one of the test circuits held in the tests directory. I recommend running the TransImpedanceAmp test, since it tests the SPICE2 POLY functionality. Information how to use ngspice is provided in the next section below.</div>
  </li>
  <li class="level1"><div class="li"> If you only want to use ngspice, you can stop now. Otherwise, next build tclspice. To build tclspice, you need to have the following other packages already installed:<br/>
   <br/>
   * TclX (tclx8.3.5 works for me.)<br/>
   * tclreadline (tclreadline-2.1.0 works for me.)<br/>
   * BLT for TCL (blt2.4z works for me.)<br/>
   <br/>
   If you don&rsquo;t have these packages already on your Linux box, you need to get them and build them. Note that building TclX requires having the sources for TCL and Tk, so you will also need to get those sources if you don&rsquo;t have them installed already. I am running successfully with TCL/Tk 8.4.3, although 8.3.X versions are also supposed to work.</div>
  </li>
  <li class="level1"><div class="li"> Assuming you have gotten the additional packages mentioned above installed, Do &ldquo;./configure &ndash;enable-xspice &ndash;prefix=/usr/local/geda &ndash;enable-tcl &ndash;enable-experimental &ndash;disable-shared&rdquo; to configure the Makefiles for tclspice. (If you don&rsquo;t have the additional packages installed correctly , configure will complain and barf, so this step acts as a check on your installation.)</div>
  </li>
  <li class="level1"><div class="li"> Do &ldquo;make tcl &amp;&amp; make install-tcl&rdquo; to compile and install tclspice.</div>
  </li>
  <li class="level1"><div class="li"> Now you will be ready to write TCL scripts which incorporate SPICE commands. Information about using tclspice is given below.</div>
  </li>
  </ol>
  
  <p>
   Finally, if you are interested in hacking tclspice (or even if you are not), it&rsquo;s a good idea to read the NOTES file living in the top source directory for a couple of useful pointers.
  </p>
  
  </div>
  
  <h4><a name="use_of_ngspice" id="use_of_ngspice">Use of ngspice</a></h4>
  <div class="level4">
  
  <p>
  Running ngspice is very simple. Just issue the command &ldquo;ngspice filename.net&rdquo; at the unix command prompt, and ngspice will load the SPICE netlist called &ldquo;filename.net&rdquo; into its workspace, and leave you at an ngspice command prompt. You can run the simulator by saying &ldquo;run&rdquo;. Your results will be stored in SPICE vectors for later printing or plotting. The command set available to you is documented at <a href="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5"; class="urlextern" title="http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5";  rel="nofollow">http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec5.html#5</a>.<br/>
   To make use of the SPICE2 POLY codemodel, you need to load it into ngspice <strong>before</strong> you load your netlist. (If you load it after loading your netlist, POLYs in your netlist are not translated, and therefore won&rsquo;t be simulated correctly.) To load the codemodel, just say &ldquo;codemodel /usr/local/src/tclspice-0.2.12/src/xspice/icm/spice2poly.cm&rdquo; at the ngspice prompt. Note that you must provide the <strong>absolute path</strong> to the location of the codemodel; ngspice isn&rsquo;t smart enough to look for it in any default locations. (Also note that you should specify the location where spice2poly.cm lives on your machine; the path above is for mine.)<br/>
   A better way to read in the spice2poly codemodel is to include it in the ngspice initialization file, &ldquo;spinit&rdquo;. The initialization file lives in the directory /usr/local/geda/share/ng-spice-rework/scripts (or where ever you placed your geda installation). Other ngspice customizations may also be placed into the spinit file.
  </p>
  
  </div>
  
  <h4><a name="use_of_tclspice" id="use_of_tclspice">Use of tclspice</a></h4>
  <div class="level4">
  
  <p>
  The tclspice package is a superset of ngspice. Not only does the package include the ngspice interactive environment; tclspice also provides a facility which exports the ngspice command set as TCL commands for inclusion into a TCL script. This is a very powerful tool: With tclspice you can write a TCL script which runs a loop, tweaks component values, runs an analysis, and then evaluates the circuit performance with the tweaked components before looping again. Obviously, this ability can be used to perform automated, multi-dimensional circuit optimization.<br/>
   To use tclspice, you just need to say &ldquo;package require spice&rdquo; at the beginning of your TCL program. Thereafter, to invoke a SPICE command, you just call it in the spice namesapce. For example, the following TCL program will read in a SPICE netlist, command a transient analysis, run the simulation, and then plot the voltage observed over time on net Vout: 
  </p>
  <pre class="code">#! tclsh
  package require spice
  spice::codemodel /usr/local/src/tclspice-0.2.12/src/xspice/icm/spice2poly.cm
  
  spice::source netlistname.cir
  spice::tran 0.1ns 40ns
  spice::run
  spice::plot Vout
  puts &quot;All done now!&quot;</pre>
  
  <p>
  Note that since tclspice doesn&rsquo;t read the ngspice initialization file &ldquo;spinit&rdquo;, you will need to put any initialization commands directly into the TCL program. For example, in the above example we read the spice2poly codemodel directly into the workspace. Many other commands are also available; the entire tclspice commandset is documented at <a href="http://tclspice.sourceforge.net/docs/tclspice_com.html"; class="urlextern" title="http://tclspice.sourceforge.net/docs/tclspice_com.html";  rel="nofollow">http://tclspice.sourceforge.net/docs/tclspice_com.html</a>.<br/>
   A major problem with tclspice (which was inherited from ngspice) is that it leaks memory. Therefore, the time over which you may run a simulation is limited. This means that if you want to do an optimization by looping through a circuit many, many times, you may run out of memory before your program has completed its optimization. This is a known issue with tclspice, and efforts are underway to plug the leaks.<br/>
   Meanwhile, there are some workarounds which can be used on moderate-sized designs to facilitate long optimization runs. One method I have employed is to have the optimizer write its current state into a file after every circuit analysis, and read its starting state from the same file. The optimizer also stores the current list of best components in another file, and reads this file at the start of every run. Then, I have a TCL program called TaskMgr.tcl which runs in a loop; at each iteration of the loop it forks a child process to run the optimizer. Meanwhile, the parent process waits for 5 minutes (a heuristically determined time), and then issues a &ldquo;KILL&rdquo; signal to the child before looping and starting the optimizer again. This way, the optimizer never runs long enough to consume all the memory in my machine. The TaskMgr.tcl program is shown here: 
  </p>
  <pre class="code">#! tclsh
  package require Tclx
  while {1} {
  
      set PID [fork]
      if {$PID} {
  
          # Parent
          after 300000
          puts &quot;About to kill child PID = $PID . . . .&quot;
          kill $PID
          wait $PID
  
      } else {
  
          # Child
          source Optimize.tcl
          # If we ever get through this, we can print out the following:
          error &quot;We are done now!!!!!!&quot; 
  
      } 
  
  }</pre>
  
  <p>
  Note that TaskMgr.tcl needs the TclX package you already installed to run tclspice. Also, you may want to change the wait time to a different value depending upon the memory and speed of your machine. Finally, the parent has to wait on $PID because that causes the child process&rsquo;s corpse to be taken off the Linux kernal&rsquo;s task list when it dies. Otherwise, you will end up with a lot of zombie processes lurking around your machine as the optimizer runs &ndash; a long optimization could turn your system into &ldquo;the night of the living dead&rdquo;!<br/>
   This method of waiting a specific amout of time for the child process is preferable if a single analysis run takes a relativly short time compared to the time required to eat all memory in the machine. If the analysis time is comparable to the time taken to eat all memory in the machine, a better approach is to have the parent keep track of the analysis state, kick off a single analysis run, and then have the run terminate after every iteration. Whether this is preferable depends upon the size and complexity of your design; you may want to experiment with your analysis to see just how long it takes and how much memory it consumes. I have found that a design comprised of six op amps (with corresponding vendor models) and 50 or so passives will run in under 10 seconds on a PIII 333MHz with 128MB RAM. Therefore, your design must be very big before a single analysis will eat a significant amount of RAM.
  </p>
  
  </div>
  <!-- SECTION [29364-40393] -->
  <h2><a name="appendix" id="appendix">Appendix</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [40394-40415] -->
  <h3><a name="component_attribute_summary" id="component_attribute_summary">Component attribute summary</a></h3>
  <div class="level3">
  
  <p>
  Native components and their attributes are given in the table below. <strong>Bold faced</strong> attributes are <strong>required</strong>, normal typeface attributes are optional. Note that the &ldquo;device&rdquo; attribute is invisible, and is normally attached to the symbol when it is created. The other attributes are attached to the symbol during schematic capture using gschem. 
  </p>
  <table class="inline">
  	<tr>
  		<th><strong><code>device</code></strong></th><th><strong><code>refdes</code></strong></th><th><strong><code>value</code></strong></th><th><strong><code>model</code></strong></th><th><strong><code>file</code></strong></th><th><strong><code>model-name</code></strong></th><th><strong><code>type</code></strong></th><th>Comment</th>
  	</tr>
  	<tr>
  		<td><strong>RESISTOR</strong></td><td><strong>R?</strong></td><td><strong>Numeric comp. value</strong></td><td>One line of spice model parameters (e.g. TC)</td><td> </td><td>Name of model.</td><td> </td><td>&ldquo;model&rdquo; parameters are placed inside parentheses after the component value.</td>
  	</tr>
  	<tr>
  		<td><strong>CAPACITOR</strong></td><td><strong>C?</strong></td><td><strong>Numeric comp. value</strong></td><td>One line of spice model parameters (e.g. IC, POLY, etc.)</td><td> </td><td>Name of model.</td><td> </td><td>&ldquo;model&rdquo; parameters are placed inside parentheses after the component value.</td>
  	</tr>
  	<tr>
  		<td><strong>POLARIZED_CAPACITOR</strong></td><td><strong>C?</strong></td><td><strong>Numeric comp. value</strong></td><td>One line of spice model parameters (e.g. IC, POLY, etc.)</td><td> </td><td>Name of model.</td><td> </td><td>&ldquo;model&rdquo; parameters are placed inside parentheses after the component value.</td>
  	</tr>
  	<tr>
  		<td><strong>INDUCTOR</strong></td><td><strong>L?</strong></td><td><strong>Numeric comp. value</strong></td><td>One line of spice model parameters (e.g. IC, POLY, etc.)</td><td> </td><td>Name of model.</td><td> </td><td>&ldquo;model&rdquo; parameters are placed inside parentheses after the component value.</td>
  	</tr>
  	<tr>
  		<td><strong>SPICE-ccvs</strong></td><td><strong>H?</strong></td><td><strong>String describing source behavior</strong></td><td> </td><td> </td><td> </td><td> </td><td> </td>
  	</tr>
  	<tr>
  		<td><strong>SPICE-cccs</strong></td><td><strong>F?</strong></td><td><strong>String describing source behavior</strong></td><td> </td><td> </td><td> </td><td> </td><td> </td>
  	</tr>
  	<tr>
  		<td><strong>SPICE-vcvs</strong></td><td><strong>E?</strong></td><td><strong>String describing source behavior</strong></td><td> </td><td> </td><td> </td><td> </td><td> </td>
  	</tr>
  	<tr>
  		<td><strong>SPICE-vccs</strong></td><td><strong>G?</strong></td><td><strong>String describing source behavior</strong></td><td> </td><td> </td><td> </td><td> </td><td> </td>
  	</tr>
  	<tr>
  		<td><strong>SPICE-nullor</strong></td><td><strong>E?</strong></td><td><strong>String describing source behavior</strong></td><td> </td><td> </td><td> </td><td> </td><td> </td>
  	</tr>
  	<tr>
  		<td><strong>DIODE</strong></td><td><strong>D?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>PMOS_TRANSISTOR</strong></td><td><strong>M?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>NMOS_TRANSISTOR</strong></td><td><strong>M?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>PNP_TRANSISTOR</strong></td><td><strong>Q?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>NPN_TRANSISTOR</strong></td><td><strong>Q?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>PFET_TRANSISTOR (JFET)</strong></td><td><strong>J?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>NFET_TRANSISTOR (JFET)</strong></td><td><strong>J?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>MESFET_TRANSISTOR</strong></td><td><strong>B?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>IC</strong></td><td><strong>U?</strong></td><td>Part number</td><td>One line SPICE model.</td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>IC with .MODEL file</td>
  	</tr>
  	<tr>
  		<td><strong>IC</strong></td><td><strong>X?</strong></td><td>Part number</td><td> </td><td>Model file name.</td><td><strong>Name of model.</strong></td><td> </td><td>IC with .SUBCKT file</td>
  	</tr>
  	<tr>
  		<td><strong>model</strong></td><td colspan="2"><strong>A?</strong></td><td>One line spice model</td><td>Model file name.</td><td><strong>Name of model pointed to by other components.</strong></td><td><strong>Corresponding SPICE model type (valid types given below)</strong>.</td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>include</strong></td><td><strong>A?</strong></td><td> </td><td> </td><td><strong>Include file name.</strong></td><td> </td><td> </td><td>Places .INCLUDE directive in SPICE netlist.</td>
  	</tr>
  	<tr>
  		<td><strong>options</strong></td><td><strong>A?</strong></td><td><strong>Line of options to include.</strong></td><td> </td><td> </td><td> </td><td> </td><td>Places .OPTIONS directive in SPICE netlist.</td>
  	</tr>
  	<tr>
  		<td><strong>directive</strong></td><td><strong>A?</strong></td><td><strong>One line string holding SPICE statements for inclusion in netlist.</strong></td><td> </td><td> </td><td> </td><td> </td><td>For modeling, one must include either &ldquo;model&rdquo; or &ldquo;file&rdquo;.</td>
  	</tr>
  	<tr>
  		<td><strong>VOLTAGE_SOURCE</strong></td><td><strong>V?</strong></td><td><strong>One line string holding voltage source behavior.</strong></td><td> </td><td> </td><td> </td><td> </td><td>Independent voltage source</td>
  	</tr>
  	<tr>
  		<td><strong>CURRENT_SOURCE</strong></td><td><strong>I?</strong></td><td><strong>One line string holding current source behavior.</strong></td><td> </td><td> </td><td> </td><td> </td><td>Independent current source</td>
  	</tr>
  </table>
  <br />
  
  <p>
   &ldquo;Native to the netlister&rdquo; means that there is a corresponding blob of scheme code which knows exactly how to handle these components and is guaranteed (almost) to generate correct spice code. Symbols having &ldquo;device&rdquo; attributes not on the above list are handled using the scheme function &ldquo;spice-sdb:write-default-component&rdquo;, which looks at the refdes of the component to make a decision about how to treat the component. In general, this function will &ldquo;do the right thing&rdquo; when generating spice code, but it is not guaranteed. In particular, this function cannot distinguish between N and P type transistors, and will generate an &lt;unknown&gt; type for the .MODEL string in the netlist. This will probably cause your SPICE simulator to barf. Therefore, it is best to make sure that all devices used have the proper &ldquo;device&rdquo; attribute.
  </p>
  
  </div>
  <!-- SECTION [40416-45184] -->
  <h3><a name="valid_type_values" id="valid_type_values">Valid &quot;type&quot; values</a></h3>
  <div class="level3">
  
  <p>
  The &ldquo;type&rdquo; attribute is a flag signaling the spice engine the component type, and prepares it to accept model parameters specific to that component type. The following values are valid SPICE &ldquo;type&rdquo;s: 
  </p>
  <table class="inline">
  	<tr>
  		<th>Component</th><th>&ldquo;type&rdquo;</th><th>Comment</th>
  	</tr>
  	<tr>
  		<td>RESISTOR</td><td>RES</td><td> </td>
  	</tr>
  	<tr>
  		<td>CAPACITOR</td><td>CAP</td><td> </td>
  	</tr>
  	<tr>
  		<td>POLARIZED_CAPACITOR</td><td>CAP</td><td> </td>
  	</tr>
  	<tr>
  		<td>INDUCTOR</td><td>IND</td><td> </td>
  	</tr>
  	<tr>
  		<td>DIODE</td><td>D</td><td> </td>
  	</tr>
  	<tr>
  		<td>PMOS_TRANSISTOR</td><td>PMOS</td><td> </td>
  	</tr>
  	<tr>
  		<td>NMOS_TRANSISTOR</td><td>NMOS</td><td> </td>
  	</tr>
  	<tr>
  		<td>PNP_TRANSISTOR</td><td>PNP</td><td> </td>
  	</tr>
  	<tr>
  		<td>NPN_TRANSISTOR</td><td>NPN</td><td> </td>
  	</tr>
  	<tr>
  		<td>PFET_TRANSISTOR</td><td>PJF</td><td> </td>
  	</tr>
  	<tr>
  		<td>NFET_TRANSISTOR</td><td>NJF</td><td> </td>
  	</tr>
  	<tr>
  		<td>MESFET_TRANSISTOR</td><td> </td><td> </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [45185-45703] -->
  <h2><a name="document_history" id="document_history">Document History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td>Revision 1.0</td><td>3.10.2003</td><td>SDB</td><td>Document creation.</td>
  	</tr>
  	<tr>
  		<td>Revision 1.1</td><td>3.19.2003</td><td>SDB</td><td>Added .SUBCKT stuff &amp; stuff about LTSpice</td>
  	</tr>
  	<tr>
  		<td>Revision 1.2</td><td>3.31.2003</td><td>SDB</td><td>Added stuff about creating hierarchical projects (i.e. creating .SUBCKTs using gschem and incorporating a lower level .SUBCKT into a higher level schematic).</td>
  	</tr>
  	<tr>
  		<td>Revision 2.0</td><td>7.23.2003</td><td>SDB</td><td>Split doc into sections. Edited netlisting stuff to correspond to gEDA-20030525, which now includes spice-sdb in the distribution. Added new section about ngspice/tclspice.</td>
  	</tr>
  </table>
  <br />
  
  <p>
   The most recent copy of this document is always available at <a href="http://www.brorson.com/gEDA/SPICE/"; class="urlextern" title="http://www.brorson.com/gEDA/SPICE/";  rel="nofollow">http://www.brorson.com/gEDA/SPICE/</a> 
  </p>
  
  </div>
  <!-- SECTION [45704-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_sn_readme.html
  
  Index: geda_sn_readme.html
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  <h1><a name="switcap_netlister_readme" id="switcap_netlister_readme">Switcap netlister README</a></h1>
  <div class="level1">
  <pre class="code">-----------------------------------------------------------------
  I.   What is this?
  -----------------------------------------------------------------
  
  This archive contains a set of symbols and a netlister backend for the
  gEDA to drive SWITCAP simulations.  gEDA is the GNU EDA project and
  includes a schematic capture tool and a highly flexible netlister.
  The SWITCAP program is a switched capacitor circuit simulator.
  
  -----------------------------------------------------------------
  II.  Overview
  -----------------------------------------------------------------
  
  The basic steps involved with using gEDA as the frontend for SWITCAP
  simulations are:
  
  - configure the gEDA symbol search path
  - set the gEDA netlister backend search path
  - create schematics of the circuit
  - create an analysis file
  - extract the netlist
  - run the SWITCAP simulation
  
  
  -----------------------------------------------------------------
  III.  Initial Setup
  -----------------------------------------------------------------
    1)  Set your symbol search path for gschem and gnetlist by adding
        the following line to the 'gschemrc' and 'gnetlistrc' files in
        your project directory.  
  
          (component-library &quot;/path/to/sym/switcap&quot;)
  
        If those files do not exist, then create them.  You will need to
        replace /path/to/sym/switcap with the directory name where you
        have installed the .sym files.
  
    2)  Set the search path for scheme files for gnetlist by adding the
        following line to your 'gnetlistrc' file.
  
          (scheme-directory &quot;/path/to/scheme&quot;)
  
        You will need to replace /path/to/scheme with the path to where
        you have installed the gnet-switcap.scm file.
  
    3)  
  
  -----------------------------------------------------------------
  IV.  Creating Schematics
  -----------------------------------------------------------------
  
  --------------------
  A.  Required Symbols
  --------------------
  
  This section assumes you are familiar with using gschem to create and
  edit schematics.  SWITCAP netlisting is only supported for the
  components contained in the SWITCAP symbol library as well as the
  ground symbol found in the 'power' library which comes with gEDA.  All
  allowed SWITCAP elements except for subcircuits are supported.  You
  _must_ include the following elements on your schematic:
  
  - one instance of the switcap-timing symbol.  This symbol will set the
    master clock period for your simulations.
  
  - one or more instances of the switcap-clock symbol.  This symbol
    defines a clock with a particular phase and period.  The reference
    designator of the clock symbol is used by the switches to set what
    phase they switch on.
  
  - one or more instances of the switcap-analysis symbol.  This symbol
    defines an analysis by specifying a file to include in the SWITCAP
    netlist.
  
  --------------------
  B.  Optional Symbols
  --------------------
  
  You can also optionally add the following SWITCAP special symbols to
  your schematic:
  
  - zero or one instance of the switcap-title symbol.  This will add a
    TITLE: line to the SWITCAP netlist and will appear in the output
    file.
  
  - zero or one instance of the switcap-options symbol.  By editing the
    OPTIONS attribute on this symbol you can set the various options
    which can be passed to SWITCAP.
  
  --------------------
  C.  Net Names
  --------------------
  
  When creating schematics to drive SWITCAP, you should name all nets
  that you wish to plot.  To avoid possible conflicts with unnamed nets,
  you should avoid using purely numerical names for nets because
  all unnamed nets will be assigned (somewhat randomly) numbers.
  SWITCAP limits the length of node names to 7 characters.
  
  --------------------
  D.  Switches
  --------------------
  
  When placing switches on your schematic, you will need to define
  which clock they are controlled with.  This is done by setting
  the clock attribute on the switch to the reference designator 
  of the clock which should control it.
  
  -----------------------------------------------------------------
  V.  Extracting the SWITCAP Netlist
  -----------------------------------------------------------------
  
  To extract the SWITCAP netlist, run
  
    gnetlist -g switcap -o test.scn file1.sch [file2.sch ...]
  
  For the example file contained in this archive, you can run:
  
    gnetlist -g switcap -o example.scn ckt.sch clocks.sch analysis.sch
  
  The netlist will be left in example.scn.
  
  -----------------------------------------------------------------
  VI.  Running SWITCAP
  -----------------------------------------------------------------
  
  I typically use something like:
  
    printf &quot;example.scn\nexample.out&quot; | sw
  
  so I can use command history to rerun SWITCAP without having to
  manually type the file names each time.
  
  Refer to the SWITCAP manual for more details.
  
  
  </pre>
  
  </div>
  </div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_ssan.html
  
  Index: geda_ssan.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#geda_gaf_switcap_symbols_and_netlister" class="toc">gEDA/gaf Switcap Symbols and Netlister</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#overview" class="toc">Overview</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#requirements" class="toc">Requirements</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#creating_schematics" class="toc">Creating Schematics</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#required_symbols" class="toc">Required Symbols</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#optional_symbols" class="toc">Optional Symbols</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#net_names" class="toc">Net Names</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#switches" class="toc">Switches</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#extracting_the_switcap_netlist" class="toc">Extracting the SWITCAP Netlist</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#running_switcap" class="toc">Running SWITCAP</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#appendix_a_--_symbols_in_the_library" class="toc">Appendix A -- Symbols in the Library</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#capacitors_switcap-capacitor" class="toc">Capacitors (switcap-capacitor)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#switches_switcap-switch" class="toc">Switches (switcap-switch)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#independent_voltage_sources_switcap-vsrc" class="toc">Independent Voltage Sources (switcap-vsrc)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#dependent_voltage_sources_switcap-vcvs" class="toc">Dependent Voltage Sources (switcap-vcvs)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#clock_specification_switcap-clock" class="toc">Clock Specification (switcap-clock)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#master_timing_specification_switcap-timing" class="toc">Master Timing Specification (switcap-timing)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#analysis_file_include_switcap-analysis" class="toc">Analysis File Include (switcap-analysis)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#simulation_title_specification_switcap-title" class="toc">Simulation Title Specification (switcap-title)</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#simulation_options_specification_switcap-options" class="toc">Simulation Options Specification (switcap-options)</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#example" class="toc">Example</a></span></div>
  <ul class="toc">
  <li class="level3"><div class="li"><span class="li"><a href="#example_schematics" class="toc">Example Schematics</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#netlist_the_design" class="toc">Netlist the Design</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#run_the_simulation" class="toc">Run the Simulation</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#process_the_results" class="toc">Process the Results</a></span></div></li>
  <li class="level3"><div class="li"><span class="li"><a href="#plot_the_results" class="toc">Plot the Results</a></span></div></li>
  </ul>
  </li>
  <li class="level2"><div class="li"><span class="li"><a href="#document_revision_history" class="toc">Document Revision History</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="geda_gaf_switcap_symbols_and_netlister" id="geda_gaf_switcap_symbols_and_netlister">gEDA/gaf Switcap Symbols and Netlister</a></h1>
  <div class="level1">
  
  <p>
  by: Dan McMahill
  </p>
  
  <p>
  This document is released under <a href="http://www.gnu.org/copyleft/fdl.html"; class="urlextern" title="http://www.gnu.org/copyleft/fdl.html";  rel="nofollow">GFDL</a>
  </p>
  
  <p>
  April 13th, 2003
  </p>
  
  </div>
  <!-- SECTION [1-168] -->
  <h2><a name="overview" id="overview">Overview</a></h2>
  <div class="level2">
  
  <p>
  This document describes the symbol library and gnetlist backend which supports driving SWITCAP simulations from the gEDA/gaf system. SWITCAP is a switched capacitor circuit simulator available from Columbia University. It is used in many classroom and research environments. One drawback to SWITCAP is the lack of a freely available schematic capture frontend. The gEDA/gaf SWITCAP symbol library and gnetlist backend tries to fill that gap.<br/>
   The basic steps involved with using gEDA as the frontend for SWITCAP simulations are:
  </p>
  <ol>
  <li class="level1"><div class="li"> Create schematics of the circuit.</div>
  </li>
  <li class="level1"><div class="li"> Create an analysis file.</div>
  </li>
  <li class="level1"><div class="li"> Extract the netlist.</div>
  </li>
  <li class="level1"><div class="li"> Run the SWITCAP simulation.</div>
  </li>
  <li class="level1"><div class="li"> Run <strong>sw2asc</strong> to extract the results.</div>
  </li>
  <li class="level1"><div class="li"> View the results with <strong>gwave</strong>.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [169-924] -->
  <h2><a name="requirements" id="requirements">Requirements</a></h2>
  <div class="level2">
  
  <p>
  You will need the following programs to be installed:
  </p>
  <ol>
  <li class="level1"><div class="li"> A recent version of gEDA/gaf. To see if your version is recent enough, see if the directory <strong><code>$prefix/share/gEDA/sym/switcap</code></strong> exists. <strong><code>$prefix</code></strong> is the installation prefix for gEDA on your system.</div>
  </li>
  <li class="level1"><div class="li"> SWITCAP. The executable is usually called <strong><code>sw</code></strong>. If you do not have SWITCAP available on your system, you will need to contact Columbia University to obtain a copy. The gEDA/gaf SWITCAP support was tested with SWITCAP Version A.5R Release 21-Sep-87.</div>
  </li>
  <li class="level1"><div class="li"> Although it is optional, you may wish to install a tool which can be used for plotting the output data. SWITCAP produces both <acronym title="American Standard Code for Information Interchange">ASCII</acronym> data listings as well as ugly <acronym title="American Standard Code for Information Interchange">ASCII</acronym> plots (note the release date of the version of SWITCAP used). Suitable tools are:</div>
  <ol>
  <li class="level2"><div class="li"> Gwave. Gwave is an analog waveform viewer. It is fairly basic, but easy to use, includes cursors, and has zoom/pan features. See <strong><a href="http://www.geda.seul.org/"; class="urlextern" title="http://www.geda.seul.org";  rel="nofollow">http://www.geda.seul.org</a></strong></div>
  </li>
  <li class="level2"><div class="li"> Scilab. Similar to matlab. Powerful, but no cursors or panning. See <strong><a href="http://www-rocq.inria.fr/scilab"; class="urlextern" title="http://www-rocq.inria.fr/scilab";  rel="nofollow">http://www-rocq.inria.fr/scilab</a></strong></div>
  </li>
  <li class="level2"><div class="li"> Octave. Similar to matlab. See <strong><a href="http://www.octave.org/"; class="urlextern" title="http://www.octave.org";  rel="nofollow">http://www.octave.org</a></strong></div>
  </li>
  <li class="level2"><div class="li"> Grace. See <strong><a href="http://plasma-gate.weizmann.ac.il/Grace/"; class="urlextern" title="http://plasma-gate.weizmann.ac.il/Grace/";  rel="nofollow">http://plasma-gate.weizmann.ac.il/Grace/</a></strong></div>
  </li>
  </ol>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [925-2127] -->
  <h2><a name="creating_schematics" id="creating_schematics">Creating Schematics</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [2128-2159] -->
  <h3><a name="required_symbols" id="required_symbols">Required Symbols</a></h3>
  <div class="level3">
  
  <p>
  This section assumes you are familiar with using gschem to create and edit schematics. SWITCAP netlisting is only supported for the components contained in the SWITCAP symbol library as well as the ground symbol found in the &lsquo;power&rsquo; library which comes with gEDA. All allowed SWITCAP elements except for subcircuits are supported. You <em>must</em> include the following elements on your schematic:
  </p>
  <ol>
  <li class="level1"><div class="li"> One instance of the switcap-timing symbol. This symbol will set the master clock period for your simulations.</div>
  </li>
  <li class="level1"><div class="li"> One or more instances of the switcap-clock symbol. This symbol defines a clock with a particular phase and period. The reference designator of the clock symbol is used by the switches to set what phase they switch on.</div>
  </li>
  <li class="level1"><div class="li"> One or more instances of the switcap-analysis symbol. This symbol defines an analysis by specifying a file to include in the SWITCAP netlist. By including multiple instances of this symbol, multiple analysis files may be included.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [2160-3152] -->
  <h3><a name="optional_symbols" id="optional_symbols">Optional Symbols</a></h3>
  <div class="level3">
  
  <p>
  You can also optionally add the following SWITCAP special symbols to your schematic:
  </p>
  <ol>
  <li class="level1"><div class="li"> Zero or one instance of the switcap-title symbol. This will add a TITLE: line to the SWITCAP netlist and will appear in the output file.</div>
  </li>
  <li class="level1"><div class="li"> Zero or one instance of the switcap-options symbol. By editing the OPTIONS attribute on this symbol you can set the various options which can be passed to SWITCAP.</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [3153-3574] -->
  <h3><a name="net_names" id="net_names">Net Names</a></h3>
  <div class="level3">
  
  <p>
  When creating schematics to drive SWITCAP, you should name all nets that you wish to plot. To avoid possible conflicts with unnamed nets, you should avoid using purely numerical names for nets because all unnamed nets will be assigned (somewhat randomly) numbers without checking for possible conflicts with explicitly named nets. SWITCAP limits the length of node names to 7 characters.
  </p>
  
  </div>
  <!-- SECTION [3575-3983] -->
  <h3><a name="switches" id="switches">Switches</a></h3>
  <div class="level3">
  
  <p>
  When placing switches on your schematic, you will need to define which clock they are controlled with. This is done by setting the clock attribute on the switch to the reference designator of the clock which should control it.
  </p>
  
  </div>
  <!-- SECTION [3984-4230] -->
  <h2><a name="extracting_the_switcap_netlist" id="extracting_the_switcap_netlist">Extracting the SWITCAP Netlist</a></h2>
  <div class="level2">
  
  <p>
  To extract the SWITCAP netlist, run: 
  </p>
  <pre class="code">gnetlist -g switcap -o test.scn file1.sch [file2.sch ...]</pre>
  
  <p>
  For the example file contained in this archive, you can run: 
  </p>
  <pre class="code">gnetlist -g switcap -o example.scn ckt.sch clocks.sch analysis.sch</pre>
  
  <p>
  The netlist will be left in <strong>example.scn</strong>.
  </p>
  
  </div>
  <!-- SECTION [4231-4570] -->
  <h2><a name="running_switcap" id="running_switcap">Running SWITCAP</a></h2>
  <div class="level2">
  
  <p>
  I typically use something like: 
  </p>
  <pre class="code">printf &quot;example.scn\nexample.out\n&quot; | sw</pre>
  
  <p>
  so I can use command history to rerun SWITCAP without having to manually type the file names each time.<br/>
   Refer to the SWITCAP manual for more details.
  </p>
  
  </div>
  <!-- SECTION [4571-4838] -->
  <h2><a name="appendix_a_--_symbols_in_the_library" id="appendix_a_--_symbols_in_the_library">Appendix A -- Symbols in the Library</a></h2>
  <div class="level2">
  
  </div>
  <!-- SECTION [4839-4887] -->
  <h3><a name="capacitors_switcap-capacitor" id="capacitors_switcap-capacitor">Capacitors (switcap-capacitor)</a></h3>
  <div class="level3">
  
  <p>
  Ideal capacitor. Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>C</strong>=capacitance. Required. Specifies filename to be included.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes</strong>=reference designator. Required. Must start with &ldquo;C&rdquo; and be unique.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [4888-5108] -->
  <h3><a name="switches_switcap-switch" id="switches_switcap-switch">Switches (switcap-switch)</a></h3>
  <div class="level3">
  
  <p>
  Ideal switch. Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>clock</strong>=Controlling clock. Required. Specifies which clock controls this switch.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes</strong>=reference designator. Required. Must start with &ldquo;S&rdquo; and be unique.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5109-5340] -->
  <h3><a name="independent_voltage_sources_switcap-vsrc" id="independent_voltage_sources_switcap-vsrc">Independent Voltage Sources (switcap-vsrc)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>refdes</strong>=reference designator. Required. Must start with &ldquo;V&rdquo; and be unique.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5341-5488] -->
  <h3><a name="dependent_voltage_sources_switcap-vcvs" id="dependent_voltage_sources_switcap-vcvs">Dependent Voltage Sources (switcap-vcvs)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>gain</strong>=gain. Required. Specifies the gain of the controlled source.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes</strong>=reference designator. Required. Must start with &ldquo;E&rdquo; and be unique.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5489-5708] -->
  <h3><a name="clock_specification_switcap-clock" id="clock_specification_switcap-clock">Clock Specification (switcap-clock)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>PSTART</strong>=starting clock phase. Required. Specifies on what phase of the master clock this clock turns on.</div>
  </li>
  <li class="level1"><div class="li"> <strong>PSTOP</strong>=ending clock phase. Required. Specifies on what phase of the master clock this clock turns off.</div>
  </li>
  <li class="level1"><div class="li"> <strong>PERIOD</strong>=clock period. Required. Specifies the period of the clock in terms of master clock cycles.</div>
  </li>
  <li class="level1"><div class="li"> <strong>refdes</strong>=reference designator. Required. The switches that are controlled by this clock will refer to it by the reference designator. As such, avoid running any reference designator renumbering tools.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [5709-6302] -->
  <h3><a name="master_timing_specification_switcap-timing" id="master_timing_specification_switcap-timing">Master Timing Specification (switcap-timing)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> PERIOD=clock period. Required. Specifies the period of the master clock in seconds.</div>
  </li>
  </ul>
  
  <p>
   Only a single instance of this symbol is allowed.
  </p>
  
  </div>
  <!-- SECTION [6303-6509] -->
  <h3><a name="analysis_file_include_switcap-analysis" id="analysis_file_include_switcap-analysis">Analysis File Include (switcap-analysis)</a></h3>
  <div class="level3">
  
  <p>
  This symbol will cause a specified file containing SWITCAP analysis commands to be included in the output netlist. Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>file</strong>=filename. Required. Specifies filename to be included.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [6510-6756] -->
  <h3><a name="simulation_title_specification_switcap-title" id="simulation_title_specification_switcap-title">Simulation Title Specification (switcap-title)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>TITLE</strong>=switcap title. Required. Specifies the TITLE line for the SWITCAP netlist.</div>
  </li>
  </ul>
  
  <p>
   Only a single instance of this symbol is allowed.
  </p>
  
  </div>
  <!-- SECTION [6757-6966] -->
  <h3><a name="simulation_options_specification_switcap-options" id="simulation_options_specification_switcap-options">Simulation Options Specification (switcap-options)</a></h3>
  <div class="level3">
  
  <p>
  Attributes:
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>OPTIONS</strong>=switcap options. Required. Specifies the OPTIONS line for the SWITCAP netlist. See the SWITCAP manual for allowed values.</div>
  </li>
  </ul>
  
  <p>
   Only a single instance of this symbol is allowed.
  </p>
  
  </div>
  <!-- SECTION [6967-7229] -->
  <h2><a name="example" id="example">Example</a></h2>
  <div class="level2">
  
  <p>
  This appendix provides a simple example of the entire process of generating a schematic, producing a SWITCAP netlist, running a simulation, and plotting the results. 
  </p>
  <table class="inline">
  	<tr>
  		<td> <a href="_detail/geda_switcap_figure1.html" class="media" title="geda:switcap_figure1.jpg"><img src="_media/geda_switcap_figure1.jpg" class="media" title="switcap_figure1.jpg" alt="switcap_figure1.jpg" /></a> </td>
  	</tr>
  	<tr>
  		<td> <a href="_detail/geda_switcap_figure2.html" class="media" title="geda:switcap_figure2.jpg"><img src="_media/geda_switcap_figure2.jpg" class="media" title="switcap_figure2.jpg" alt="switcap_figure2.jpg" /></a> </td>
  	</tr>
  	<tr>
  		<td> <a href="_detail/geda_switcap_figure3.html" class="media" title="geda:switcap_figure3.jpg"><img src="_media/geda_switcap_figure3.jpg" class="media" title="switcap_figure3.jpg" alt="switcap_figure3.jpg" /></a> </td>
  	</tr>
  	<tr>
  		<td> <a href="_detail/geda_switcap_figure4.html" class="media" title="geda:switcap_figure4.jpg"><img src="_media/geda_switcap_figure4.jpg" class="media" title="switcap_figure4.jpg" alt="switcap_figure4.jpg" /></a> </td>
  	</tr>
  </table>
  <br />
  
  <p>
   Figure 5/6: Simulation Results - Transient MISSING
  </p>
  
  </div>
  <!-- SECTION [7230-7605] -->
  <h3><a name="example_schematics" id="example_schematics">Example Schematics</a></h3>
  <div class="level3">
  
  <p>
  <strong>Figure 1</strong> shows the schematic of a simple switched capacitor circuit. Note that some switches, S1 and S3 for example, are controlled by CLK1 while others, S2 and S4 for example, are controlled by the complement of CLK1 (#CLK1).<br/>
   <strong>Figure 2</strong> shows the definition of a clock and the master clock. Here we define a master clock period (mcp) of 1.0 Î¼s in the timing block. In the clock definition symbol, we define a clock called CLK1 that has a period equal to 1 master clock period (mcp). The phase of CLK1 turning on switches is 0 and the phase of CLK1 turning off switches is 3/8 mcp. Additional clock phases can be defined by creating more instances of the clock definition symbol.<br/>
   <strong>Figure 3</strong> shows an instantiation of the title block symbol which will cause &ldquo;my title&rdquo; to be used in the TITLE line in the SWITCAP netlist. Figure 3 also shows an instantiation of an analysis block which directs the netlister to include the contents of the file test.ana in the output netlist. <strong>Figure 4</strong> shows the contents of the test.ana file.
  </p>
  
  </div>
  <!-- SECTION [7606-8677] -->
  <h3><a name="netlist_the_design" id="netlist_the_design">Netlist the Design</a></h3>
  <div class="level3">
  
  <p>
  To netlist the design, run: 
  </p>
  <pre class="code">gnetlist -g switcap -o example.scn ckt.sch clocks.sch analysis.sch</pre>
  
  </div>
  <!-- SECTION [8678-8815] -->
  <h3><a name="run_the_simulation" id="run_the_simulation">Run the Simulation</a></h3>
  <div class="level3">
  
  <p>
  Run the simulation with: 
  </p>
  <pre class="code">printf &quot;example.scn\nexample.out\n&quot; | sw</pre>
  
  </div>
  <!-- SECTION [8816-8924] -->
  <h3><a name="process_the_results" id="process_the_results">Process the Results</a></h3>
  <div class="level3">
  
  <p>
  Convert the SWITCAP output file to something gwave can read by running: 
  </p>
  <pre class="code">sw2asc example.out</pre>
  
  </div>
  <!-- SECTION [8925-9059] -->
  <h3><a name="plot_the_results" id="plot_the_results">Plot the Results</a></h3>
  <div class="level3">
  
  <p>
  Start up the gwave program and load the first sinusoidal steady state result by running: 
  </p>
  <pre class="code">gwave example.out.SSS.1.asc</pre>
  
  <p>
  Drag the two waveforms onto the two waveform panels and change the x-axis to a log scale. Figure 5 shows the output. Start up the gwave program and load the transient result by running: 
  </p>
  <pre class="code">gwave example.out.TRAN.1.asc</pre>
  
  </div>
  <!-- SECTION [9060-9446] -->
  <h2><a name="document_revision_history" id="document_revision_history">Document Revision History</a></h2>
  <div class="level2">
  <table class="inline">
  	<tr>
  		<td> April 13th, 2003 </td><td> Created switcap.tex </td>
  	</tr>
  </table>
  <br />
  
  </div>
  <!-- SECTION [9447-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_style_guide.html
  
  Index: geda_style_guide.html
  ===================================================================
  <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
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   lang="en" dir="ltr">
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    <title>geda:style_guide</title>
    <meta name="generator" content="DokuWiki Release 2006-03-09" />
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  </head>
  <body>
  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#style_guide" class="toc">Style Guide</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#downloading_installing_pavuk" class="toc">Downloading/Installing pavuk</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#downloading_installing_htmldoc" class="toc">Downloading/Installing HTMLDOC</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#for_both_existing_and_new_documents" class="toc">For both existing and new documents</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#for_new_documents" class="toc">For new documents:</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#for_existing_documents" class="toc">For existing documents:</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="style_guide" id="style_guide">Style Guide</a></h1>
  <div class="level1">
  
  <p>
  <span class="hilited">This is definitely a work in progress.</span><br/>
   All documentation is eventually going to be made available as both <acronym title="HyperText Markup Language">HTML</acronym> and <acronym title="Portable Document Format">PDF</acronym>.<br/>
   The problem is to convert the gEDA wiki&rsquo;s Dokuwiki-pages (i.e., <acronym title="Extensible HyperText Markup Language">XHTML</acronym>) into a format that can be converted into <acronym title="Portable Document Format">PDF</acronym>.<br/>
   The ideal path would be to use the pavuk application to mine the gEDA wiki, converting the <acronym title="Extensible HyperText Markup Language">XHTML</acronym> wiki-pages into <acronym title="HyperText Markup Language">HTML</acronym> pages, and then use the HTMLDOC application to convert the <acronym title="HyperText Markup Language">HTML</acronym> pages to <acronym title="Portable Document Format">PDF</acronym>.<br/>
  
  </p>
  
  </div>
  <!-- SECTION [1-472] -->
  <h2><a name="downloading_installing_pavuk" id="downloading_installing_pavuk">Downloading/Installing pavuk</a></h2>
  <div class="level2">
  
  <p>
  pavuk is a function-testing, performance-measuring, site-mirroring, web spider that is widely portable and capable of using scenarios to process a wide range of web transactions, including ssl and forms.<br/>
   pavuk is hosted on SourceForge at <a href="http://sourceforge.net/projects/pavuk"; class="urlextern" title="http://sourceforge.net/projects/pavuk";  rel="nofollow">http://sourceforge.net/projects/pavuk</a>. Simply check if your distribution already includes the latest version of pavuk (pavuk-0.9.34 used for the current wiki), and download/install if necessary.<br/>
   pavuk comes as an RPM, a tar-ball, and a compressed tar-ball. Don&rsquo;t install from the RPM, as this uses dated library dependencies and may not build on newer distributions.<br/>
   pavuk has both a command-line interface and a <acronym title="Graphical User Interface">GUI</acronym> interface.
  </p>
  
  </div>
  <!-- SECTION [473-1190] -->
  <h2><a name="downloading_installing_htmldoc" id="downloading_installing_htmldoc">Downloading/Installing HTMLDOC</a></h2>
  <div class="level2">
  
  <p>
  HTMLDOC converts <acronym title="HyperText Markup Language">HTML</acronym> files and web pages into indexed <acronym title="HyperText Markup Language">HTML</acronym>, PostScript, and <acronym title="Portable Document Format">PDF</acronym> files suitable for on-line viewing and printing.<br/>
   HTMLDOC is hosted at <a href="http://www.easysw.com/htmldoc/"; class="urlextern" title="http://www.easysw.com/htmldoc/";  rel="nofollow">http://www.easysw.com/htmldoc/</a>, and may be downloaded/installed under the open-source license for non-commercial applications. Simply check if you distribution already includes HTMLDOC version htmldoc-1.8-27 or later, and install as appropriate. Note that RPM distributions are available, so that your normal package install/update utilities may already contain HTMLDOC (e.g., htmldoc-1.8.27 is in Fedora Core 4 extras repository and may be installed using yum).<br/>
   HTMLDOC version htmldoc-1.8.26 is broken, it will not generate appropriate <acronym title="Portable Document Format">PDF</acronym> documents.<br/>
   Note one limitation of HTMLDOC. It is based on <acronym title="HyperText Markup Language">HTML</acronym> 3.o, not <acronym title="HyperText Markup Language">HTML</acronym> 4.01. Many <acronym title="HyperText Markup Language">HTML</acronym> 4.01 tags are not recognized by HTMLDOC.<br/>
   HTMLDOC is both a <acronym title="Graphical User Interface">GUI</acronym> application and a command-line application. Use it as you feel most comfortable.
  </p>
  
  </div>
  <!-- SECTION [1191-2172] -->
  <h2><a name="for_both_existing_and_new_documents" id="for_both_existing_and_new_documents">For both existing and new documents</a></h2>
  <div class="level2">
  
  <p>
  The following are meant to stimulate discussion on document style:
  </p>
  <ol>
  <li class="level1"><div class="li"> Consider that the document will be exported for inclusion on the &ldquo;gEDA Tools Suite CD-ROM&rdquo; as <acronym title="Extensible HyperText Markup Language">XHTML</acronym> and/or <acronym title="Portable Document Format">PDF</acronym>. Examples:</div>
  <ul>
  <li class="level2"><div class="li"> <a href="http://geda.seul.org/wiki/?do=export_raw"; class="urlextern" title="http://geda.seul.org/wiki/?do=export_raw";  rel="nofollow">http://geda.seul.org/wiki/?do=export_raw</a> will generate the gEDA Project Wiki&rsquo;s start page as plain text. Simply use your browser to copy to a text file and include on the CD-ROM image.</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://geda.seul.org/wiki/?do=export_xhtml"; class="urlextern" title="http://geda.seul.org/wiki/?do=export_xhtml";  rel="nofollow">http://geda.seul.org/wiki/?do=export_xhtml</a> will generate the gEDA Project Wiki&rsquo;s start page as valid <acronym title="Extensible HyperText Markup Language">XHTML</acronym>. Simply use your browser to &ldquo;Save Page As...&rdquo;, and name the file {filename}.html. Note that the URLs in this file are NOT relative to this file, but are as they would be found on the gEDA Project Wiki.</div>
  </li>
  <li class="level2"><div class="li"> <a href="http://geda.seul.org/wiki/?do=export_xhtmlbody"; class="urlextern" title="http://geda.seul.org/wiki/?do=export_xhtmlbody";  rel="nofollow">http://geda.seul.org/wiki/?do=export_xhtmlbody</a> will generate the gEDA Project Wiki&rsquo;s start page as valid rendered <acronym title="Extensible HyperText Markup Language">XHTML</acronym>. Simply use your browser to &ldquo;Save Page As...&rdquo;, and name the file {filename}.html. Note that the URLs in this file are NOT relative to this file, but are as they would be found on the gEDA Project Wiki.</div>
  </li>
  <li class="level2"><div class="li"> The following sequence of commands will retreive a gEDA Project Wiki page (for a list of the gEDA Project Wiki&rsquo;s pages, use the Index button at the bottom of the page) from the &ldquo;geda&rdquo; namespace (when new wiki-pages are created, we <em class="u">explicitly</em> create them in the &ldquo;geda&rdquo; namespace) and convert that page into a <acronym title="Portable Document Format">PDF</acronym> document:<br/>
   <pre STYLE="background : Lightgreen;margin-left : 2em"><font size="+0">% wget --convert-links -O {page-name}.wget &quot;http://geda.seul.org/wiki/geda:{page-name}?do=export_html&quot;
  % sed -e 's/\&amp;amp;/\&amp;/g' {page-name}.wget &gt; {page-name}.sed
  % iconv -f utf-8 -t iso-8859-1 {page-name}.sed &gt; {page-name}.iconv
  % htmldoc {page-name}.iconv -t pdf14 --webpage --no-title --linkstyle underline --size letter --left 1.00in \\
    --right 0.50in --top 0.50in --bottom 0.50in --header .t. --footer . --nup 1 --tocheader .t. --tocfooter ..i \\
    --portrait --color --no-pscommands --no-xrxcomments --compression=1 --jpeg=0 --fontsize 11.0 --fontspacing 1.2 \\
    --headingfont Helvetica --bodyfont Times --headfootsize 11.0 --headfootfont Helvetica --charset iso-8859-1 \\
    --links --no-embedfonts --pagemode document --pagelayout single --firstpage p1 --pageeffect none \\
    --pageduration 10 --effectduration 1.0 --no-encryption --permissions all --owner-password &quot;&quot;
    --user-password &quot;&quot; --browserwidth 680 -f {page-name}.pdf</font></pre> <br/>
   where <strong><code>{page-name}</code></strong> is the wiki&rsquo;s page name as seen in the upper-left corner of the wiki.</div>
  </li>
  </ul>
  </li>
  </ol>
  
  <p>
   For example, you would replace {page-name} above with the following for the related wiki-page:
  </p>
  <ul>
  <li class="level1"><div class="li"> start &ndash; The wiki&rsquo;s main page, at <a href="http://geda.seul.org/wiki/"; class="urlextern" title="http://geda.seul.org/wiki/";  rel="nofollow">http://geda.seul.org/wiki/</a>.</div>
  </li>
  <li class="level1"><div class="li"> geda:style_guide &ndash; This wiki-page, at <a href="http://geda.seul.org/wiki/geda:style_guide"; class="urlextern" title="http://geda.seul.org/wiki/geda:style_guide";  rel="nofollow">http://geda.seul.org/wiki/geda:style_guide</a>.</div>
  </li>
  <li class="level1"><div class="li"> geda:faq &ndash; The wiki&rsquo;s <acronym title="Frequently Asked Questions">FAQ</acronym> page, at <a href="http://geda.seul.org/wiki/geda:faq"; class="urlextern" title="http://geda.seul.org/wiki/geda:faq";  rel="nofollow">http://geda.seul.org/wiki/geda:faq</a></div>
  </li>
  </ul>
  
  <p>
   A <span class="hilited">sample script</span> to convert a single wiki-page into a <acronym title="Portable Document Format">PDF</acronym> document.<br/>
   A <span class="hilited">sample script</span> to convert multiple wiki-pages into a single <acronym title="Portable Document Format">PDF</acronym> document.
  </p>
  
  <p>
  An example of the current (as of 08 May 2006) version of the Wiki, <a href="http://www.offramp.com/wiki/FC5_files/Wiki.pdf"; class="urlextern" title="http://www.offramp.com/wiki/FC5_files/Wiki.pdf";  rel="nofollow">converted to PDF</a>.
  </p>
  
  </div>
  <!-- SECTION [2173-5272] -->
  <h2><a name="for_new_documents" id="for_new_documents">For new documents:</a></h2>
  <div class="level2">
  
  <p>
  The following are meant to stimulate discussion on document style:
  </p>
  <ol>
  <li class="level1"><div class="li"> You must &ldquo;own&rdquo; all content in the document. If you do not &ldquo;own&rdquo; the content, you must get explicit permission from the &ldquo;owner&rdquo; to copy the content to the gEDA Project Wiki (see below). Documents on the gEDA Project Wiki should be stand-alone, in the event the source document web-site disappears.</div>
  </li>
  <li class="level1"><div class="li"> <strong>All</strong> document contents are to be hosted on the gEDA Project Wiki. Images and other media files are to be uploaded to the wiki, and linked to. Do NOT link to external sites unless absolutely necessary.</div>
  </li>
  <li class="level1"><div class="li"> All documents are to be maintained in the &ldquo;geda&rdquo; <a href="http://wiki.splitbrain.org/wiki:namespaces"; class="urlextern" title="http://wiki.splitbrain.org/wiki:namespaces";  rel="nofollow">namespace</a>. If your document would take advantage of a separate namespace, ask Ales if &ldquo;geda:sub-namespace&rdquo; is acceptable. This would be appropriate for very large documents with multiple chapters and lots of images. Such a namespace structure would allow the document to be &ldquo;broken&rdquo; into chapters for easier navigation by the user (see <a href="http://wiki.splitbrain.org/wiki:index"; class="urlextern" title="http://wiki.splitbrain.org/wiki:index";  rel="nofollow">Index</a> for more details).</div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [5273-6383] -->
  <h2><a name="for_existing_documents" id="for_existing_documents">For existing documents:</a></h2>
  <div class="level2">
  
  <p>
  The following are meant to stimulate discussion on document style:
  </p>
  <ol>
  <li class="level1"><div class="li"> </div>
  </li>
  </ol>
  
  </div>
  <!-- SECTION [6384-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_suse_10.html
  
  Index: geda_suse_10.html
  ===================================================================
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  <h1><a name="suse_10.0_install_notes" id="suse_10.0_install_notes">Suse 10.0 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-39] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  First off, I suggest you use the installer with date code 20051203 (or later). The 2005080X installer may not work with SuSE-10.0 without major upfront preparation. 
  </p>
  
  <p>
  Secondly, if you are installing gEDA onto a pre-existing SuSE system, make sure your system runs the Gnome desktop, or at least has the Gnome libraries installed.  If you have a KDE desktop system, unpredictable things may happen with the installer.
  </p>
  
  <p>
  The remainder of these instructions describe how to build your SuSE system so that you may install gEDA.  If you already have gEDA built (and it&rsquo;s a Gnome desktop), you can use YaST to install any of the below-mentioned packages you might be missing from your original install.
  </p>
  
  <p>
  When installing SuSE-10.0 using YaST, click on the â??changeâ?? button when YaST shows you your configuration. Select â??softwareâ?? â?? â??detailsâ??. Then add the following packages to your installation list:
  </p>
  <ul>
  <li class="level1"><div class="li"> C/C++ tools</div>
  </li>
  <li class="level1"><div class="li"> Kernal development</div>
  </li>
  <li class="level1"><div class="li"> Gnome development</div>
  </li>
  <li class="level1"><div class="li"> KDE development</div>
  </li>
  <li class="level1"><div class="li"> TCL/Tk development</div>
  </li>
  </ul>
  
  <p>
   Then change the filter to search for and install the following packages:
  </p>
  <ul>
  <li class="level1"><div class="li"> Gtk-devel</div>
  </li>
  <li class="level1"><div class="li"> Termcap</div>
  </li>
  <li class="level1"><div class="li"> Ncurses-devel</div>
  </li>
  <li class="level1"><div class="li"> wxGTK-devel</div>
  </li>
  </ul>
  
  <p>
   Once these packages are installed, the installer should run to completion. 
  </p>
  
  </div>
  <!-- SECTION [40-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_suse_9.html
  
  Index: geda_suse_9.html
  ===================================================================
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  <h1><a name="installer_2005080x_on_suse_9.3_install_notes" id="installer_2005080x_on_suse_9.3_install_notes">Installer 2005080X on Suse 9.3 install notes</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-59] -->
  <h2><a name="prerequisites" id="prerequisites">Prerequisites:</a></h2>
  <div class="level2">
  
  <p>
  When installing SuSE using YaST, click on the â??changeâ?? button when YaST shows you your configuration. Select â??softwareâ?? â?? â??detailsâ??. Then add the following packages to your installation list:
  </p>
  <ul>
  <li class="level1"><div class="li"> C/C++ tools</div>
  </li>
  <li class="level1"><div class="li"> Kernal development</div>
  </li>
  <li class="level1"><div class="li"> Gnome development</div>
  </li>
  <li class="level1"><div class="li"> KDE development</div>
  </li>
  <li class="level1"><div class="li"> TCL/Tk development</div>
  </li>
  </ul>
  
  <p>
   Then change the filter to search for and install the following packages:
  </p>
  <ul>
  <li class="level1"><div class="li"> Gtk-devel</div>
  </li>
  <li class="level1"><div class="li"> Termcap</div>
  </li>
  <li class="level1"><div class="li"> Ncurses-devel</div>
  </li>
  <li class="level1"><div class="li"> wxGTK-devel</div>
  </li>
  </ul>
  
  <p>
   Once these packages are installed, the installer should run to completion.
  </p>
  
  <p>
  <span class="hilited">More SuSE info to come. . . . .</span>
  </p>
  
  </div>
  <!-- SECTION [60-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_syntax_features.html
  
  Index: geda_syntax_features.html
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  <h1><a name="syntax_features" id="syntax_features">Syntax features</a></h1>
  <div class="level1">
  
  <p>
  The new gEDA Project Wiki pages are hosted using Dokuwiki version 09 March 2006. This wiki-engine has several enhancements:
  </p>
  <ul>
  <li class="level1"><div class="li"> Bug fixes.</div>
  </li>
  <li class="level1"><div class="li"> A new toolbar in the editor.</div>
  </li>
  <li class="level1"><div class="li"> <a href="http://wiki.splitbrain.org/wiki:syntax"; class="urlextern" title="http://wiki.splitbrain.org/wiki:syntax";  rel="nofollow">Syntax</a> enhancements.</div>
  </li>
  <li class="level1"><div class="li"> Updates to the <a href="http://wiki.splitbrain.org/wiki:search"; class="urlextern" title="http://wiki.splitbrain.org/wiki:search";  rel="nofollow">Search</a> feature. You can now search for exact phrases by enclosing them with double quotes, and use &ldquo;*&rdquo; wildcard searches.</div>
  </li>
  <li class="level1"><div class="li"> Google <a href="http://wiki.splitbrain.org/wiki:sitemap"; class="urlextern" title="http://wiki.splitbrain.org/wiki:sitemap";  rel="nofollow">sitemap</a> support. Your edited content will be indexed by Google much faster.</div>
  </li>
  <li class="level1"><div class="li"> You can upload and embed <a href="http://wiki.splitbrain.org/wiki:images"; class="urlextern" title="http://wiki.splitbrain.org/wiki:images";  rel="nofollow">other files</a> into the pages using the MediaPopup feature on the toolbar in the editor (including image files, flash files, <acronym title="Portable Document Format">PDF</acronym> files, etc.). Please note that image/media files can not be removed once uploaded by an author.</div>
  </li>
  <li class="level1"><div class="li"> Footnotes.</div>
  </li>
  <li class="level1"><div class="li"> Larger global cache, allowing for larger documents (currently set to 20 <acronym title="Megabyte">MB</acronym>).</div>
  </li>
  <li class="level1"><div class="li"> You can subscribe to e-mail pagechange notification, on a wiki-page by wiki-page basis. If you are interested in monitoring the changes made by others to a spicific page, simply press the &ldquo;Subscribe Changes&rdquo; button at the bottom of the wiki-page. To unsubscribe from a wiki-page, simply press the &ldquo;Unsubscribe Changes&rdquo; button.</div>
  </li>
  <li class="level1"><div class="li"> URLs are now &ldquo;pretty&rdquo;.</div>
  </li>
  <li class="level1"><div class="li"> Breadcrumbs (i.e., the line at the top of the browser&rsquo;s window that starts with &ldquo;Trace:&rdquo;. This is a &ldquo;where are you&rdquo; indicator.</div>
  </li>
  <li class="level1"><div class="li"> Wiki-pages can be <a href="http://wiki.splitbrain.org/wiki:export"; class="urlextern" title="http://wiki.splitbrain.org/wiki:export";  rel="nofollow">exported</a> to different formats (e.g., plain-text, simple <acronym title="Extensible HyperText Markup Language">XHTML</acronym> (the page without navigational elements), rendered <acronym title="Extensible HyperText Markup Language">XHTML</acronym> (no head or body tags), <acronym title="Hyper Text Transfer Protocol">HTTP</acronym>).</div>
  </li>
  <li class="level1"><div class="li"> The <code>&lt;code&gt;&lt;/code&gt;</code> tag supports syntax highlighting for numerous programming languages.</div>
  </li>
  <li class="level1"><div class="li"> A playground for authors to &ldquo;play&rdquo; with new features, before implimenting on the wiki&rsquo;s pages.</div>
  </li>
  <li class="level1"><div class="li"> Control of Dokuwiki&rsquo;s <a href="http://wiki.splitbrain.org/wiki:caching#purging_the_cache"; class="urlextern" title="http://wiki.splitbrain.org/wiki:caching#purging_the_cache";  rel="nofollow">caching</a> operations. This is important to wiki-page authors, as sometimes a page gets cached by Dokuwiki on the server, and needs to be purged. Remember, what the author sees may not be what others see.<br/>
   This is different than your browser&rsquo;s cache, which may occassionally need to be flushed. For example, when the <acronym title="Hypertext Preprocessor">PHP</acronym> global memory limit is exceeded, that wiki-page can&rsquo;t be displayed, even if the <acronym title="Hypertext Preprocessor">PHP</acronym> global memory limit is changed on the server. You would need to flush your browser&rsquo;s cache to load and view the wiki-page.</div>
  </li>
  </ul>
  
  </div>
  </div>
  </body>
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  1.1                  eda/geda/gaf/docs/wiki/geda_systemc_netlister_readme.html
  
  Index: geda_systemc_netlister_readme.html
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  <h1><a name="systemc_netlister_readme" id="systemc_netlister_readme">SystemC netlister README</a></h1>
  <div class="level1">
  <pre class="code">TITLE:
  
       Gnetlist SystemC Backend
  
  OBJECTIVE:
  
       Transform a geda schematic into a transaction based structural systemc module.
  
  LIMITATIONS:
  
       1.- Only transaction based wires are considered (wire_name&lt;user_type&gt;).
       2.- Unnamed wires are eliminated.
       3.- In/out ports have to be inserted manually in the sysc code.
       4.- Duplicated include headers are not eliminated by the backend.
       5.- The maximum number of object constructor parameters is 31 (attr1-&gt;attr31).
  
  LINKS:
  
       GPL Electronic Design Automation (geda-gnetlist): http://www.geda.seul.org
       SystemC: http://www.systemc.org
  
  ACK:
  
       Based on gnet-verilog.scm by Mike Jarabek.
  
  EXAMPLE:
  
       Schematic:
  
       src1                         alg1                      snk1
       ______________               _______________           _______________
       | source     |  a&lt;user_type&gt; |  algorithm  |  b&lt;float&gt; |        sink |
       |         OUT|__ _________ __|IN        OUT|__ _____ __|IN           |
       |            |               |             |           |             |
       | infile.data|               |             |           | outfile.data|
       |____________|               |_____________|           |_____________|
  
  
       Attributes:
  
              Schematic:
                       module_name=test_sch2sysc
       
              Wires:
                       netname=a&lt;user_type&gt;
                       netname=b&lt;float&gt;
              Symbols:
                       refdes=src1 attr1=infile.data
                       refdes=alg1
                       refdes=snk1 attr1=outfile.data
                       refdes=pina
                       refdes=pinb
  
       SystemC:
  
  		#include &quot;systemc.h&quot;
  		#include &quot;sink.h&quot;
  		#include &quot;source.h&quot;
  		#include &quot;algorithm.h&quot;
  
  		SC_MODULE (test_sch2sysc)
  		{
  			/* Port directions begin here */
  
  		 	/* Wires from the design */
  			sc_signal&lt;float&gt; b;
  			sc_signal&lt;packet_type&gt; a;
  	
  			/* Package instantiations */
  			sink snk1;
  			source src1;
  			algorithm alg1;
  
  			SC_CTOR(test_sch2sysc):
  				snk1(&quot;snk1&quot;,&quot;outfile.data&quot;),
  				src1(&quot;src1&quot;,&quot;infile.data&quot;),
  				alg1(&quot;alg1&quot;)
  			{
  				snk1.IN(b);
  			  	src1.OUT(a);
  			  	alg1.IN(a);
  			  	alg1.OUT(b);
  			}
  		};
  
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_tasks.html
  
  Index: geda_tasks.html
  ===================================================================
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  <h1><a name="geda_tasks" id="geda_tasks">gEDA Tasks</a></h1>
  <div class="level1">
  
  <p>
  gEDA is run by volunteers, so these are volunteer (read: unpaid) tasks. Please consider helping out. Thank you.
  </p>
  <ul>
  <li class="level1"><div class="li"> <strong>Documentation Writers/Editors</strong><br/>
   Somebody is needed to act as an editor for the gEDA documentation effort. Basically this person would take whatever documentation already exists and/or is currently being written and formats it into something presentable. This individual does not write the actual documentation, but would instead perform editorial work. People who want to write the actual documentation are also needed.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Publicity Manager</strong><br/>
   Somebody is needed to do publicity for the gEDA project. This consists of posting release updates to the various Linux/Unix websites (like Freshmeat or LWN)</div>
  </li>
  <li class="level1"><div class="li"> <strong>Netlist Hacker</strong><br/>
   Somebody who is familiar with the generation/management of netlists is needed to help work on and improve gnetlist. Whether the existing gnetlist is used or if a total rewrite is needed is always an open option. Must be extremely familiar with UNIX/C/C++ programming.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Symbol Library Hacker</strong><br/>
   Somebody is needed to help get the symbol library up to the current symbol <acronym title="specification">spec</acronym>. This individual would also help in the integration of new symbols and making sure that they meet the current symbol <acronym title="specification">spec</acronym>. The task of getting the symbol library up to <acronym title="specification">spec</acronym> is a combination of manual effort and automated updating (this sort of automated updating lends itself very well to a person with shell/perl scripting familiarity).</div>
  </li>
  <li class="level1"><div class="li"> <strong>geda <acronym title="Graphical User Interface">GUI</acronym> Hacker</strong><br/>
   Somebody who knows C, UNIX, and gtk+ programming is needed to work on the gEDA <acronym title="Graphical User Interface">GUI</acronym> (the program named geda). This program has been stalled for the past year due to the lack of manpower. Whether the existing geda is used or a total rewrite is needed is always an open option.</div>
  </li>
  <li class="level1"><div class="li"> <strong>UNIX Port Testers</strong><br/>
   People are always needed to test gEDA on different and new UNIX like operating systems. This person would basically download a new release and make sure it works on their platform of choice. Any problems found would be then submitted to the appropriate gEDA author.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Windows Port Hacker/Manager</strong><br/>
   Somebody with expertise building and testing gEDA on UNIX systems and familiarity with the <acronym title="Microsoft">MS</acronym> Windows 95/98/NT platform is needed to manage the gEDA Windows port. Testing, bug fixing, packaging, and releasing of gEDA on the Windows platform would be the primary responsibility of this person. This task requires a person who knows C, gtk+, UNIX, and <acronym title="Microsoft">MS</acronym> Windows programming. The Windows port will NOT move forward if this task is not filled.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Release Hacker</strong><br/>
   Somebody who wants to create and manage releases is needed. Releases occur when the code is ready to be released, so there&rsquo;s no marketing pressure. This task requires gEDA building/testing familiarity as well perhaps some minor code hacking.</div>
  </li>
  <li class="level1"><div class="li"> <strong>Website/Mirror Hacker</strong><br/>
   Somebody to watch over the mirrors and maybe do some <acronym title="HyperText Markup Language">HTML</acronym> hacking is needed. There are currently three websites which need to be monitored and occasionally fixed. The person would also have influence in the changing/expansion of the gEDA website. Duties would be split among the current webmasters.</div>
  </li>
  </ul>
  
  </div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_todos.html
  
  Index: geda_todos.html
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#todo" class="toc">ToDo</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#things_to_be_done_before_the_next_release" class="toc">Things to be done before the next release</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#longer_term_upgrades_desired_for_specific_tools" class="toc">Longer term upgrades desired for specific tools</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#ideas_for_new_tools_or_geda_suite-wide_enhancements" class="toc">Ideas for new tools or gEDA Suite-wide enhancements</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="todo" id="todo">ToDo</a></h1>
  <div class="level1">
  
  <p>
  These lists are meant to provide developers a reminder of undone projects. It is also a wish list capturing userâ??s desires for new features. New developers can also look here for projects which they might be interested in working on.
  </p>
  
  </div>
  <!-- SECTION [1-256] -->
  <h2><a name="things_to_be_done_before_the_next_release" id="things_to_be_done_before_the_next_release">Things to be done before the next release</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <strong>Gschem</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Fix postscript output.</div>
  </li>
  </ul>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [257-356] -->
  <h2><a name="longer_term_upgrades_desired_for_specific_tools" id="longer_term_upgrades_desired_for_specific_tools">Longer term upgrades desired for specific tools</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> <strong>Libgeda</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Enable handling of .sch files with symbols having some (but not all) pins promoted onto the .sch file. This will enable pin-swapping via backannotation from PCB.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>Gschem</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Enable hierarchical bus support.</div>
  </li>
  <li class="level2"><div class="li"> Make gschemrc variables settable from within gschem using a â??settingsâ?? pull-down menu item (new).</div>
  </li>
  <li class="level2"><div class="li"> Make gschem start up with a reasonable zoom, not zoomed waaaaay out.</div>
  </li>
  <li class="level2"><div class="li"> Improve symbol library to handle very large symbol collections better</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>Gnetlist</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Enable <strong><code>â??help</code></strong> flag. Do other gEDA/gaf programs recognize this flag?</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>Gattrib</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Make it export CSV to support BOM generation.</div>
  </li>
  <li class="level2"><div class="li"> Get printing working.</div>
  </li>
  <li class="level2"><div class="li"> Enable attachment of attributes to nets.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>Garchive</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Incorporate guile so that it reads RC files using the same mechanism as the rest of gEDA/gaf.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>CD Installer</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Change it so that the user is presented a pick-list at the beginning of the install, instead of blindly installing everything.</div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> <strong>Refdes_renum</strong>:</div>
  <ul>
  <li class="level2"><div class="li"> Doesnâ??t currently work properly with slotted parts (it gives new refdes numbers to slotted parts). Fix it so it recognizes slotted parts and assigns refdes appropriately.</div>
  </li>
  <li class="level2"><div class="li"> Provide <strong><code>â??gentle</code></strong> option, which doesnâ??t clobber (overwrite) any refdeses which are already assigned.</div>
  </li>
  </ul>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [357-1752] -->
  <h2><a name="ideas_for_new_tools_or_geda_suite-wide_enhancements" id="ideas_for_new_tools_or_geda_suite-wide_enhancements">Ideas for new tools or gEDA Suite-wide enhancements</a></h2>
  <div class="level2">
  <ul>
  <li class="level1"><div class="li"> Develop scheme for backward annotation of changes from PCB to gschem. Requires modifications to libgeda to support, e.g. pin promotion from .sym file to .sch file (enabling pin swapping).</div>
  </li>
  <li class="level1"><div class="li"> Create a Gerber â?? .pcb conversion tool. Result is metal layer or footprint editable by PCB. This might be a <acronym title="Practical Extraction and Report Language">Perl</acronym> script.</div>
  </li>
  <li class="level1"><div class="li"> Implement lockfiles between gattrib and gschem.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1753-] --></div>
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  1.1                  eda/geda/gaf/docs/wiki/geda_tragesym_readme.html
  
  Index: geda_tragesym_readme.html
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  <h1><a name="tragesym_symbol_generator_readme" id="tragesym_symbol_generator_readme">tragesym (symbol generator) README</a></h1>
  <div class="level1">
  <pre class="code">tragesym is a small python script that creates geda symbols out of 
  structured textfiles.
  
  For creating a symbol you have to edit the sourcefile first.  You can
  use the template.src file, which is in /examples/tragesym/ directory.
  Some examples are in the examples/tragesym directory too.
  
  For possible footprint names take a look into the ~geda directory 
  of the PCB program.
  
  usage is:
    tragesym &lt;sourcefile&gt; &lt;symbolfile&gt;
  
  After you have translated the sourcefile to the symbolfile you have to
  rearrange some pins with gschem, translate the symbol to the origin
  and save it in an appropriate symbol directory.  Make the attributes
  visible while doing that (edit-&gt;show hidden text) and hide the text
  again before saving.
  
  tragesym requires python (versions greater 1.5 should work).
  
  Comment an questions are welcome. 
  Send it to Werner Hoch (werner.ho@xxxxxx)
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_usage.html
  
  Index: geda_usage.html
  ===================================================================
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#what_s_the_best_way_to_learn_to_use_geda" class="toc">What's the best way to learn to use gEDA?</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#what_does_the_design_flow_in_geda_look_like" class="toc">What does the design flow in gEDA look like?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_limitations_exist_for_the_geda_tools" class="toc">What limitations exist for the gEDA tools?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_local_configuration_files_are_used_for_a_project" class="toc">What local configuration files are used for a project?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_are_the_names_and_locations_of_the_rc_files_used_with_geda_gaf_applications" class="toc">What are the names and locations of the RC files used with gEDA/gaf applications?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#what_about_a_project_manager" class="toc">What about a project manager?</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="what_s_the_best_way_to_learn_to_use_geda" id="what_s_the_best_way_to_learn_to_use_geda">What's the best way to learn to use gEDA?</a></h1>
  <div class="level1">
  
  <p>
  The first thing to do is to read and understand Bill Wilsonâ??s excellent <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">gschem -&gt; gsch2pcb -&gt; PCB</a> tutorial. This should get you started.
  </p>
  
  <p>
  Also be sure to check out the other <a href="http://geda.seul.org/docs"; class="urlextern" title="http://geda.seul.org/docs";  rel="nofollow">gEDA documentation</a> available on this website.
  </p>
  
  <p>
  However, perhaps the best way to learn the gEDA Suite is to download it and try it out yourself! If you consult Bill Wilsonâ??s <a href="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html"; class="urlextern" title="http://geda.seul.org/docs/current/tutorials/gsch2pcb/tutorial.html";  rel="nofollow">tutorial</a> while trying the suite for yourself, you will become an expert in no time!
  </p>
  
  </div>
  <!-- SECTION [1-664] -->
  <h2><a name="what_does_the_design_flow_in_geda_look_like" id="what_does_the_design_flow_in_geda_look_like">What does the design flow in gEDA look like?</a></h2>
  <div class="level2">
  
  <p>
  Here is a quick graphic for simple PCB design flow using the gEDA Suite:
  </p>
  
  <p>
  <a href="_detail/geda_design_flow.html" class="media" title="geda:design_flow.jpg"><img src="_media/geda_design_flow.jpg" class="media" title="design_flow.jpg" alt="design_flow.jpg" /></a>
  </p>
  
  <p>
  In words, the design flow for a simple PCB proceeds as follows:
  </p>
  <ol>
  <li class="level1"><div class="li"> Create your schematic using â??gschemâ??.</div>
  </li>
  <li class="level1"><div class="li"> Check your schematics with the DRC checker. Learn about it <a href="geda_faq-attribs.html" class="wikilink1" title="geda:faq-attribs">here</a>.</div>
  </li>
  <li class="level1"><div class="li"> Assign reference designators to your components using â??grenumâ?? or â??refdes_renumâ?? (or just attach them manually from within â??gschemâ??).</div>
  </li>
  <li class="level1"><div class="li"> Assign other component attributes (such as component footprints) using â??gattribâ?? (or just attach them manually using â??gschemâ??).</div>
  </li>
  <li class="level1"><div class="li"> Create a preliminary layout file and netlist using â??gsch2pcbâ??.</div>
  </li>
  <li class="level1"><div class="li"> Lay out and route your board using â??pcbâ??.</div>
  </li>
  <li class="level1"><div class="li"> Output Gerbers from within â??pcbâ?? using â??File â?? print layoutâ??, and select â??Gerber/RS274Xâ?? as the output file type.</div>
  </li>
  </ol>
  
  <p>
   If you make changes, or add to your schematic or attributes while in layout, update your board file like this:
  </p>
  <ol>
  <li class="level1"><div class="li"> Edit your schematic and/or attributes (â??gschemâ?? or â??gattribâ??).</div>
  </li>
  <li class="level1"><div class="li"> Check your schematics with the DRC checker. Learn about it <a href="geda_faq-attribs.html" class="wikilink1" title="geda:faq-attribs">here</a>.</div>
  </li>
  <li class="level1"><div class="li"> Forward annotate your changes using â??gsch2pcbâ??.</div>
  </li>
  <li class="level1"><div class="li"> From within â??pcbâ??, update your components using â??File â?? load layout data to paste bufferâ??, and then click on the drawing area to place the components.</div>
  </li>
  <li class="level1"><div class="li"> From within â??pcbâ??, update your netlist using â??File â?? load netlist fileâ??.</div>
  </li>
  </ol>
  
  <p>
   Usually, users invoke the individual tools from the command line. A project manager (â??gedaâ??) exists, but needs improvement.
  </p>
  
  </div>
  <!-- SECTION [665-2338] -->
  <h2><a name="what_limitations_exist_for_the_geda_tools" id="what_limitations_exist_for_the_geda_tools">What limitations exist for the gEDA tools?</a></h2>
  <div class="level2">
  
  <p>
  The most important thing to keep in mind about gEDAâ??s limitations is this: GEDA is an open-source software project. It has some limitations, but unlike many instances of commerical software, its limitations are not artificial, arbitrary, or driven by marketeering. That is, gEDA is neither nagware, crippleware, demoware, nor â??limited student editionâ??-ware. Any limitations to the gEDA tools exist because the programmers havenâ??t yet implemented that particular feature. Since the code is open for all to see and modify, anybody is welcome to implement a new feature or remove a limitation, and then submit their patches to the project. If you are a hacker and are interested in making a contribution to the gEDA project, consider tackling one of the limitations listed below! You will make a lot of friends, and earn international exposure!
  </p>
  <ul>
  <li class="level1"><div class="li"> Hierarchical bus support: Support for hierarchical busses doesnâ??t exist yet.</div>
  </li>
  <li class="level1"><div class="li"> Net and pin attributes in gattrib: Attaching routing attributes for nets and pins in gattrib remains TBD. (Net attributes are useful for high-speed design. For example, itâ??s often important that all tracks in a bus have the same electrical length. Unfortunately, itâ??s not clear that PCB will support these routing attributes right now.)</div>
  </li>
  <li class="level1"><div class="li"> Backannotation from PCB to gschem. Support for pinswapping and modification of the design file in pcb with subsequent backanno to gschem is TBD.</div>
  </li>
  <li class="level1"><div class="li"> The project manager â??gedaâ?? is out of date, and needs an update.</div>
  </li>
  <li class="level1"><div class="li"> Layer count in PCB: Currently, the layer count in PCB is limited to about 8 layers (which is more than adequate for small- and mid-sized projects). The PCB developers are working on increasing the layer count to an aribtrary number, but they are not yet done with this work. Contact them directly if you are interested in this project.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [2339-4233] -->
  <h2><a name="what_local_configuration_files_are_used_for_a_project" id="what_local_configuration_files_are_used_for_a_project">What local configuration files are used for a project?</a></h2>
  <div class="level2">
  
  <p>
  A typical PCB design requires the following config files in your local directory:
  </p>
  <ul>
  <li class="level1"><div class="li"> gafrc: This holds configuration info for the gEDA/gaf programs (i.e. gschem, gattrib, gnetlist, etc.). It should hold pointers to your local symbol directory (if any).</div>
  </li>
  <li class="level1"><div class="li"> attribs: If you use â??gnetlist -g bom2â?? to create a project BOM, then you need this file in order to specify which attributes are written into the BOM.</div>
  </li>
  <li class="level1"><div class="li"> projectrc: When going to layout, â??gsch2pcb projectrcâ?? is a convenient way to specify paths to local footprint directories, as well as hold other configuration information for â??gsch2pcbâ??. Note that this file may have any name you choose; I like to use projectrc ince its name is suggestive of its function.</div>
  </li>
  </ul>
  
  <p>
   Further detailed information about each configuration file is provided in the <a href="http://geda.seul.org/docs/index.html"; class="urlextern" title="http://geda.seul.org/docs/index.html";  rel="nofollow">documentation</a> for each facility.
  </p>
  
  </div>
  <!-- SECTION [4234-5185] -->
  <h2><a name="what_are_the_names_and_locations_of_the_rc_files_used_with_geda_gaf_applications" id="what_are_the_names_and_locations_of_the_rc_files_used_with_geda_gaf_applications">What are the names and locations of the RC files used with gEDA/gaf applications?</a></h2>
  <div class="level2">
  
  <p>
  The various gEDA/gaf applications (gschem, gattrib, gnetlist, etc.) use a set of RC files to set various configurable options in the tools themselves. These RC files are read in by each application upon start-up. Philosophically, there are three places where a gEDA/gaf application looks for RC files:
  </p>
  <ul>
  <li class="level1"><div class="li"> In the system installation directory: <strong><code>${prefix}/share/gEDA/</code></strong>. This location holds RC files which are global to the entire system, and are common to all users. These RC files must be found and successfully loaded for the gEDA application to work properly. <strong><code>${prefix}</code></strong> is set to the path where you installed gEDA/gaf.</div>
  </li>
  <li class="level1"><div class="li"> In the userâ??s home directory: <strong><code>$HOME/.gEDA/</code></strong>. This location holds RC files which apply to all of this userâ??s projects. <strong><code>.gEDA</code></strong> is a directory. These files are optional. Do not just place a copy of the system-gschemrc (or whatever) into this directory; this will not work properly. The right thing to do is to override specific things you want to change.</div>
  </li>
  <li class="level1"><div class="li"> In the local project directory. This location holds RC files which apply to the local project (which also lives in this directory). These RC files provide specific overrides, such as component or source libraries. This file is also optional. Do not just place a copy of the system-gschemrc (or whatever) into this directory; this will not work properly.</div>
  </li>
  </ul>
  
  <p>
   The RC file system has evolved over time. Originally, each gEDA/gaf application used its own RC file (for example, gschem used gschemrc, gnetlist used gnetlistrc, and so on). However, as the number of gEDA/gaf applications grew, it became clear that the individual RC files held a lot of redundant information, and that new users were confused by all the different RC files. Therefore, the different RC files were consolidated into a single file, called â??gafrcâ??. However, because gschem needs all kind of special customizations, we decided to keep the system gschemrc in addition to all the gafrc files. Also, in order to preserve backwards compatibility, the old RC file system is still maintained in the system directory. Accordingly, the current RC file configuration looks like this:
  </p>
  <ul>
  <li class="level1"><div class="li"> In the system installation directory:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>system-gafrc</code></strong> â?? This contains most of the global gaf settings.</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>system-gattribrc</code></strong></div>
  </li>
  <li class="level2"><div class="li"> <strong><code>system-gnetlistrc</code></strong></div>
  </li>
  <li class="level2"><div class="li"> <strong><code>system-gschemrc</code></strong> â?? This contains lots of settings specific to gschem</div>
  </li>
  <li class="level2"><div class="li"> <strong><code>system-gschlasrc</code></strong></div>
  </li>
  <li class="level2"><div class="li"> <strong><code>system-gsymcheckrc</code></strong></div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> In the userâ??s <strong><code>${HOME}</code></strong> directory:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>.gEDA/gafrc</code></strong></div>
  </li>
  </ul>
  </li>
  <li class="level1"><div class="li"> In the local project directory:</div>
  <ul>
  <li class="level2"><div class="li"> <strong><code>gafrc</code></strong> â?? This should contain your local overrides, such as pointers to locally defined symbols.</div>
  </li>
  </ul>
  </li>
  </ul>
  
  <p>
   Also loaded by the system-gschemrc is the gschem-darkbg or gschem-lightbg color definitions.
  </p>
  
  <p>
  Finally, note that gEDA/gaf applications will look for up to six configuration files upon startup:
  </p>
  <ol>
  <li class="level1"><div class="li"> <strong><code>system-gafrc</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>system-gschemrc</code></strong> (or whatever)</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>${HOME}/.geda/gafrc</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>${HOME}/.geda/gschemrc</code></strong> (or whaver)</div>
  </li>
  <li class="level1"><div class="li"> <strong><code>./gafrc</code></strong></div>
  </li>
  <li class="level1"><div class="li"> <strong><code>./gschemrc</code></strong> (or whatever)</div>
  </li>
  </ol>
  
  <p>
   If you get a warning that your app canâ??t find one or another of these files, donâ??t worry. Most of them are optional. The only required files are the system RC files.
  </p>
  
  </div>
  <!-- SECTION [5186-8559] -->
  <h2><a name="what_about_a_project_manager" id="what_about_a_project_manager">What about a project manager?</a></h2>
  <div class="level2">
  
  <p>
  The individual components in the gEDA design suite do not have the concept of an end-to-end project. Rather, they deal with their own files (e.g. â??gschemâ?? â?? .sch, â??pcbâ?? â?? .pcb). However, there is a project manager, called â??gedaâ??, which you can invoke from the command line. Itâ??s goal is to help manage your design as a whole as you take it from concept, through schematic capture, attribute attachment, layout, BOM generation, and so on.
  </p>
  
  <p>
  Unfortunately, development of â??gedaâ?? has not kept up with the rest of gEDA/gaf. In particular, â??gedaâ?? does not use the latest tools or methods to accomplish the individual design tasks. Therefore, we recommend that user simply invoke the individual tools (e.g. gschem, gattrib, gnetlist, gsch2pcb, etc) from the command line. Meanwhile, if your are a hacker are looking for a smallish project to adopt, polishing up â??gedaâ?? would make a nice introduction to the gEDA Suite, and you would make a lot of friends by doing so! 
  </p>
  
  </div>
  <!-- SECTION [8560-] --></div>
  </body>
  </html>
  
  
  
  1.1                  eda/geda/gaf/docs/wiki/geda_vams_netlister_readme.html
  
  Index: geda_vams_netlister_readme.html
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  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#vams_netlister_readme" class="toc">VAMS netlister README</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#vams_netlister" class="toc">VAMS netlister</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#vams_netlister_syntax_architecture" class="toc">VAMS netlister syntax architecture</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#vams_netlister_syntax_entity" class="toc">VAMS netlister syntax entity</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="vams_netlister_readme" id="vams_netlister_readme">VAMS netlister README</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-36] -->
  <h2><a name="vams_netlister" id="vams_netlister">VAMS netlister</a></h2>
  <div class="level2">
  <pre class="code">date: 10 october 2000
  gEDA: gnetlist vams mode
  first unrevised vams mode documentation
  
  
  Written by: Martin Lehmann
  -------------------------------------------------------------------------
  
  
  VHDL-AMS support for the gEDA gnetlist tool
  -------------------------------------------
  
  CONTENT:
  
     1. functionality
        1. ARCHITECTURE generation   
        2. ENTITY generation
        3. automatisate gnetlist calls
  
     2. implementation
        1. the vams mode of gEDA gnetlist
  	 1. scheme
  	    1. settings and new definition
  	    2. gnet-vams.scm
  	       1. routines main structure
  	    3. helpfully setting in gEDA gschem environment
  
  	 2. new c-code
  	    1. routines
  	    2. code-adaptation
        
        2. automatic generating gnetlist calls in gEDA gschem
  	 1. generated gEDA gnetlist calls
  	 2. scheme
  	    1. generate_netlist.scm
  	    2. settings
  	 
  	 3. new c-code
  	    1. routines
  	    2. code-adaptation
     
  
     The purpose of our endevour, is that gEDA gnelist completly
     supportted VHDL-AMS (VHDL Analog and Mixed-Signal) netlist
     generation. 
  
     The VHDL-AMS netlist support mode is called vams.
  
  
     1. FUNCTIONALITY
  
     gEDA gnetlist in vams mode allow it to generate a VHDL-AMS
     ARCHITECTURE or an ENTIY declaration. Which of both tasks is
     performed, dependends on the generate-mode variable. This variable
     is defined in the gnetlist command or will be set default.
  
     If generate-mode=1 (default) gnetlist creates a netlist as an
     VHDL-AMS ARCHITECTURE of the current schematic. Otherwise
     (generate-mode=2), it creates an VHDL-AMS ENTITY declaration of the
     selected component (this task needs information from gEDA gschem,
     see below).
  
     Now follows a stepwise discription of the program run in both
     submodes.
  
     We presuppose that you are familiar with the structure of gEDA
     gnetlist usage (otherwise try gnetlist -help) and that you have
     ever seen an VHDL-AMS ARCHITECTURE with its belonging ENTITY. If
     you does not then the following distription will be seems very
     strange to you. Maybe the syntax files (syntax_entity.txt,
     syntax_architeture.txt) can helps you further.
     
     ==================================================================
       
     1.1. ARCHITECTURE GENERATION
  
     
     We suppose generate-mode is equal to 1, from this it follows that
     vams creates a netlist as an ARCHITECTURE (saved to
     &lt;value-of-toplevel-attribute-entity&gt;_arc.&lt;output-fileextension&gt;).
  
  
       ARCHITECTURE &lt;architecture-identifier&gt; OF &lt;entity-identifier&gt; IS 
  
     The architecture-identifier we are getting from the toplevel
     attribute architecture, which we have introduced. If it is not
     defined, we are setting architecture-identifier default
     (default_architecture).  The same have we doing with the
     entity-identifier (toplevel attribute entity, default_entity).
  
  
       {&lt;subnet-object&gt; &lt;subnet-name&gt; : subnet-kind;}
    
     In the signal declaration part all subnets of the schematic will be
     declarated. A subnet declaration consists of an net-object, a
     net-name and a net-kind. All subnets are connected to various
     components pins. If this pins have all the same port-object and the
     same port-kind it is ok, but if one of them different, the net is
     faulty, and will be not declarated. Moreover, if the subnet-object
     a quantity, then it will be checked, whether the subnet consists
     exactly one output pin (port-mode), else the subnet is faulty too.
     The three net attributes (object, kind, mode) we are getting from
     the pin attribs, port_kind, port_object and port_mode (which we
     have introduced newly) of a component pin.
  
       
       BEGIN
  	
     Ok. it's only marks the start of the architecture body.
  
  
       {&lt;label&gt; : ENTITY &lt;entity&gt; [(&lt;architecture&gt;)]
  	    [GENERIC MAP (&lt;set generic&gt; =&gt; &lt;generic-value&gt;
  			 {; &lt;set-generic=&gt; &lt;generic-value&gt;})]
              PORT MAP ( &lt;pin-name&gt; =&gt; &lt;subnet-name&gt;{; &lt;.. =&gt; ..&gt;});}
   
     We only support component instantiation statements, like this
     above, because we generate simple VHDL-AMS netlists. The label of
     an instance is defined from the uref of the instanciated
     component. Watch out, this label must be unique,it is not checked
     anywhere. The entity variable is not the same as the
     entity-identifier, it is the value of the device attribute which on
     its part identifies the precompiled ENTITY of this special
     component. Similar is the architecture variable belonging to the
     instanciated components ARCHITECTURE (note: one ENTITY can have more
     ARCHITECTURES), hence we are getting it from the component
     attribute ARCHITECTURE (newly introduced).
  
     All generics of the generic-list are component parameters, which
     are different from its default values (set in its ENTITY
     declaration). How can we distinguish them?  All defined generics
     are attached to the component and looks like :
  
  	   &lt;attribute-name&gt;=?&lt;default-value&gt; &lt;- default, not in
  					        generic-list 
       
     And if you want to change a parameter, you only must delete the
     ?-character and replace the default-value with your wanted value,
     like this :
  
             &lt;attribute-name&gt;=&lt;new-value&gt; &lt;- element of generic list 
  	   
     If you do it this way, the new assigned value and its attribute-name
     will be appear in the GENERIC MAP (set-generic=attribute-name and
     generic-value=new-value).
  
     The PORT MAP consists of all pins of a component and which nets
     them connected to. The pin-name is getting from the pin# attribute
     of the pin and the subnet-name means the value of the label
     attribute of a net (mostly default named), which the pin is
     connected to. If the pin directly wired to a PORT component (=
     component, which device attribute =PORT), then we assign the uref
     of this component to subnet-name.
  
  
       END ARCHITECTURE &lt;architecture-identifier&gt;;
  
     I think, this line needs no more explanation. The
     architecture-identifier is the same like in the first line of
     ARCHITECTURE declaration. Hence, the ARCHITECTURE part ends here.
  
     ==================================================================
       
     1.2. ENTITY GENERATION
  
  
     Now, we suppose generate-mode is equal to 2, from this it follows
     that vams creates an ENTITY declaration of a component (save to
     &lt;component-device&gt;.vhdl). If there no component selected (empty
     top-attribs list) then it will be created an toplevel ENTITY of the
     current schematic (save to
     &lt;value-of-toplevel-attribute-entity&gt;.vhdl).
  
  
       LIBRARY &lt;library-identifier&gt;{,&lt;library-identifier&gt;};
       USE     &lt;package-identidier&gt;{,&lt;package-identifier&gt;};
   
     Well, the context clause part is not very ingenious. All libraries
     and packages you needs for your simulation you must insert staticly
     (a library contents precompiled ENTITIES, ARCHITECTURES and
     PACKAGES, which are needed from base components [base of the
     hierachical netlist] of your schematic. a package contents
     predefined types, constants, ...).  We are searching for a better
     usability of this part.
  
       
       ENTITY &lt;entity-identifier&gt; IS 
  	 [genric_clause]
  	 [port_clause]
       END ENTITY;
  
     If you want generate a toplevel ENTITY of your current schematic
     then the entity-identifier is defined from the toplevel attribute
     entity of the schematic-file. Moreover, there are no generic_clause
     and no port_clause.
  
     In case of an component based ENTITY declaration, the
     entity-identifier is getting from the device attribute of the
     selected component (this attribute is included in top-attribs list,
     which is defined in the automatic generated gnetlist command .. more
     about this, later).
  
  
       generic_clause :=
  	       GENERIC ( &lt;generic-identifier&gt; : REAL := &lt;default-value&gt;
  	                {;&lt;generic-identifier&gt; : REAL := &lt;default-value&gt;});
  
     All needed generic-identifiers and it default-values are getting
     from the top-attribs list. Note: all attached attributes of a
     component appears in the generic_clause, only special attributes,
     like uref, source and architecture, are taked out. The values of
     this attributes are taked from the top-attribs list, too, but it
     does not matter whether the value starts with a ?-character or not
     (?-character always will be deleted, if it exist in front of a
     value).
  
  
       port_clause :=
              PORT (&lt;port-kind&gt; &lt;port-identifier&gt; : [&lt;port-mode&gt;] &lt;port-type&gt;
  	          {;&lt;port-kind&gt; &lt;port-identifier&gt; : [&lt;port-mode&gt;] &lt;port-type&gt;});
  
     All variables of this clause are grabbed from the symbol of the
     selected component. Port-kind corresponds with the value of the
     port_kind attribute of the pin, which pin# attribute value is equal
     to port-identifier. Just as corresponds port-type with the the
     value of the pin attribute port_type and port-mode with the value
     of port_mode.
  	
     ===================================================================
  
     1.3. AUTOMATISATING gnetlist CALLS
  
     Because it is very arduous to type the whole gnetlist command,
     which all its parameters, per hand into the terminal, we are
     implement an automatisation of this process in gEDA gschem. This
     makes it possible to create a VHDL-AMS ARCHITECTURE or ENTITY
     whitout any commandline actions. The only thing you must do, is to
     use one of the following hotkeys:
        
  	    &lt;g e&gt; for generating an ENTITY 
  	    &lt;g n&gt; for genarating an ARCHITECTURE.
       
  	NOTE to &lt;g e&gt; - hotkey : If one component of the schematic
  				 selected then the ENTITY generation 
  				 will be applied to this component !!
  
     ===================================================================			
  
     2. IMPLEMENTATION
       
     At this section it will be explained the basic concept of the
     implementation, which is splited in two sections. The first one
     aimed to the gnelist implementation and the second to the gschem
     implementation. 
  
       
     2.1. THE VAMS MODE OF gEDA gnetlist
  
     To realize gnetlist VHDL-AMS support, it was necessary to create
     new scheme and c stuff.
  
  
     2.1.1. SCHEME 
  
     The scheme implementation contents two parts. On one hand the new
     file gnet-vams.scm, which realize the VHDL-AMS-code generation, and
     on the other hand some settings in rc-files.
  
       
     2.1.1.1. SETTINGS AND NEW DEFINITIONS
  
     The following lines insert in your gschemrc, or wherever you want,
     but it must be loaded at gnetlist startup.
  	 		
  	   - load two modules, which we needs in our new implementation.
  
  	     (define-module (ice-9 ls) :use-module (ice-9 common-list)
  		                       :use-module (ice-9 string-fun))	   
  
             - load main file for VHDL-AMS support, which contents the 
  	     startup procedure vams.
  
  	     (load &quot;&lt;path_of_gnet-vams.scm&gt;/gnet-vams.scm&quot;)
  
  
     2.1.1.2. gnet-vams.scm
  
     This file contents all necessary scheme-functions to generate
     VHDL-AMS-code. Especially, the main procedure vams, which can be
     execute from the gnetlist command.
  	 
  	 For example : 
  	     
  		gnetlist -g vams schematic_filename.sch
  
        ...
  
        
     2.1.2.1. ROUTINES MAIN STRUCTURE
  
     the mainly functions structure looks like:
  
     - (vams output-filename)
   
       ARCHITECTURE generation
  
  	- (vams:write-secondary-unit architecture entity  output-port)
  
  	    - (vams:write-architecture-declarative-part output-port)
  		  - (vams:write-signal-declarations output-port)
  
  	    - (vams:write-architecture-statement-part packages output-port)
  	          - (vams:write-generic-map output-port package)
  		  - (vams:write-port-map package output-port)
  
       ENTITY declaraction
  
  	 - (vams:write-primary-unit entity port-list generic-list output-port)     
  	    
  	     - (vams:write-context-clause output-port)
  
  	     - (vams:write-generic-clause generic-list output-port)
  		  - (vams:write-generic-list generic-list output-port)
  
  	     - (vams:write-port-clause port-list output-port)
  		  - (vams:write-port-list port-list output-port)
  
  
     2.1.1.3 HELPFULLY SETTING IN THE gEDA gschem ENVIRONMENT   
  
     This settings are not absolutly necessary, but they makes work
     easier.
  
  	- set in .gEDA/gschemrc or wherever you want, but place it
  	  right.
  
  	   	(attribute-promotion &quot;enable&quot;) 	   
  		(promote-invisible &quot;enable&quot;)
  		(enforce-hierarchy &quot;disabled&quot;)
           
  		(attribute-name &quot;port_object&quot;)
  		(attribute-name &quot;port_type&quot;)
  		(attribute-name &quot;port_mode&quot;)
  		(attribute-name &quot;entity&quot;)
  		(attribute-name &quot;architecture&quot;)
  
  
     2.1.2. NEW C - CODE 
        
     To got all informations, which we needed for currently netlist 
     generation, we must implemented two new c - functions.
  
     
     2.1.2.1 NEW ROUTINES (saved in vams_misc.c)
  
  
       SCM vams_get_package_attributes(SCM scm_uref)
  
     The first function gets all attribute names (not its values) of a
     component. This routine requires the name a component (package),
     especially the uref of it, and returns a list of all attribute
     names which are attached to this package. 
  
     We needs this functionality to produce a currectly 
     VHDL-AMS GENERIC MAP.
   
  
       char* vams_get_attribs_list 
  	   (OBJECT *object, SCM *list, OBJECT **return_found)
  
     It exists only for the support of the first function.
  	   
  
     2.1.2.2. CODE ADAPTATION
  	 
     To place this new functions at gnetlist scheme's disposal, you must
     perform the following actions.
  	 
       (1) gnetlist/src/g_register.c
  	 
  	   gh_new_procedure1_0 
  	       (&quot;gnetlist:vams-get-package-attributes&quot;, 
  	         vams_get_package_attributes);
  	 
  
       (2) gnetlist/include/prototype.h
  	     
  	   SCM vams_get_package_attributes(SCM scm_uref);
  	     
  
       (3) edit gnetlist/src/Makefile.in or directly in Makefile
  	     
  	 (if you have edited Makefile.in you must run make config of
  	 course)
  	     
  	  - add &quot;vams_misc.c&quot; to gnetlist_SOURCES - variable
  	  - add &quot;vams_misc.o&quot; to gnetlist_OBJECTS - variable
  	     
       (4) copy vams_misc.c to gEDA/gnetlist/src/
  
       (5) compile your code newly
  
     ===================================================================	
  
     2.2. AUTOMATIC GENERATING gnetlist CALLS IN gEDA gschem
  
     To realize this new feature it was necessary to put more
     information from the schematic to the scheme world of gEDA gschem.
     Concretly, we needs the filename of the current schematic, because
     gEDA gnetlist required it, and the attached attributes of a
     selected component for creating an VHDL-AMS ENTITY.  Hence, the
     gnetlist command is mutated to an unidirectional interface between
     the world of gschem scheme and the world of gnetlist scheme.
     
     There are three important things, which transfer through this
     interface:
     
  	(1) the source-file, which contents the complett filename
  	    (with path) of the current schematic.
  
  	(2) the top-attribs list, which contents all attached
              attributes of the selected component.
  
  	(3) the generate-mode, which is defined by the users actions.
  
  
     2.2.1. STRUCTURE OF gEDA gnetlist CALLS FROM COMMANDLINE OR FROM gEDA
  	  gschem.
  
       typical commandline call :
       
  		gnetlist [-o &lt;output-filename&gt;] 
  			 -g vams
  			 &lt;schematic-file&gt;
  
     There are nothing to explain. The top-attribs list and the
     generate-mode variable are default defined ('() and 1).
  
  
     calls from gEDA gschem (3 possible variations) :
  
  
     Note: vhdl-path is a predefined variable, which is set in
  	 generate_netlist.scm first times. You can it simple redefine
  	 in your local gschemrc file, which is loading everytimes you
  	 starts gEDA gschem.
  
       
       (1) hot-key-stroke: - g n  (generate netlist)
  	 
  	 --&gt; generates a netlist of the current schematic. 
  	     
  	 
  	     gnetlist -o &lt;vhdl-path&gt;/&lt;target-file&gt;
  		      -g vams
  		      &lt;source-file&gt;
  
            The source-file variable is equate to the complett
            path+filename of the current schematic, which we get with
            help of a self coded c function. If you cut out the filename
            of the source-file variable (source-file without path) then
            you are getting the target-file.generate-mode and
            top-attribs are default again.
  
        (2) hot-key-stroke: - g e (generate-entity) 
  	  and no component is selected.  
  	  
  	  --&gt; generates an toplevel ENTITY of the current
  	      schematic.
  
  
  	      gnetlist -c &lt;scheme-comm&gt;
  		       -o &lt;vhdl-path&gt;/&lt;target-file&gt;
  		       -g vams
  		       &lt;source-file&gt;
  
  		  scheme-comm=&quot;(define top-attribs '&lt;top-attribs&gt;)
  			       (define generate-mode '2)&quot;
  
  	   
  	   Source-file needs no comment, because it is the same as in
  	   (1). To get all attributes of a selected component, we are 
  	   must write a new c function again. The values, which we get 
  	   from this new function are saved in top-attribs. The sense
  	   of the scheme-comm command is to put top-attribs and 
  	   generate-mode from the gschem to the gnetlist environment.
  	   At last, the target-file consists of the pure basefilename
  	   of the source-file and an .vhdl extention.
  
         (3) hot-key-stroke: - g e (generate-entity)
  	   and only one component is selected.
  
  	   --&gt; generates an ENTITY of the selected schematic.
  
  
  	       commandline is the same as in (2).
  
  	   
  	   Differences: The target-file is different, but it does not
  	   matter, because gnetlist generate an new output-filename in
  	   in this case (&lt;device-name-of-selected-component&gt;.vhdl,
  	   normally).But one fact is very important: the top-attribs
  	   variable includes all attached attributes of the selected
  	   component now.
  
     2.2.2. SCHEME
  
     The gnetlist command is generating from two scheme functions, which
     are saved in generate_netlist.scm. This functions starts if the
     gschem user is typing one of the specified hot-keys ([g e] starts
     generate-entity and [g n] starts generate-netlis). Both routines
     puts the whole gnetlist command together and execute it. The syntax
     you see above.
  
  
     2.2.2.1. generate_netlist.scm
  
  
     2.2.2.2. SETTINGS
  
     If you want use the new feature then you must do some entries in one
     of your gEDA gschem rc-files
  
       necessary defines:
  
  	 - in system-gschemrc 
  	 	   
  		    (&quot;g&quot; . gnetlist-keymap)
  
  	   Edit your global-keymap and if &quot;g&quot; always defined then find
  	   out an other free hot-key-stroke.
   
  	   Note: the documentation supports the &quot;g&quot; - key only.
  	 
  
           - in one of the gschem startup files
  		    
   	     (define gnetlist-keymap
  	       '((&quot;n&quot; . generate-netlist)
  		 (&quot;e&quot; . generate-entity)))
  
  
       loads :
  
  	    (load &quot;/home/fliser3/.gEDA/generate_netlist.scm&quot;)
  	    
  	    
     2.2.3. NEW C-CODE
     
     The c-code makes it possible to get directly informations from the
     gschem tool, which is necessary for the online execution of
     gnetlist.
  
  
     2.2.3.1. ROUTINES
  
     It exists two new c-functions. Both are put down in
     misc_for_gnetlist.c.
  
     
       SCM get_selected_filename(gpointer data,		
  			  guint callback_action,	
  			  GtkWidget *widget)
  
     This function returns the whole filename of the current schematic,
     which is picked from the w_current-&gt;page_current-&gt;page_filename
     string.
  
  
       SCM get_selected_component_attributes(gpointer data,		
  				      guint callback_action,	
  				      GtkWidget *widget)
  
     How the name is saying, this functions returns all attributes of
     the selected component. It is realized with a simple while loop
     over all objects of the schematic, which picked out all elements
     where the selected flag is set.
  
  
     2.2.3.2. CODE-ADAPTATION
  
     Here are some actions you must conclude to makes the software
     runable.
  
     (1) new lines in /gschem/src/g_register.c
  
  	gh_new_procedure0_0 (&quot;get-selected-filename&quot;,g_get_selected_filename);
  
  
     (2) new lines in /gschem/include/prototype.h
  
  	SCM g_get_selected_filename();
  
  
     (3) copy the file misc_for_gnetlist.c to gschem/src 
  
     (4) add in file /gschem/src/Makefile.in or directly in Makefile.
  
         (if you have edited Makefile.in you must run make config of
         course)
  
  	- add &quot;misc_for_gnetlist.c&quot; to gschem_SOURCES - variable
  	- add &quot;misc_for_gnetlist.o&quot; to gschem_OBJECTS - variable
  
     (5) add new lines in /gschem/src/g_key.c
  	
  	 SCM g_get_selected_filename(void)			
  	 {							
  	   return (get_selected_filename(window_current, 0, NULL));
  	 }
  
  
     (6) compile your changed c-code newly
  </pre>
  
  </div>
  <!-- SECTION [37-20220] -->
  <h2><a name="vams_netlister_syntax_architecture" id="vams_netlister_syntax_architecture">VAMS netlister syntax architecture</a></h2>
  <div class="level2">
  <pre class="code">ARCHITECTURE &lt;architecture-identifier&gt; OF &lt;entity-identifier&gt; IS 
   
        {&lt;subnet-object&gt; &lt;subnet-name&gt; : subnet-kind;}
  
  BEGIN
  
    {&lt;label&gt; : ENTITY &lt;entity&gt; [(&lt;architecture&gt;)]
  	    [GENERIC MAP (&lt;set-generic&gt; =&gt; &lt;generic-value&gt; 
  			 {; &lt;set-generic=&gt; &lt;generic-value&gt;})]
              PORT MAP ( &lt;pin-name&gt; =&gt; &lt;subnet-name&gt;{; &lt;.. =&gt; ..&gt;});} 
  
  END ARCHITECTURE &lt;architecture-identifier&gt;;
  </pre>
  
  </div>
  <!-- SECTION [20221-20667] -->
  <h2><a name="vams_netlister_syntax_entity" id="vams_netlister_syntax_entity">VAMS netlister syntax entity</a></h2>
  <div class="level2">
  <pre class="code">LIBRARY &lt;library-identifier&gt;{,&lt;library-identifier&gt;};
  USE     &lt;package-identidier&gt;{,&lt;package-identifier&gt;};
  
  ENTITY &lt;entity-identifier&gt; IS 
     [GENERIC ( &lt;generic-identifier&gt; : REAL := &lt;default-value&gt;
  	    {;&lt;generic-identifier&gt; : REAL := &lt;default-value&gt;}); ]
     [PORT (&lt;port-kind&gt; &lt;port-identifier&gt; : [&lt;port-mode&gt;] &lt;port-type&gt;
  	{;&lt;port-kind&gt; &lt;port-identifier&gt; : [&lt;port-mode&gt;] &lt;port-type&gt;});]
  END ENTITY;
  </pre>
  
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  <h1><a name="verilog_netlister_readme" id="verilog_netlister_readme">Verilog netlister README</a></h1>
  <div class="level1">
  <pre class="code">Verilog netlister readme.
  
  THIS IS FREE SOFTWARE, see the included file COPYING for more info.
  
  Latest README:
  
  	This is the fifth release of the Verilog netlister for gEDA.
  
  	New in this release:
  
  	1) Escaped Verilog identifiers.
  
  	To facilitate board level simulations, the Verilog netlister now
  outputs `escaped' Verilog identifiers for any net, port or instance name
  that does not appear to be a valid Verilog identifier.  In this way, 
  chips with numbered pins can be netlisted and models constructed to run
  digital simulations of complete circuits.
  
  
  		Mike Jarabek
  
  
  ----- OLDER README.verilog's -----
  
  	This is the fourth release of the Verilog netlister for gEDA.
  
  	New in this release:
  
  	1) Multiple width wires.
  
  How to use: (mostly taken from a previous readme... )
  
         Here's how to proceed to make a schematic that can be netlisted
  to verilog.
  
  	   1) Create your modules by the standard method, keep in mind
                that you must supply a `pin#' attribute for each port
                you want to create in the generated verilog.  gmk_sym is
                useful for this.
  
  	   2) Place each of your newly created modules on the
                schematic.  You may also place primitives from the
                `verilog' symbol library.  Be sure to give a _unique_
                `uref' to every symbol you place on the schematic,
                unless two symbols are actually different parts of the
                same module, and the pins listed on each symbol do not
                have any names in common.  Otherwise they will not get
                netlisted.
  
  	   3) Connect nets between the modules you want.  Remember, if
                you want legible Verilog later, don't forget to name all
                your nets by attaching `label' attributes to them.  For
                Multiple bit wires just use standard Verilog notation.
                The netlister will figure out which bit ordering you
                want.  Be sure to have at least one net labeled with the
                complete range expression, otherwise the netlister will
                guess at whether you wanted net[15:0] or net[0:15] in
                your declarations.  Any inconsistent ranges will be
                reported as a warning.  Strings that appear to be
                invalid Verilog identifiers will be printed with a
                warning, but otherwise ignored. (If you get a warning
                for a valid Verilog identifier, please post a bug
                report!)
  
  	   4) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
                want to be visible in the module declaration statement.
                It is especially important to make sure that the nets
                you hook up to the pads are named, as the net names
                could change from run to run, that's a bad thing. (I/O
                pads would be a good place to put the aformentionned
                full range expressions.  Range expressions on I/O pads
                are ignored when outputting the module declaration, but
                they are used in figuring out the final bit ranges.)
                Every pad must have a unique uref, otherwise the
                netlister will get confused.
  
   	   5) Add an unattached attribute `module_name=Your_Module'
  	      somewhere on the schematic, near the title block is
  	      good.  This will name the generated Verilog module
  	      `Your_Module'.
  		
  	   6) Save your design.
  
  	   7) Run the schematic through the netlister:
  
  		  gnetlist -g verilog -o output.v schematic.sch
  
             7a) Check the output for correctness, _especially_ if you got
                 any warnings. (There should be no warnings.)
  
  	   8) Feed the netlist to your favorite simulator/synthesis tool.
  
  	
  					Mike Jarabek
  
  
          This is the third release of the Verilog netlister for geda.
  
          Fixed in this release:
  
          1) Netlister no longer barfs if there are no
             Input/Output/InOut ports on the module.
  
          2) Module instantiation code much improved/cleaned up, mostly
             due to g_netlist.c patch.
  
          New in this release:
  
          1) A whole wack-load of symbols, I created a C program that
             generates n-input versions of and, nand, or, nor, xor, and
             xnor symbols
  
          2) Modules instantiated with positional port connections.
             Just add the attribute `VERILOG_PORTS=POSITIONAL' to your
  
            symbol file as an unattached attribute, or attach it to the
             symbol on the schematic.
  
          3) Added bufif?, notif?, not and buf symbols.
          
          4) Added example of positional port module instantiation to
             the example schematic
          
          5) Added 7447 example schematic
  
          Coming:
  
          1) Module instantiation parameters. (probably by an attribute)
  
  	
          Included in this tar-ball are three patch files against the
          19990705 version of gEDA.  Apply g_netlist.c.diff and
          g_register.c.diff to the files in gnetlist/src/ and
          gnetlist.scm.diff to gnetlist.scm in the gnetlist/scheme
          directory. You may have to regenerate prototype.h, or manually
          patch it. Replace the symbols in the sym/verilog directory
          with the symbols in this distribution. (I have modified all of
          the symbols to use the new unattached attribute convention for
          device et al.) (if you have applied the patch I sent to the
          mailing list that fixes netlisting a module with no ports, you
          may have trouble applying the gnetlist.scm.diff patch.) Don't
          forget to do a `make all install' after applying the patches.
  
  	Once again, to netlist the example schematics to verilog type:
          (Assuming gnetlist has been patched and is properly installed.)
  
          gnetlist -g verilog -o test.v examples/sch/test.sch
  
          or
  
          gnetlist -g verilog -o 7447.v examples/sch/7447.sch
  
  
  (This README was from 19990629)
  Verilog netlister readme.
  
  THIS IS FREE SOFTWARE, see the included file COPYING for more info.
  
  	This is the second release of the Verilog netlister for geda.
  
  	Fixed in this release:
  
  	1) The last comma in the argument list to instantiations and
             module definitions is now suppressed
  
  	2) Better handling of `special' components has been added
  
  	New in this release:
  
  	1) Continuous assignments to 1'b0 and 1'b1 can now be
             generated by connecting the `high' or `low' symbol to a
             net.
  
  				Mike Jarabek
  				mjarabek@xxxxxxxxxxxxxx
  
  
  
  --
  
  
  	This the verilog netlister for gEDA.  Included in the tarball
  are several diff files against the 19990327 gEDA distribution.  All of
  the patches apply to the gnetlist subirectory.  You should be able to
  apply them with `patch -p1'.
  
        The netlister has its limitations:  (most of these will
  eventually get fixed, I hope..)
  
  	   1) Components connected by reference, (i.e. by having named
                net stubs attached to pins, but not conected by a
                continuous line) create duplicate entries in the wire
                declaration section of the verilog code.
  
  	   2) Multiple width wires don't work.  (Busses will help
                this)
  
  	   3) There is no way to force a signal to 1,0,z,x (yet).
  
  	   4) Some scheme code needs to be improved. (Mainly the
                classification code, it inserts `()' elements into the
                output lists. (I should know how to fix this in a day or
                two.. too bad I never got a scheme course before..))
  
  	   5) I don't know if this will work on multiple page schematics.
  
  	   6) The top level module is outputted with the same name
                every time, I don't currently think there is a way to
                get at the name of the top level schematic.
  
  
        The netlister does some neat things:
        
  
  	   1) It outputs a verilog module with proper port
                declarations, outputs are declared as outputs, inputs
                are declared as inputs, and bidirectional signals are
                declared as inouts.
  
  	   2) All nets that are found on the design are declared as
                wires. (This is to allow for net attributes later to
                declare wand's and such)
  
  	   3) Any components placed on the schematic that are given
                uref attributes create a verilog instantiation for the
                name of the module as stored in the `device' attribute,
                the instatiated name is given as the `uref' attribute.
  
  	   4) All connections into and out of instantiated modules are
                made by name, and not by order, because I can't be sure
                that the order will be right coming off the schematic.
                (anyway, that's better for the long run.)
                
  	   5) A comment is inserted at the top of the module to say
                that the file was automatically generated.
  
  
  
         Here's how to proceed to make a schematic that can be netlisted
  to verilog.
  
  	   1) Create your modules by the standard method, keep in mind
                that you must supply a `pin#' attribute for each port
                you want to create in the generated verilog.  gmk_sym is
                useful for this (with the patch to allow ascii pin names).
  
  	   2) Place each of your newly created modules on the
                schematic
  
  	   3) Connect nets between the modules you want.  Remember, if
                you want legible verilog later, don't forget to name all
                your nets by attaching `label' attributes to them.
  
  	   4) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
                want to be visible in the module declaration statement.
                It is especially important to make sure that the nets
                you hook up to the pads are named, as the net names
                could change from run to run, that's a bad thing.
  
  	   5) Save your design.
  
  	   6) Run the schematic through the netlister:
  
  		  gnetlist -g verilog -o output.v schematic.sch
  
             6a) Edit the output file to have the right module name, and
                 to remove any duplicate wires.
  
  
      There is an example schematic in the schematic directory, and a
      copy of the verilog netlist generated.
  
  The mechanics:
  
      The I/O ports for the module are detected by enumerating all of
      the nets attached to any symbol bearing the device name of `IPAD',
      `OPAD', or `IOPAD'.  If you name one of your blocks with that
      name, don't be surprised if you find `extra' ports in the module
      declaration.
  
      The wires are declared by walking through the list of nets
      returned by the function that I patched into gnetlist.  This is
      the source of the duplicate wire declarations.  This should
      probably get fixed when `net_is_duplicate' gets set for
      connections made by reference.
  
      Module instantiations are created by enumerating the pins found on
      a symbol and connecting the nets found to the pins.  If your block
      has spelling errors, then the module instantiation won't work.
      You will have to manually trace back to find the error.
  
      
  				Mike Jarabek
  
  
  
  ------------ Below is the previous version README -------------------
  
  Verilog netlister readme.
  
  THIS IS FREE SOFTWARE, see the included file COPYING for more info.
  
  
  	This the verilog netlister for gEDA.  Included in the tarball
  are several diff files against the 19990327 gEDA distribution.  All of
  the patches apply to the gnetlist subirectory.  You should be able to
  apply them with `patch -p1'.
  
  [ editor's note, if you are reading this file in a gEDA dist, then all
    the required patching and integration is already done ]
  
        The netlister has its limitations:  (most of these will
  eventually get fixed, I hope..)
  
  	   1) Components connected by reference, (i.e. by having named
                net stubs attached to pins, but not conected by a
                continuous line) create duplicate entries in the wire
                declaration section of the verilog code.
  
  	   2) Multiple width wires don't work.  (Busses will help
                this)
  
  	   3) There is no way to force a signal to 1,0,z,x (yet).
  
  	   4) Some scheme code needs to be improved. (Mainly the
                classification code, it inserts `()' elements into the
                output lists. (I should know how to fix this in a day or
                two.. too bad I never got a scheme course before..))
  
  	   5) I don't know if this will work on multiple page schematics.
  
  	   6) The top level module is outputted with the same name
                every time, I don't currently think there is a way to
                get at the name of the top level schematic.
  
  
        The netlister does some neat things:
        
  
  	   1) It outputs a verilog module with proper port
                declarations, outputs are declared as outputs, inputs
                are declared as inputs, and bidirectional signals are
                declared as inouts.
  
  	   2) All nets that are found on the design are declared as
                wires. (This is to allow for net attributes later to
                declare wand's and such)
  
  	   3) Any components placed on the schematic that are given
                uref attributes create a verilog instantiation for the
                name of the module as stored in the `device' attribute,
                the instatiated name is given as the `uref' attribute.
  
  	   4) All connections into and out of instantiated modules are
                made by name, and not by order, because I can't be sure
                that the order will be right coming off the schematic.
                (anyway, that's better for the long run.)
                
  	   5) A comment is inserted at the top of the module to say
                that the file was automatically generated.
  
  
  
         Here's how to proceed to make a schematic that can be netlisted
  to verilog.
  
  	   1) Create your modules by the standard method, keep in mind
                that you must supply a `pin#' attribute for each port
                you want to create in the generated verilog.  gmk_sym is
                useful for this (with the patch to allow ascii pin names).
  
  	   2) Place each of your newly created modules on the
                schematic
  
  	   3) Connect nets between the modules you want.  Remember, if
                you want legible verilog later, don't forget to name all
                your nets by attaching `label' attributes to them.
  
  	   4) Insert IPAD's, OPAD's, and IOPAD's for all the nets you
                want to be visible in the module declaration statement.
                It is especially important to make sure that the nets
                you hook up to the pads are named, as the net names
                could change from run to run, that's a bad thing.
  
  	   5) Save your design.
  
  	   6) Run the schematic through the netlister:
  
  		  gnetlist -g verilog -o output.v schematic.sch
  
             6a) Edit the output file to have the right module name, and
                 to remove any duplicate wires.
  
  
      There is an example schematic in the schematic directory, and a
      copy of the verilog netlist generated.
  
  The mechanics:
  
      The I/O ports for the module are detected by enumerating all of
      the nets attached to any symbol bearing the device name of `IPAD',
      `OPAD', or `IOPAD'.  If you name one of your blocks with that
      name, don't be surprised if you find `extra' ports in the module
      declaration.
  
      The wires are declared by walking through the list of nets
      returned by the function that I patched into gnetlist.  This is
      the source of the duplicate wire declarations.  This should
      probably get fixed when `net_is_duplicate' gets set for
      connections made by reference.
  
      Module instantiations are created by enumerating the pins found on
      a symbol and connecting the nets found to the pins.  If your block
      has spelling errors, then the module instantiation won't work.
      You will have to manually trace back to find the error.
  
      
  				Mike Jarabek
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_vhdl_netlister_readme.html
  
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  <h1><a name="vhdl_netlister_readme" id="vhdl_netlister_readme">VHDL netlister README</a></h1>
  <div class="level1">
  <pre class="code">The VHDL backend
  
  Written by Magnus Danielson and improved by Thomas Heidel 
  
  
  A few things you have to care about:
  
  1. In order to generate valid component declarations, you
     have to add an additional attribute to each pin.
     &quot;type=IN&quot; or &quot;type=OUT&quot; or &quot;type=INOUT&quot;
  
  2. The &quot;device&quot; attribute must be unique to a symbol!
     The verilog symbols of the same type for example, have all
     the same device attribute and will therefore not work.
  
  3. Make sure your component-library picks up the vhdl symbols instead
     of the verilog symbols  Library paths that show up last are searched
     first!
  </pre>
  
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  1.1                  eda/geda/gaf/docs/wiki/geda_wcalc_mp.html
  
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  <h1><a name="wcalc_man-page" id="wcalc_man-page">Wcalc man-page</a></h1>
  <div class="level1">
  <pre class="code">WCALC(1)							      WCALC(1)
  
  
  
  NAME
         wcalc - Transmission line analysis/synthesis calculator.
  
  
  SYNOPSIS
         wcalc
  
  
  DESCRIPTION
         The wcalc program is a tool for the analysis and synthesis of transmis-
         sion line structures and related components.  Wcalc provides the	 abil-
         ity  to	analyze	 the  electrical  parameters of a particular structure
         based on the physical dimensions and material parameters.  The  synthe-
         sis portion calculates the required physical parameters to meet desired
         electrical specifications.  Wcalc includes several models and places an
         emphasis on accuracy.
  
  
  ENVIRONMENT
         WCALC_DATADIR
  	      If  set, wcalc searches in $WCALC_DATADIR for the EPS files used
  	      when printing out	 models.   The	default	 value	is  the	 $pre-
  	      fix/share/wcalc directory, where prefix is the installation pre-
  	      fix.
  
  
  SEE ALSO
         stdio-wcalc(1)
  
  
  AUTHORS
         Wcalc was written by Dan McMahill &lt;mcmahill@xxxxxxxxxxxx&gt;
  
  
  BUGS
         None known.  Please report any on the Wcalc Sourceforge Project page at
         http://www.sourceforge.net/projects/wcalc
  
  
  
  
  
  
  								      WCALC(1)</pre>
  
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  <h1><a name="wcalc_readme" id="wcalc_readme">Wcalc README</a></h1>
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  <pre class="code">$Id: geda_wcalc_readme.html,v 1.1 2006/08/22 02:56:12 ahvezda Exp $
  
  Wcalc is a tool for the analysis and synthesis of transmission line structures and 
  related components.  Wcalc provides the ability to analyze the electrical parameters
  of a particular structure based on the physical dimensions and material parameters.
  The synthesis portion calculates the required physical parameters to meet desired
  electrical specifications.  Wcalc includes several models and places an emphasis on
  accuracy.  Several frontends provide the user with several options for its use.
  
  Models include:
  
   - single layer solenoid inductor
   - single microstrip and stripline
   - coupled microstrip
   - metal-insulator-semiconductor microstrip
   - coaxial cable
  
  Frontends include:
  
   - gtk gui
   - web (cgi)
   - scilab
   - octave
   - matlab
   - stdio
  
  See the file INSTALL for building and installation instructions.
  
  Please report all bugs at the wcalc sourceforge project page
  at http://wcalc.sf.net
  
  See the file COPYING for copying conditions.</pre>
  
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  <h1><a name="stdio_wcalc_man-page" id="stdio_wcalc_man-page">stdio Wcalc man-page</a></h1>
  <div class="level1">
  <pre class="code">STDIO-WCALC(1)							STDIO-WCALC(1)
  
  
  
  NAME
         stdio-wcalc - Transmission line analysis/synthesis calculator.
  
  
  SYNOPSIS
         stdio-wcalc [ -v|--verbose ] [ file ...	]
         stdio-wcalc [ -h|--help ]
         stdio-wcalc [ -V|--version ]
  
  
  DESCRIPTION
         The  stdio-wcalc program is a simple standard input/output interface to
         libwcalc which is the numerical engine  for  the	 wcalc	program.   The
         input  is read from the standard input on a line at a time basis.  Each
         line consists of a command followed by the numerical arguments.
  
         The analysis and synthesis functions supported by stdio-wcalc  are  the
         same  as	 those	in  the scilab, octave, and matlab frontends to wcalc.
         Please refer to the man pages listed at the end of this	man  page  for
         details	on  each  of  the  supported  functions.   The	syntax used by
         stdio-wcalc is slightly different than  scilab/octave/matlab.   Instead
         of  [a,b,c] = somefn(x,y,z) as you would use in scilab, octave, or mat-
         lab, you simply enter somefn x y z as the input line to stdio-wcalc and
         the standard output will be a b c
  
         In  addition  to the analysis and synthesis functions, stdio-wcalc sup-
         ports the &quot;version&quot; command which returns the current  version  of  the
         program.
  
  
  SEE ALSO
         wcalc(1), air_coil_calc(n), air_coil_syn(n), coax_calc(n), coax_syn(n),
         coupled_microstrip_calc(n),		    coupled_microstrip_syn(n),
         ic_microstrip_calc(n),	  ic_microstrip_syn(n),	   microstrip_calc(n),
         microstrip_syn(n), stripline_calc(n), stripline_syn(n)
  
  
  AUTHORS
         Wcalc was written by Dan McMahill &lt;mcmahill@xxxxxxxxxxxx&gt;
  
  
  BUGS
         Please  report  any  on	the  Wcalc  Sourceforge	 project  website   at
         http://wcalc.sf.net
  
  
  
  
  
  
  								STDIO-WCALC(1)</pre>
  
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  <p>
   The <a href="http://geda.seul.org/"; class="urlextern" title="http://geda.seul.org";  rel="nofollow">gEDA project</a> is developing a full <acronym title="GNU General Public License">GPL</acronym>&lsquo;d suite of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout.  
  </p>
  
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  The tools involved in the Suite enable you to professional-quality design of low- to mid-level complexity.  Using the gEDA tools, you can create PCB of up to 8 layers (soon more) with an unlimited number of components and nets.  The tools are suitable for use by students, educators, hobbiests, consultants, small businesses, and even in large corporations where an engineer might need to crank out a quick PC board (e.g. for a test stand) in a hurry.
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   <a href="http://www.jcoppens.com/soft/howto/geda-spice"; class="urlextern" title="http://www.jcoppens.com/soft/howto/geda-spice";  rel="nofollow"> SimulaciÃ³n de circuitos con gEDA y SPICE</a>
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   <a href="http://pwp.etb.net.co/jegc/out/index.html"; class="urlextern" title="http://pwp.etb.net.co/jegc/out/index.html";  rel="nofollow"> Verilog con Software Libre</a>
  </p>
  
  <p>
  <a href="http://www.ciclope.info/display/howto_es.shtml"; class="urlextern" title="http://www.ciclope.info/display/howto_es.shtml";  rel="nofollow"> HowTo Proyecto gEDA y asociados</a>
  </p>
  
  <p>
  <a href="http://marcelo.memebot.com/linux/Geda01.html"; class="urlextern" title="http://marcelo.memebot.com/linux/Geda01.html";  rel="nofollow">  Como de GEDA + Spice + easy_spice Debian Sarge.</a> 
  </p>
  
  </div>
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  1.1                  eda/geda/gaf/docs/wiki/start_fr.html
  
  Index: start_fr.html
  ===================================================================
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  <div class="dokuwiki export">
  <div class="toc">
  <div class="tocheader toctoggle" id="toc__header">Table of Contents</div>
  <div id="toc__inside">
  
  <ul class="toc">
  <li class="level1"><div class="li"><span class="li"><a href="#wiki_du_projet_geda" class="toc">Wiki du Projet gEDA</a></span></div>
  <ul class="toc">
  <li class="level2"><div class="li"><span class="li"><a href="#qu_est_ce_que_geda" class="toc">Qu'est ce que gEDA?</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#documentation_du_projet_officiel" class="toc">Documentation du Projet Officiel</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#faq_et_documentations_du_projet_informel" class="toc">FAQ et Documentations du Projet Informel</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#presentations" class="toc">PrÃ©sentations</a></span></div></li>
  <li class="level2"><div class="li"><span class="li"><a href="#a_propos_du_wiki" class="toc">Ã? propos du Wiki</a></span></div></li></ul>
  </li></ul>
  </div>
  </div>
  
  <h1><a name="wiki_du_projet_geda" id="wiki_du_projet_geda">Wiki du Projet gEDA</a></h1>
  <div class="level1">
  
  </div>
  <!-- SECTION [1-35] -->
  <h2><a name="qu_est_ce_que_geda" id="qu_est_ce_que_geda">Qu'est ce que gEDA?</a></h2>
  <div class="level2">
  
  <p>
   Le <a href="http://geda.seul.org/"; class="urlextern" title="http://geda.seul.org";  rel="nofollow">projet gEDA</a> est de dÃ©velopper une suite complÃ¨te d&rsquo;outils <acronym title="GNU General Public License">GPL</acronym> de Â« Electronic Design Automation Â». Ces outils sont utilisÃ©s pour la conception de circuits Ã©lectriques, de saisie de schÃ©mas, de simulation, de prototypage et de produciton. Le projet gEDA offre actuellement une suite mature d&rsquo;applications de logiciels libres pour la conception Ã©lectronique, incluant le la saisie de schÃ©mas, la gestion d&rsquo;attributs, la gÃ©nÃ©ration de bill of materials (BOM), le netlisting dans plus de 20 formats de netlist, la simulation analogique et numÃ©rique et le placement sur circuit imprimÃ© Â« printed circuit board (PCB) Â».  
  </p>
  
  <p>
  Les outils placÃ©s dans la Suite vous permettent de concevoir des systÃ¨mes de complexitÃ© basse Ã  moyenne, de qualitÃ© professionnelle. En utilisant les outils gEDA, vous pouvez crÃ©er des PCB jusqu&rsquo;Ã  8 couches (bientÃ´t plus) avec un nombre illimitÃ© de composants et de pistes. Les outils sont adaptÃ©s Ã  une utilisation par les Ã©tudiants, les Ã©ducateurs, les passionnÃ©s, les consultants, les petites sÃ©ries et mÃªme les grandes corporations oÃ¹ un ingÃ©nieur peut avoir besoin de rÃ©aliser une carte rapidement (i.e. pour un test manuel), dans l&rsquo;urgence.
  </p>
  
  <p>
  Tous les logiciels de la suite gEDA peuvent Ãªtre trouvÃ©s sur la <a href="http://geda.seul.org/download.html"; class="urlextern" title="http://geda.seul.org/download.html";  rel="nofollow">page de tÃ©lÃ©chargement</a>.
  </p>
  
  </div>
  <!-- SECTION [36-1427] -->
  <h2><a name="documentation_du_projet_officiel" id="documentation_du_projet_officiel">Documentation du Projet Officiel</a></h2>
  <div class="level2">
  
  <p>
  Ce sont les docs officielles du projet. Elles ont Ã©tÃ© converties depuis des documents LaTeX et <acronym title="HyperText Markup Language">HTML</acronym> en des pages Wiki de telle maniÃ¨re que la communautÃ© gEDA puisse les maintenir plus facilement. 
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="001geda_documentation.html" class="wikilink1" title="geda:documentation.fr">Documentation.fr</a> : Les derniÃ¨res versions de la documentation de la Suite d&rsquo;Outils de gEDA.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1428-1781] -->
  <h2><a name="faq_et_documentations_du_projet_informel" id="faq_et_documentations_du_projet_informel">FAQ et Documentations du Projet Informel</a></h2>
  <div class="level2">
  
  <p>
  Ce sont les <acronym title="Frequently Asked Questions">FAQ</acronym>, les HOWTO et les trucs/astuces pour vous aider avec les dÃ©tails pratiques de l&rsquo;utilisation de la Suite gEDA. Si vous avez un problÃ¨me, naviguez d&rsquo;abord sur ces pages. 
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="001geda_faq.html" class="wikilink1" title="geda:faq.fr">FAQ.fr</a> : Questions les plus frÃ©quement posÃ©es sur le projet gEDA lui-mÃªme.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_installation.html" class="wikilink2" title="geda:installation.fr">Installation.fr</a> : HOWTO et <acronym title="Frequently Asked Questions">FAQ</acronym> de l&rsquo;installation de gEDA.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_glossary.html" class="wikilink2" title="geda:glossary.fr">Glossary.fr</a> : Glossaire de termes qui sont spÃ©cifiques Ã  la Suite gEDA</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_usage.html" class="wikilink2" title="geda:usage.fr">Usage.fr</a> : Questions sur la maniÃ¨re d&rsquo;effectuer de la conception Ã©lectronique en utilisant le jeu d&rsquo;outils &ndash; informations qui s&rsquo;appliquent Ã  plusieurs ou Ã  tous les outils de la Suite de gEDA.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_faq-gschem.html" class="wikilink2" title="geda:faq-gschem.fr">FAQ-gschem.fr</a> : Questions sur l&rsquo;installation, la configuration et l&rsquo;utilisation de gschem. De mÃªme, les questions sur la crÃ©ation et l&rsquo;utilisation de symboles avec gschem.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_faq-attribs.html" class="wikilink2" title="geda:faq-attribs.fr">FAQ-attribs.fr</a> : De l&rsquo;utilisation des BOM, des DRC, de la gestion des attributs et ainsi de suite.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_faq-gnetlist.html" class="wikilink2" title="geda:faq-gnetlist.fr">FAQ-gnetlist.fr</a> : Questions sur l&rsquo;installation, la configuration et l&rsquo;utilisation de gnetlist.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_faq-simulation.html" class="wikilink2" title="geda:faq-simulation.fr">FAQ-simulation.fr</a> : Questions sur la simulation de votre schÃ©ma en utilisant les outils gEDA.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_faq-gsch2pcb.html" class="wikilink2" title="geda:faq-gsch2pcb.fr">FAQ-gsch2pcb.fr</a> : Comment transformer votre schÃ©ma en un circuit avec PCB.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_pcb_tips.html" class="wikilink2" title="geda:pcb_tips.fr">PCB tips.fr</a> : Trucs et astuces pour l&rsquo;utilisation de PCB.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_pcb-quick_reference.html" class="wikilink2" title="geda:pcb-quick_reference.fr">PCB-quick reference.fr</a> : PCB Quick Reference Sheet.</div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_tasks.html" class="wikilink2" title="geda:tasks.fr">Tasks.fr</a> : Une liste des travaaux/tÃ¢ches prioritaires qui nÃ©cessitent de l&rsquo;aide. </div>
  </li>
  <li class="level1"><div class="li"> <a href="001geda_todos.html" class="wikilink2" title="geda:todos.fr">ToDos.fr</a> : Pour les dÃ©veloppeurs seulement: liste d&rsquo;amÃ©liorations de projets en cours et Ã  faire.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [1782-3458] -->
  <h2><a name="presentations" id="presentations">PrÃ©sentations</a></h2>
  <div class="level2">
  
  <p>
  Ce sont les transparents de prÃ©sentations effectuÃ©s sur gEDA. Ils fournissent un bon survol pointu du projet pour ceux qui sont intÃ©ressÃ©s. 
  </p>
  <ul>
  <li class="level1"><div class="li"> <a href="http://geda.seul.org/talks/"; class="urlextern" title="http://geda.seul.org/talks/";  rel="nofollow">prÃ©sentations</a>: Plusieurs discours et prÃ©sentations Ã  propos de gEDA.</div>
  </li>
  </ul>
  
  </div>
  <!-- SECTION [3459-3739] -->
  <h2><a name="a_propos_du_wiki" id="a_propos_du_wiki">Ã? propos du Wiki</a></h2>
  <div class="level2">
  
  <p>
  Cette section du site gEDA est dÃ©diÃ©e Ã  la documentation fournie par plusieurs auteurs, y compris des utilisateurs. En particulier, il doit devenir une source d&rsquo;information pour ceux qui dÃ©butent juste avec les outils.  
  </p>
  
  <p>
  Toutes les contributions sont les bienvenues. Mais contrairement Ã  wikipedia, il n&rsquo;y a pas de bouton pour crÃ©er un login seul. La raison est que personne de gEDA n&rsquo;a les nerfs suffisamment solides pour traiter le vandalisme anonyme. Par consÃ©quent, vous devez Ã©crire un courriel Ã  l&rsquo;admin du site (ahvezda AT geda.seul.org) pour obtenir un accÃ¨s. Il vous enverra un accÃ¨s avec plaisir. 
  </p>
  
  </div>
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