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gEDA-cvs: pcb.git: branch: master updated (e8dd18a2f7b83c6108d2c9398903d4be92e22d4c)
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via e8dd18a2f7b83c6108d2c9398903d4be92e22d4c (commit)
from 05bd7804fa66b65159959c25d126ff939146a1eb (commit)
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=========
Summary
=========
src/create.c | 33 ++++++++++++++++++++++++---------
src/create.h | 5 +++++
src/parse_l.l | 4 ++++
3 files changed, 33 insertions(+), 9 deletions(-)
=================
Commit Messages
=================
commit e8dd18a2f7b83c6108d2c9398903d4be92e22d4c
Author: DJ Delorie <dj@xxxxxxxxxxx>
Commit: DJ Delorie <dj@xxxxxxxxxxx>
Allow via copper to overlap; preserve illegal vias from file.
Reduce "overlapping via" tests to check for overlapping drills, not
overlapping copper. If a file being loaded has "illegal" vias, load
them anyway - the check only happens at create time, if the user figures
out a way around it, preserve it.
:100644 100644 538ea0d... 07de918... M src/create.c
:100644 100644 8086b1e... 521f60e... M src/create.h
:100644 100644 a2808ad... 4ed5741... M src/parse_l.l
=========
Changes
=========
commit e8dd18a2f7b83c6108d2c9398903d4be92e22d4c
Author: DJ Delorie <dj@xxxxxxxxxxx>
Commit: DJ Delorie <dj@xxxxxxxxxxx>
Allow via copper to overlap; preserve illegal vias from file.
Reduce "overlapping via" tests to check for overlapping drills, not
overlapping copper. If a file being loaded has "illegal" vias, load
them anyway - the check only happens at create time, if the user figures
out a way around it, preserve it.
diff --git a/src/create.c b/src/create.c
index 538ea0d..07de918 100644
--- a/src/create.c
+++ b/src/create.c
@@ -66,6 +66,8 @@ RCSID ("$Id$");
static int ID = 1; /* current object ID; incremented after */
/* each creation of an object */
+static bool be_lenient = false;
+
/* ----------------------------------------------------------------------
* some local prototypes
*/
@@ -74,6 +76,16 @@ static void AddTextToElement (TextTypePtr, FontTypePtr,
FlagType);
/* ---------------------------------------------------------------------------
+ * Set the lenience mode.
+ */
+
+void
+CreateBeLenient (bool v)
+{
+ be_lenient = v;
+}
+
+/* ---------------------------------------------------------------------------
* creates a new paste buffer
*/
DataTypePtr
@@ -229,17 +241,20 @@ CreateNewVia (DataTypePtr Data,
{
PinTypePtr Via;
- VIA_LOOP (Data);
- {
- if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
- SQUARE (via->Thickness / 2 + Thickness / 2))
+ if (!be_lenient)
{
- Message (_("Dropping via at (%d, %d) because it would overlap with the via "
- "at (%d, %d)\n"), X/100, Y/100, via->X/100, via->Y/100);
- return (NULL); /* don't allow via stacking */
+ VIA_LOOP (Data);
+ {
+ if (SQUARE (via->X - X) + SQUARE (via->Y - Y) <=
+ SQUARE (via->DrillingHole / 2 + DrillingHole / 2))
+ {
+ Message (_("Dropping via at (%d, %d) because it's hole would overlap with the via "
+ "at (%d, %d)\n"), X/100, Y/100, via->X/100, via->Y/100);
+ return (NULL); /* don't allow via stacking */
+ }
+ }
+ END_LOOP;
}
- }
- END_LOOP;
Via = GetViaMemory (Data);
diff --git a/src/create.h b/src/create.h
index 8086b1e..521f60e 100644
--- a/src/create.h
+++ b/src/create.h
@@ -33,6 +33,11 @@
#include "global.h"
+/* TRUE during file loads, for example to allow overlapping vias.
+ FALSE otherwise, to stop the user from doing normally dangerous
+ things. */
+void CreateBeLenient (bool);
+
DataTypePtr CreateNewBuffer (void);
void pcb_colors_from_settings (PCBTypePtr);
PCBTypePtr CreateNewPCB (bool);
diff --git a/src/parse_l.l b/src/parse_l.l
index a2808ad..4ed5741 100644
--- a/src/parse_l.l
+++ b/src/parse_l.l
@@ -275,6 +275,8 @@ static int Parse(char *Executable, char *Path, char *Filename, char *Parameter)
* on termination.
*/
+ CreateBeLenient (true);
+
#if !defined(HAS_ATEXIT) && !defined(HAS_ON_EXIT)
if (PCB)
SaveTMPData();
@@ -286,6 +288,8 @@ static int Parse(char *Executable, char *Path, char *Filename, char *Parameter)
/* clean up parse buffer */
yy_delete_buffer(YY_CURRENT_BUFFER);
+ CreateBeLenient (false);
+
if (used_popen)
return(pclose(yyin) ? 1 : returncode);
return(fclose(yyin) ? 1 : returncode);
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