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gEDA-cvs: gaf.git: branch: master updated (1.7.1-20110619-263-g8741d19)



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=========
 Summary
=========

 NEWS                               |    3 +++
 gnetlist/scheme/gnet-verilog.scm   |   35 ++++++++++++++++++++++++++++-------
 gschem/scheme/gschem/gschemdoc.scm |    2 +-
 3 files changed, 32 insertions(+), 8 deletions(-)


=================
 Commit Messages
=================

commit 8741d194a6c2fa304d15123d398a9c3758169e6e
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>

    gnetlist: Add basic concatenated net support for verilog.
    
    Frank Thomson says: "I modified gnet-verilog.scm to support the basic
    verilog format concatenated net naming like {a,b,c[3:0]}."
    
    Closes-bug: lp-821618

:100644 100644 b035147... 576ac82... M	NEWS
:100644 100644 f0f5b8c... 1288bcb... M	gnetlist/scheme/gnet-verilog.scm

commit 8134a47e969c9025b7469d40d5ae1e56a8bab9a5
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>

    gschem: Error in gschemdoc PDF internet search.
    
    gschemdoc was trying to call internet-pdf-search to Google for
    documentation, but the correct function was internet-doc-search.

:100644 100644 7e13a6c... dcc3876... M	gschem/scheme/gschem/gschemdoc.scm

=========
 Changes
=========

commit 8741d194a6c2fa304d15123d398a9c3758169e6e
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>

    gnetlist: Add basic concatenated net support for verilog.
    
    Frank Thomson says: "I modified gnet-verilog.scm to support the basic
    verilog format concatenated net naming like {a,b,c[3:0]}."
    
    Closes-bug: lp-821618

diff --git a/NEWS b/NEWS
index b035147..576ac82 100644
--- a/NEWS
+++ b/NEWS
@@ -42,6 +42,9 @@ Notable changes in gEDA/gaf 1.7.2
   netlists for use with the National Instruments ULTIboard layout
   tool.
 
+* The `verilog' backend to `gnetlist' now supports concatenated net
+  naming like "{a,b,c[3:0]}".
+
 * `gsch2pcb' no longer supports the `m4_command' parameter in project
   files.
 
diff --git a/gnetlist/scheme/gnet-verilog.scm b/gnetlist/scheme/gnet-verilog.scm
index f0f5b8c..1288bcb 100644
--- a/gnetlist/scheme/gnet-verilog.scm
+++ b/gnetlist/scheme/gnet-verilog.scm
@@ -20,6 +20,8 @@
 ;;
 ;; Verilog netlist backend written by Mike Jarabek starts here
 ;;
+;; 14 July 2011 - VERY basic concatenation support added by Frank Thomson
+;;
 ;; --------------------------------------------------------------------------
 
 ;; some useful regexes for working with net-names
@@ -28,6 +30,14 @@
 
 (define id-regexp "[a-zA-Z_][a-zA-Z0-9_$]*")
 (define numeric  "[0-9]+")
+;; match on a verilog concatened net like:  {netname[x:y],othernet}
+;; Will not expand a bus for replication so 
+(define concat-bus-reg (make-regexp
+		       (string-append "^[[:space:]]*" 
+				      "\\{"
+				      ".*"
+				      "\\}")))
+
 ;; match on a verilog identifier like:  netname[x:y]
 (define bit-range-reg (make-regexp
 		       (string-append "^(" id-regexp ")[[:space:]]*" 
@@ -213,6 +223,7 @@
   (lambda (netname)
     (let 
 	((bit-range (regexp-exec bit-range-reg netname))
+	 (concat-bus (regexp-exec concat-bus-reg netname))
 	 (single-bit (regexp-exec single-bit-reg netname))
 	 (simple-id (regexp-exec simple-id-reg netname)))
 
@@ -259,14 +270,16 @@
   (lambda (netname)
     (let 
 	((bit-range (regexp-exec bit-range-reg netname))
+	 (concat-bus (regexp-exec concat-bus-reg netname))
 	 (single-bit (regexp-exec single-bit-reg netname))
 	 (simple-id (regexp-exec simple-id-reg netname)))
 
       ;; check over each expression type, return
       ;; result
-      ;(display netname) (display ": ")
+      ;;(display netname) (display ": ")(display concat-bus)(display "\n")
       (cond
        (bit-range  `#t )
+       (concat-bus  `#t )
        (single-bit `#t )
        (simple-id  `#t )
        (else       `#f )
@@ -488,12 +501,20 @@
     (display "/* Wires from the design */" p)
     (newline p)
     (for-each (lambda (wire)          ; print a wire statement for each
-		(display "wire " p)   ; net in the design
-		(verilog:display-wire wire p)
-		(display " ;" p)
-		(newline p))
-	      verilog:get-nets ) 
-    (newline p)))
+		; if it does not appear to be a concatenated bus then print it
+		(if (not (regexp-exec concat-bus-reg (car(cdr(cdr(cdr(cdr(cadr wire))))))))
+			(begin
+			(display "wire " p)   ; net in the design
+			(verilog:display-wire wire p)
+			(display " ;" p)
+			(newline p)
+			) ;; begin
+		 ) ;; if
+		) ;; lambda
+	      verilog:get-nets ) ;; for-each
+    (newline p)
+	) ;; lambda
+) ;; define
 
 ;;
 ;;  Output any continuous assignment statements generated

commit 8134a47e969c9025b7469d40d5ae1e56a8bab9a5
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>

    gschem: Error in gschemdoc PDF internet search.
    
    gschemdoc was trying to call internet-pdf-search to Google for
    documentation, but the correct function was internet-doc-search.

diff --git a/gschem/scheme/gschem/gschemdoc.scm b/gschem/scheme/gschem/gschemdoc.scm
index 7e13a6c..dcc3876 100644
--- a/gschem/scheme/gschem/gschemdoc.scm
+++ b/gschem/scheme/gschem/gschemdoc.scm
@@ -207,7 +207,7 @@ system associated viewer application."
      (and
       value
       ;; e) If there's a value attribute, search for it with Google.
-      (internet-pdf-search value))
+      (internet-doc-search value))
 
      ;; 3) Checks based on component basename
      (and




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