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gEDA-cvs: branch: master updated (1.4.0-20080127-11-gdb168ef)
The branch, master has been updated
via db168efbbe2656ef2103852e92e02ec3ce58e300 (commit)
from 4d441af32c63bb847ba62b4fb502fd1ed2d39c7c (commit)
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=========
Summary
=========
gnetlist/scheme/gnet-verilog.scm | 201 ++++++++++++++++++++------------------
gnetlist/scheme/gnet-vhdl.scm | 7 +-
2 files changed, 109 insertions(+), 99 deletions(-)
=================
Commit Messages
=================
commit db168efbbe2656ef2103852e92e02ec3ce58e300
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Wed Feb 13 14:59:45 2008 +0000
Fix verilog and VHDL netlist backends
These were inadvertently broken when making core gnetlist changes to
accomodate slotting in spice-sdb. Since the netlist backend is loaded
before gnetlist has traversed the schematic, the backends must not
execute any code which queries gnetlist on load. All such work is
to be done only when gnetlist invokes the (<backend>) method.
:100644 100644 ad31a8b... 2675d3d... M gnetlist/scheme/gnet-verilog.scm
:100644 100644 0b4bcf1... dea8b66... M gnetlist/scheme/gnet-vhdl.scm
=========
Changes
=========
commit db168efbbe2656ef2103852e92e02ec3ce58e300
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Wed Feb 13 14:59:45 2008 +0000
Fix verilog and VHDL netlist backends
These were inadvertently broken when making core gnetlist changes to
accomodate slotting in spice-sdb. Since the netlist backend is loaded
before gnetlist has traversed the schematic, the backends must not
execute any code which queries gnetlist on load. All such work is
to be done only when gnetlist invokes the (<backend>) method.
diff --git a/gnetlist/scheme/gnet-verilog.scm b/gnetlist/scheme/gnet-verilog.scm
index ad31a8b..2675d3d 100644
--- a/gnetlist/scheme/gnet-verilog.scm
+++ b/gnetlist/scheme/gnet-verilog.scm
@@ -343,102 +343,110 @@
;; return a list of net description objects
;;
-(define the-nets '())
-
-(define verilog:get-nets
- (begin
- (for-each
- (lambda (netname)
- ; parse the netname, and see if it is already on the list
- (let* ((parsed (verilog:net-parse netname))
- (listed (assoc (car parsed) the-nets)))
- (if listed
- (begin ; it is, do some checks, and update the record
- ;; extract fields from list
- (let* ((list-name (car listed))
- (list-n1 (car (cadr listed)))
- (list-n2 (cadr (cadr listed)))
- (list-increasing (caddr (cadr listed)))
- (list-sure (cadddr (cadr listed)))
- (list-real (cadddr (cdr (cadr listed))))
-
- (name (car parsed))
- (n1 (car (cadr parsed)))
- (n2 (cadr (cadr parsed)))
- (increasing (caddr (cadr parsed)))
- (sure (cadddr (cadr parsed)))
- (real (cadddr (cdr (cadr parsed))))
-
- (consistant (or (and list-increasing increasing)
- (and (not list-increasing)
- (not increasing))))
-
- )
-
- (cond
- ((and list-sure consistant)
- (begin
- (set-cdr! listed
- (verilog:update-record n1 n2
- list-n1 list-n2
- increasing
- #t
- real)
- )))
- ((and list-sure (not sure) (zero? n1) (zero? n2))
- '() ;; this is a net without any expression, leave it
- )
- ((and list-sure (not consistant))
- (begin ;; order is inconsistent
- (display
- (string-append "Warning: Net `" real "' has a "
- "bit order that conflicts with "
- "the original definition of `"
- list-real "', ignoring `"
- real "'"
- ))
- (newline)))
- ((and (not list-sure) sure consistant)
- (begin
- (set-cdr! listed
- (verilog:update-record n1 n2
- list-n1 list-n2
- increasing
- #t
- real))))
-
- ((and (not list-sure) sure (not consistant))
- (begin
- (set-cdr! listed
- (verilog:update-record n1 n2
- list-n2 list-n1
- increasing
- #t
- real))))
- ((and (not list-sure) (not sure))
- (begin
- (set-cdr! listed
- (verilog:update-record n1 n2
- list-n1 list-n2
- increasing
- #f
- real))))
- (else
- (begin
- (display "This should never happen!")
- (newline)))
- )
- )
- )
- (begin ; it is not, just add it to the end
- (set! the-nets
- (append the-nets
- (list parsed))))
- ))
- )
-
- all-unique-nets)
- the-nets))
+
+(define verilog:get-nets '())
+
+
+(define verilog:get-nets-once!
+ (lambda nil
+ (define the-nets '())
+ (set! verilog:get-nets
+ (begin
+ (for-each
+ (lambda (netname)
+ ; parse the netname, and see if it is already on the list
+ (let* ((parsed (verilog:net-parse netname))
+ (listed (assoc (car parsed) the-nets)))
+ (if listed
+ (begin ; it is, do some checks, and update the record
+ ;; extract fields from list
+ (let* ((list-name (car listed))
+ (list-n1 (car (cadr listed)))
+ (list-n2 (cadr (cadr listed)))
+ (list-increasing (caddr (cadr listed)))
+ (list-sure (cadddr (cadr listed)))
+ (list-real (cadddr (cdr (cadr listed))))
+
+ (name (car parsed))
+ (n1 (car (cadr parsed)))
+ (n2 (cadr (cadr parsed)))
+ (increasing (caddr (cadr parsed)))
+ (sure (cadddr (cadr parsed)))
+ (real (cadddr (cdr (cadr parsed))))
+
+ (consistant (or (and list-increasing increasing)
+ (and (not list-increasing)
+ (not increasing))))
+
+ )
+
+ (cond
+ ((and list-sure consistant)
+ (begin
+ (set-cdr! listed
+ (verilog:update-record n1 n2
+ list-n1 list-n2
+ increasing
+ #t
+ real)
+ )))
+ ((and list-sure (not sure) (zero? n1) (zero? n2))
+ '() ;; this is a net without any expression, leave it
+ )
+ ((and list-sure (not consistant))
+ (begin ;; order is inconsistent
+ (display
+ (string-append "Warning: Net `" real "' has a "
+ "bit order that conflicts with "
+ "the original definition of `"
+ list-real "', ignoring `"
+ real "'"
+ ))
+ (newline)))
+ ((and (not list-sure) sure consistant)
+ (begin
+ (set-cdr! listed
+ (verilog:update-record n1 n2
+ list-n1 list-n2
+ increasing
+ #t
+ real))))
+
+ ((and (not list-sure) sure (not consistant))
+ (begin
+ (set-cdr! listed
+ (verilog:update-record n1 n2
+ list-n2 list-n1
+ increasing
+ #t
+ real))))
+ ((and (not list-sure) (not sure))
+ (begin
+ (set-cdr! listed
+ (verilog:update-record n1 n2
+ list-n1 list-n2
+ increasing
+ #f
+ real))))
+ (else
+ (begin
+ (display "This should never happen!")
+ (newline)))
+ )
+ )
+ )
+ (begin ; it is not, just add it to the end
+ (set! the-nets
+ (append the-nets
+ (list parsed))))
+ ))
+ )
+
+ all-unique-nets)
+ the-nets)
+ )
+ verilog:get-nets
+))
;; Retrieve the requested net record from the database.
@@ -624,6 +632,7 @@
(lambda (output-filename)
(let ((port (open-output-file output-filename)))
(begin
+ (verilog:get-nets-once!)
(verilog:write-top-header port)
(verilog:write-wires port)
(verilog:write-continuous-assigns port)
diff --git a/gnetlist/scheme/gnet-vhdl.scm b/gnetlist/scheme/gnet-vhdl.scm
index 0b4bcf1..dea8b66 100644
--- a/gnetlist/scheme/gnet-vhdl.scm
+++ b/gnetlist/scheme/gnet-vhdl.scm
@@ -418,8 +418,9 @@
;;;
(define unique-devices
- (vhdl:get-unique-devices (map get-device packages))
-)
+ (lambda nil
+ (vhdl:get-unique-devices (map get-device packages))
+))
;;; Signal Declaration
@@ -516,7 +517,7 @@
; Due to my taste will the component declarations go first
; XXX - Broken until someday
; THHE fixed today ;-)
- (vhdl:write-component-declarations unique-devices p)
+ (vhdl:write-component-declarations (unique-devices) p)
; Then comes the signal declatations
(vhdl:write-signal-declarations p)
)
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