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gEDA-cvs: gaf.git: branch: master updated (1.5.1-20081221-158-g2d88825)
The branch, master has been updated
via 2d888258d954c993aa03e4a1beb7b03e62df4d95 (commit)
from d57fcbf52893127f5a37656f65c6f076c6d51470 (commit)
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=========
Summary
=========
gnetlist/src/g_netlist.c | 23 +--
.../common/outputs/PCBboard/cascade-output.net | 4 +
.../tests/common/outputs/allegro/JD-output.net | 14 +-
.../common/outputs/allegro/JD_Include-output.net | 14 +-
.../outputs/allegro/JD_Include_nomunge-output.net | 14 +-
.../common/outputs/allegro/JD_Sort-output.net | 14 +-
.../outputs/allegro/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/allegro/JD_nomunge-output.net | 14 +-
.../common/outputs/allegro/TwoStageAmp-output.net | 28 ++--
.../outputs/allegro/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/allegro/TwoStageAmp_Sort-output.net | 28 ++--
.../common/outputs/allegro/cascade-output.net | 8 +-
.../common/outputs/allegro/multiequal-output.net | 2 +-
.../common/outputs/allegro/netattrib-output.net | 2 +-
.../common/outputs/allegro/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/bae/JD-output.net | 14 +-
.../tests/common/outputs/bae/JD_Include-output.net | 14 +-
.../outputs/bae/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/bae/JD_Sort-output.net | 14 +-
.../common/outputs/bae/JD_Sort_nomunge-output.net | 14 +-
.../tests/common/outputs/bae/JD_nomunge-output.net | 14 +-
.../common/outputs/bae/TwoStageAmp-output.net | 28 ++--
.../outputs/bae/TwoStageAmp_Include-output.net | 28 ++--
.../common/outputs/bae/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/bae/cascade-output.net | 8 +-
.../tests/common/outputs/bae/multiequal-output.net | 2 +-
.../tests/common/outputs/bae/netattrib-output.net | 2 +-
.../common/outputs/bae/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/bom/JD-output.net | 14 +-
.../tests/common/outputs/bom/JD_Include-output.net | 14 +-
.../outputs/bom/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/bom/JD_Sort-output.net | 14 +-
.../common/outputs/bom/JD_Sort_nomunge-output.net | 14 +-
.../tests/common/outputs/bom/JD_nomunge-output.net | 14 +-
.../common/outputs/bom/TwoStageAmp-output.net | 28 ++--
.../outputs/bom/TwoStageAmp_Include-output.net | 28 ++--
.../common/outputs/bom/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/bom/cascade-output.net | 8 +-
.../tests/common/outputs/bom/multiequal-output.net | 2 +-
.../tests/common/outputs/bom/netattrib-output.net | 2 +-
.../common/outputs/bom/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/bom2/JD-output.net | 14 +-
.../common/outputs/bom2/JD_Include-output.net | 14 +-
.../outputs/bom2/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/bom2/JD_Sort-output.net | 14 +-
.../common/outputs/bom2/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/bom2/JD_nomunge-output.net | 14 +-
.../common/outputs/bom2/TwoStageAmp-output.net | 28 ++--
.../outputs/bom2/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/bom2/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/bom2/cascade-output.net | 8 +-
.../common/outputs/bom2/multiequal-output.net | 2 +-
.../tests/common/outputs/bom2/netattrib-output.net | 2 +-
.../common/outputs/bom2/powersupply-output.net | 12 +-
.../common/outputs/drc/TwoStageAmp-output.net | 2 +-
.../outputs/drc/TwoStageAmp_Include-output.net | 2 +-
.../common/outputs/drc/TwoStageAmp_Sort-output.net | 2 +-
.../tests/common/outputs/drc/cascade-output.net | 8 +-
.../tests/common/outputs/drc/netattrib-output.net | 2 +-
.../common/outputs/drc/powersupply-output.net | 6 +-
.../tests/common/outputs/drc2/netattrib-output.net | 6 +-
gnetlist/tests/common/outputs/eagle/JD-output.net | 28 ++--
.../common/outputs/eagle/JD_Include-output.net | 28 ++--
.../outputs/eagle/JD_Include_nomunge-output.net | 28 ++--
.../tests/common/outputs/eagle/JD_Sort-output.net | 28 ++--
.../outputs/eagle/JD_Sort_nomunge-output.net | 28 ++--
.../common/outputs/eagle/JD_nomunge-output.net | 28 ++--
.../common/outputs/eagle/TwoStageAmp-output.net | 56 ++++----
.../outputs/eagle/TwoStageAmp_Include-output.net | 56 ++++----
.../outputs/eagle/TwoStageAmp_Sort-output.net | 56 ++++----
.../tests/common/outputs/eagle/cascade-output.net | 16 +-
.../common/outputs/eagle/multiequal-output.net | 4 +-
.../common/outputs/eagle/netattrib-output.net | 4 +-
.../common/outputs/eagle/powersupply-output.net | 24 ++--
.../tests/common/outputs/futurenet2/JD-output.net | 88 +++++-----
.../outputs/futurenet2/JD_Include-output.net | 88 +++++-----
.../futurenet2/JD_Include_nomunge-output.net | 88 +++++-----
.../common/outputs/futurenet2/JD_Sort-output.net | 88 +++++-----
.../outputs/futurenet2/JD_Sort_nomunge-output.net | 88 +++++-----
.../outputs/futurenet2/JD_nomunge-output.net | 88 +++++-----
.../outputs/futurenet2/TwoStageAmp-output.net | 168 ++++++++++----------
.../futurenet2/TwoStageAmp_Include-output.net | 168 ++++++++++----------
.../outputs/futurenet2/TwoStageAmp_Sort-output.net | 168 ++++++++++----------
.../common/outputs/futurenet2/cascade-output.net | 52 +++---
.../outputs/futurenet2/multiequal-output.net | 10 +-
.../common/outputs/futurenet2/netattrib-output.net | 24 ++--
.../outputs/futurenet2/powersupply-output.net | 66 ++++----
gnetlist/tests/common/outputs/geda/JD-output.net | 14 +-
.../common/outputs/geda/JD_Include-output.net | 14 +-
.../outputs/geda/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/geda/JD_Sort-output.net | 14 +-
.../common/outputs/geda/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/geda/JD_nomunge-output.net | 14 +-
.../common/outputs/geda/TwoStageAmp-output.net | 28 ++--
.../outputs/geda/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/geda/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/geda/cascade-output.net | 8 +-
.../common/outputs/geda/multiequal-output.net | 2 +-
.../tests/common/outputs/geda/netattrib-output.net | 2 +-
.../common/outputs/geda/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/gossip/JD-output.net | 14 +-
.../common/outputs/gossip/JD_Include-output.net | 14 +-
.../outputs/gossip/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/gossip/JD_Sort-output.net | 14 +-
.../outputs/gossip/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/gossip/JD_nomunge-output.net | 14 +-
.../common/outputs/gossip/TwoStageAmp-output.net | 28 ++--
.../outputs/gossip/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/gossip/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/gossip/cascade-output.net | 8 +-
.../common/outputs/gossip/multiequal-output.net | 2 +-
.../common/outputs/gossip/netattrib-output.net | 2 +-
.../common/outputs/gossip/powersupply-output.net | 12 +-
.../tests/common/outputs/gsch2pcb/JD-output.net | 14 +-
.../common/outputs/gsch2pcb/JD_Include-output.net | 14 +-
.../outputs/gsch2pcb/JD_Include_nomunge-output.net | 14 +-
.../common/outputs/gsch2pcb/JD_Sort-output.net | 14 +-
.../outputs/gsch2pcb/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/gsch2pcb/JD_nomunge-output.net | 14 +-
.../common/outputs/gsch2pcb/TwoStageAmp-output.net | 28 ++--
.../gsch2pcb/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/gsch2pcb/TwoStageAmp_Sort-output.net | 28 ++--
.../common/outputs/gsch2pcb/cascade-output.net | 8 +-
.../common/outputs/gsch2pcb/multiequal-output.net | 2 +-
.../common/outputs/gsch2pcb/netattrib-output.net | 2 +-
.../common/outputs/gsch2pcb/powersupply-output.net | 12 +-
.../tests/common/outputs/mathematica/JD-output.net | 16 +-
.../outputs/mathematica/JD_Include-output.net | 16 +-
.../mathematica/JD_Include_nomunge-output.net | 16 +-
.../common/outputs/mathematica/JD_Sort-output.net | 16 +-
.../outputs/mathematica/JD_Sort_nomunge-output.net | 16 +-
.../outputs/mathematica/JD_nomunge-output.net | 16 +-
.../outputs/mathematica/TwoStageAmp-output.net | 28 ++--
.../mathematica/TwoStageAmp_Include-output.net | 28 ++--
.../mathematica/TwoStageAmp_Sort-output.net | 28 ++--
.../common/outputs/mathematica/cascade-output.net | 10 +-
.../outputs/mathematica/multiequal-output.net | 4 +-
.../outputs/mathematica/netattrib-output.net | 4 +-
.../outputs/mathematica/powersupply-output.net | 12 +-
.../tests/common/outputs/maxascii/JD-output.net | 14 +-
.../common/outputs/maxascii/JD_Include-output.net | 14 +-
.../outputs/maxascii/JD_Include_nomunge-output.net | 14 +-
.../common/outputs/maxascii/JD_Sort-output.net | 14 +-
.../outputs/maxascii/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/maxascii/JD_nomunge-output.net | 14 +-
.../common/outputs/maxascii/TwoStageAmp-output.net | 28 ++--
.../maxascii/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/maxascii/TwoStageAmp_Sort-output.net | 28 ++--
.../common/outputs/maxascii/cascade-output.net | 8 +-
.../common/outputs/maxascii/multiequal-output.net | 2 +-
.../common/outputs/maxascii/netattrib-output.net | 2 +-
.../common/outputs/maxascii/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/osmond/JD-output.net | 14 +-
.../common/outputs/osmond/JD_Include-output.net | 14 +-
.../outputs/osmond/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/osmond/JD_Sort-output.net | 14 +-
.../outputs/osmond/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/osmond/JD_nomunge-output.net | 14 +-
.../common/outputs/osmond/TwoStageAmp-output.net | 28 ++--
.../outputs/osmond/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/osmond/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/osmond/cascade-output.net | 8 +-
.../common/outputs/osmond/multiequal-output.net | 2 +-
.../common/outputs/osmond/netattrib-output.net | 2 +-
.../common/outputs/osmond/powersupply-output.net | 12 +-
gnetlist/tests/common/outputs/pads/JD-output.net | 14 +-
.../common/outputs/pads/JD_Include-output.net | 14 +-
.../outputs/pads/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/pads/JD_Sort-output.net | 14 +-
.../common/outputs/pads/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/pads/JD_nomunge-output.net | 14 +-
.../common/outputs/pads/TwoStageAmp-output.net | 28 ++--
.../outputs/pads/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/pads/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/pads/cascade-output.net | 8 +-
.../common/outputs/pads/multiequal-output.net | 2 +-
.../tests/common/outputs/pads/netattrib-output.net | 2 +-
.../common/outputs/pads/powersupply-output.net | 12 +-
.../tests/common/outputs/pcbpins/JD-output.net | 48 +++---
.../common/outputs/pcbpins/JD_Include-output.net | 48 +++---
.../outputs/pcbpins/JD_Include_nomunge-output.net | 48 +++---
.../common/outputs/pcbpins/JD_Sort-output.net | 48 +++---
.../outputs/pcbpins/JD_Sort_nomunge-output.net | 48 +++---
.../common/outputs/pcbpins/JD_nomunge-output.net | 48 +++---
.../common/outputs/pcbpins/TwoStageAmp-output.net | 102 ++++++------
.../outputs/pcbpins/TwoStageAmp_Include-output.net | 102 ++++++------
.../outputs/pcbpins/TwoStageAmp_Sort-output.net | 102 ++++++------
.../common/outputs/pcbpins/cascade-output.net | 30 ++--
.../common/outputs/pcbpins/multiequal-output.net | 4 +-
.../common/outputs/pcbpins/netattrib-output.net | 16 +-
.../common/outputs/pcbpins/powersupply-output.net | 46 +++---
.../tests/common/outputs/protelII/JD-output.net | 64 ++++----
.../common/outputs/protelII/JD_Include-output.net | 64 ++++----
.../outputs/protelII/JD_Include_nomunge-output.net | 64 ++++----
.../common/outputs/protelII/JD_Sort-output.net | 64 ++++----
.../outputs/protelII/JD_Sort_nomunge-output.net | 64 ++++----
.../common/outputs/protelII/JD_nomunge-output.net | 64 ++++----
.../common/outputs/protelII/TwoStageAmp-output.net | 120 +++++++-------
.../protelII/TwoStageAmp_Include-output.net | 120 +++++++-------
.../outputs/protelII/TwoStageAmp_Sort-output.net | 120 +++++++-------
.../common/outputs/protelII/cascade-output.net | 46 +++---
.../common/outputs/protelII/multiequal-output.net | 12 +-
.../common/outputs/protelII/netattrib-output.net | 14 +-
.../common/outputs/protelII/powersupply-output.net | 52 +++---
.../tests/common/outputs/spice-sdb/JD-output.net | 12 +-
.../common/outputs/spice-sdb/JD_Include-output.net | 12 +-
.../spice-sdb/JD_Include_nomunge-output.net | 12 +-
.../common/outputs/spice-sdb/JD_nomunge-output.net | 12 +-
.../outputs/spice-sdb/TwoStageAmp-output.net | 28 ++--
.../spice-sdb/TwoStageAmp_Include-output.net | 28 ++--
.../common/outputs/spice-sdb/cascade-output.net | 8 +-
.../common/outputs/spice-sdb/multiequal-output.net | 2 +-
.../common/outputs/spice-sdb/netattrib-output.net | 2 +-
.../outputs/spice-sdb/powersupply-output.net | 12 +-
.../common/outputs/spice-sdb/singlenet-output.net | 2 +-
gnetlist/tests/common/outputs/spice/JD-output.net | 14 +-
.../common/outputs/spice/JD_Include-output.net | 14 +-
.../outputs/spice/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/spice/JD_Sort-output.net | 14 +-
.../outputs/spice/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/spice/JD_nomunge-output.net | 14 +-
.../common/outputs/spice/TwoStageAmp-output.net | 28 ++--
.../outputs/spice/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/spice/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/spice/cascade-output.net | 8 +-
.../common/outputs/spice/multiequal-output.net | 2 +-
.../common/outputs/spice/netattrib-output.net | 2 +-
.../common/outputs/spice/powersupply-output.net | 12 +-
.../tests/common/outputs/systemc/JD-output.net | 76 +++++-----
.../common/outputs/systemc/JD_Include-output.net | 76 +++++-----
.../outputs/systemc/JD_Include_nomunge-output.net | 76 +++++-----
.../common/outputs/systemc/JD_Sort-output.net | 76 +++++-----
.../outputs/systemc/JD_Sort_nomunge-output.net | 76 +++++-----
.../common/outputs/systemc/JD_nomunge-output.net | 76 +++++-----
.../common/outputs/systemc/TwoStageAmp-output.net | 144 +++++++++---------
.../outputs/systemc/TwoStageAmp_Include-output.net | 144 +++++++++---------
.../outputs/systemc/TwoStageAmp_Sort-output.net | 144 +++++++++---------
.../common/outputs/systemc/cascade-output.net | 46 +++---
.../common/outputs/systemc/multiequal-output.net | 8 +-
.../common/outputs/systemc/netattrib-output.net | 18 +-
.../common/outputs/systemc/powersupply-output.net | 68 ++++----
gnetlist/tests/common/outputs/tango/JD-output.net | 64 ++++----
.../common/outputs/tango/JD_Include-output.net | 64 ++++----
.../outputs/tango/JD_Include_nomunge-output.net | 64 ++++----
.../tests/common/outputs/tango/JD_Sort-output.net | 64 ++++----
.../outputs/tango/JD_Sort_nomunge-output.net | 64 ++++----
.../common/outputs/tango/JD_nomunge-output.net | 64 ++++----
.../common/outputs/tango/TwoStageAmp-output.net | 110 +++++++-------
.../outputs/tango/TwoStageAmp_Include-output.net | 110 +++++++-------
.../outputs/tango/TwoStageAmp_Sort-output.net | 110 +++++++-------
.../tests/common/outputs/tango/cascade-output.net | 32 ++--
.../common/outputs/tango/multiequal-output.net | 12 +-
.../common/outputs/tango/netattrib-output.net | 10 +-
.../common/outputs/tango/powersupply-output.net | 46 +++---
gnetlist/tests/common/outputs/vams/JD-output.net | 82 +++++-----
.../common/outputs/vams/JD_Include-output.net | 82 +++++-----
.../outputs/vams/JD_Include_nomunge-output.net | 82 +++++-----
.../tests/common/outputs/vams/JD_Sort-output.net | 82 +++++-----
.../common/outputs/vams/JD_Sort_nomunge-output.net | 82 +++++-----
.../common/outputs/vams/JD_nomunge-output.net | 82 +++++-----
.../common/outputs/vams/TwoStageAmp-output.net | 168 ++++++++++----------
.../outputs/vams/TwoStageAmp_Include-output.net | 168 ++++++++++----------
.../outputs/vams/TwoStageAmp_Sort-output.net | 168 ++++++++++----------
.../tests/common/outputs/vams/cascade-output.net | 76 +++++-----
.../common/outputs/vams/multiequal-output.net | 10 +-
.../tests/common/outputs/vams/netattrib-output.net | 20 ++--
.../common/outputs/vams/powersupply-output.net | 50 +++---
.../tests/common/outputs/verilog/JD-output.net | 60 ++++----
.../common/outputs/verilog/JD_Include-output.net | 60 ++++----
.../outputs/verilog/JD_Include_nomunge-output.net | 60 ++++----
.../common/outputs/verilog/JD_Sort-output.net | 60 ++++----
.../outputs/verilog/JD_Sort_nomunge-output.net | 60 ++++----
.../common/outputs/verilog/JD_nomunge-output.net | 60 ++++----
.../common/outputs/verilog/TwoStageAmp-output.net | 116 +++++++-------
.../outputs/verilog/TwoStageAmp_Include-output.net | 116 +++++++-------
.../outputs/verilog/TwoStageAmp_Sort-output.net | 116 +++++++-------
.../common/outputs/verilog/cascade-output.net | 34 ++--
.../common/outputs/verilog/multiequal-output.net | 4 +-
.../common/outputs/verilog/netattrib-output.net | 14 +-
.../common/outputs/verilog/powersupply-output.net | 44 +++---
gnetlist/tests/common/outputs/vhdl/JD-output.net | 76 +++++-----
.../common/outputs/vhdl/JD_Include-output.net | 76 +++++-----
.../outputs/vhdl/JD_Include_nomunge-output.net | 76 +++++-----
.../tests/common/outputs/vhdl/JD_Sort-output.net | 76 +++++-----
.../common/outputs/vhdl/JD_Sort_nomunge-output.net | 76 +++++-----
.../common/outputs/vhdl/JD_nomunge-output.net | 76 +++++-----
.../common/outputs/vhdl/TwoStageAmp-output.net | 124 +++++++-------
.../outputs/vhdl/TwoStageAmp_Include-output.net | 124 +++++++-------
.../outputs/vhdl/TwoStageAmp_Sort-output.net | 124 +++++++-------
.../tests/common/outputs/vhdl/cascade-output.net | 48 +++---
.../common/outputs/vhdl/multiequal-output.net | 10 +-
.../tests/common/outputs/vhdl/netattrib-output.net | 22 ++--
.../common/outputs/vhdl/powersupply-output.net | 56 ++++----
gnetlist/tests/common/outputs/vipec/JD-output.net | 14 +-
.../common/outputs/vipec/JD_Include-output.net | 14 +-
.../outputs/vipec/JD_Include_nomunge-output.net | 14 +-
.../tests/common/outputs/vipec/JD_Sort-output.net | 14 +-
.../outputs/vipec/JD_Sort_nomunge-output.net | 14 +-
.../common/outputs/vipec/JD_nomunge-output.net | 14 +-
.../common/outputs/vipec/TwoStageAmp-output.net | 28 ++--
.../outputs/vipec/TwoStageAmp_Include-output.net | 28 ++--
.../outputs/vipec/TwoStageAmp_Sort-output.net | 28 ++--
.../tests/common/outputs/vipec/cascade-output.net | 8 +-
.../common/outputs/vipec/multiequal-output.net | 2 +-
.../common/outputs/vipec/netattrib-output.net | 2 +-
.../common/outputs/vipec/powersupply-output.net | 12 +-
gnetlist/tests/hierarchy/hierarchy.geda | 2 +-
gnetlist/tests/multiequal.spice-sdb | 4 +-
gnetlist/tests/netattrib.geda | 2 +-
gnetlist/tests/powersupply.allegro | 12 +-
gnetlist/tests/powersupply.bae | 12 +-
gnetlist/tests/powersupply.geda | 12 +-
gnetlist/tests/powersupply.maxascii | 12 +-
gnetlist/tests/powersupply.pads | 12 +-
gnetlist/tests/powersupply.protelII | 52 +++---
gnetlist/tests/powersupply.tango | 46 +++---
gnetlist/tests/stack_1.geda | 4 +-
317 files changed, 5375 insertions(+), 5382 deletions(-)
=================
Commit Messages
=================
commit 2d888258d954c993aa03e4a1beb7b03e62df4d95
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Thu Jan 8 00:45:28 2009 +0000
gnetlist: Avoid depending on GHashTable ordering for output consistency
If the GLib hash table changes (which it has in late versions of GLib),
the netlist output ordering changes due to our mis-use of GHashTable to
list all unique component names without enforcing any eplicit order on
the enumeration of the hash table contents.
Since ordering may be important to backends, want to have known output
ordering whilst removing duplicate entrys, but without an explicit sort
of the refdes list.
This commit introduces an incremental build of the list, first checking
the hash table for a hit, and only adding the new refdes if it wasn't
already in the has table. This is gives the output a predictable order
(based on the input), rather than inserting all refdes into the hash
table, and building the list in whatever order the table implentation
traverses them in.
This change does unfortunately means a large number or ordering related
changes are also made in the gnetlist test suite's golden files.
There are also some non-ordering changes in the checked in golden files.
These is encountered in the pretty well obsolete PCBboard backend - which
errors out when it hits certain components it can't find footprints for.
Changing the ordering changes the point at which it dies, and thus the
netlist output. Lets just accept these changes as is.
:100644 100644 aa9a7b6... f8ef142... M gnetlist/src/g_netlist.c
:100644 100644 65641ae... 6d5de41... M gnetlist/tests/common/outputs/PCBboard/cascade-output.net
:100644 100644 5492bf8... f7d2890... M gnetlist/tests/common/outputs/allegro/JD-output.net
:100644 100644 5492bf8... f7d2890... M gnetlist/tests/common/outputs/allegro/JD_Include-output.net
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:100644 100644 4614352... d577f9e... M gnetlist/tests/common/outputs/protelII/multiequal-output.net
:100644 100644 d06c95d... 518684b... M gnetlist/tests/common/outputs/protelII/netattrib-output.net
:100644 100644 0dd831a... a376138... M gnetlist/tests/common/outputs/protelII/powersupply-output.net
:100644 100644 e1bb285... 0a05417... M gnetlist/tests/common/outputs/spice-sdb/JD-output.net
:100644 100644 647fbff... c0a926e... M gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
:100644 100644 eec3dd1... 6d91f4b... M gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
:100644 100644 cfaab32... 70bef5b... M gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
:100644 100644 3fa5a97... 233a4d1... M gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
:100644 100644 6b45461... 2583d1d... M gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
:100644 100644 53dbc40... 56db97e... M gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
:100644 100644 13f8df9... 6b94c5c... M gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
:100644 100644 775b16e... c9982c8... M gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
:100644 100644 8902cec... 9d6040b... M gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
:100644 100644 21adb89... 210c1f4... M gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD_Include-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD_Sort-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
:100644 100644 9c485da... d5c82c3... M gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
:100644 100644 a91f1a6... 5e8b1d9... M gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
:100644 100644 a91f1a6... 5e8b1d9... M gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
:100644 100644 a91f1a6... 5e8b1d9... M gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
:100644 100644 a578dfa... f466b73... M gnetlist/tests/common/outputs/spice/cascade-output.net
:100644 100644 0ed4801... 1e4a9cc... M gnetlist/tests/common/outputs/spice/multiequal-output.net
:100644 100644 f2d3500... 1d4c88e... M gnetlist/tests/common/outputs/spice/netattrib-output.net
:100644 100644 f52e908... 482a411... M gnetlist/tests/common/outputs/spice/powersupply-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD_Include-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD_Include_nomunge-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD_Sort-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge-output.net
:100644 100644 8c3783a... 9bb9af3... M gnetlist/tests/common/outputs/systemc/JD_nomunge-output.net
:100644 100644 bc07ad1... 1067781... M gnetlist/tests/common/outputs/systemc/TwoStageAmp-output.net
:100644 100644 bc07ad1... 1067781... M gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include-output.net
:100644 100644 bc07ad1... 1067781... M gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort-output.net
:100644 100644 14254df... c5df0e6... M gnetlist/tests/common/outputs/systemc/cascade-output.net
:100644 100644 c65bb1a... cc69709... M gnetlist/tests/common/outputs/systemc/multiequal-output.net
:100644 100644 295e05c... d014a09... M gnetlist/tests/common/outputs/systemc/netattrib-output.net
:100644 100644 a12b8de... 8b53306... M gnetlist/tests/common/outputs/systemc/powersupply-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD_Include-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD_Sort-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
:100644 100644 e4c961a... 246256d... M gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
:100644 100644 42312fd... 29bab15... M gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
:100644 100644 42312fd... 29bab15... M gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
:100644 100644 42312fd... 29bab15... M gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
:100644 100644 f21920b... 07552b1... M gnetlist/tests/common/outputs/tango/cascade-output.net
:100644 100644 96b14bc... dc357ef... M gnetlist/tests/common/outputs/tango/multiequal-output.net
:100644 100644 6ef1d9d... a859cef... M gnetlist/tests/common/outputs/tango/netattrib-output.net
:100644 100644 96576c4... 56453f0... M gnetlist/tests/common/outputs/tango/powersupply-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD_Include-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD_Sort-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
:100644 100644 103b337... 7dcdf01... M gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
:100644 100644 95a10a5... 42676c2... M gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
:100644 100644 95a10a5... 42676c2... M gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
:100644 100644 95a10a5... 42676c2... M gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
:100644 100644 9e52aae... fa06718... M gnetlist/tests/common/outputs/vams/cascade-output.net
:100644 100644 52043c4... 4d8d95e... M gnetlist/tests/common/outputs/vams/multiequal-output.net
:100644 100644 39dc79a... ba111c8... M gnetlist/tests/common/outputs/vams/netattrib-output.net
:100644 100644 a90b651... 92782b5... M gnetlist/tests/common/outputs/vams/powersupply-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Include-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
:100644 100644 0d5313b... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
:100644 100644 dec17e9... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
:100644 100644 dec17e9... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
:100644 100644 dec17e9... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
:100644 100644 af96ecc... 5af04ac... M gnetlist/tests/common/outputs/verilog/cascade-output.net
:100644 100644 2d57b47... 5a2fe51... M gnetlist/tests/common/outputs/verilog/multiequal-output.net
:100644 100644 1e1836c... dba917e... M gnetlist/tests/common/outputs/verilog/netattrib-output.net
:100644 100644 9386f4b... 3611994... M gnetlist/tests/common/outputs/verilog/powersupply-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
:100644 100644 534f455... d3589de... M gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
:100644 100644 30a9a84... 35595e0... M gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
:100644 100644 30a9a84... 35595e0... M gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
:100644 100644 30a9a84... 35595e0... M gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
:100644 100644 3ff2e72... 5c70356... M gnetlist/tests/common/outputs/vhdl/cascade-output.net
:100644 100644 68da18d... cd7166f... M gnetlist/tests/common/outputs/vhdl/multiequal-output.net
:100644 100644 a97e18e... f36d919... M gnetlist/tests/common/outputs/vhdl/netattrib-output.net
:100644 100644 b815feb... c05b54f... M gnetlist/tests/common/outputs/vhdl/powersupply-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD_Include-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
:100644 100644 c7cd2ab... 48899a3... M gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
:100644 100644 a5eda3f... b030f3e... M gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
:100644 100644 a5eda3f... b030f3e... M gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
:100644 100644 a5eda3f... b030f3e... M gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
:100644 100644 75b0b79... d369aac... M gnetlist/tests/common/outputs/vipec/cascade-output.net
:100644 100644 a800cc8... 818ce82... M gnetlist/tests/common/outputs/vipec/multiequal-output.net
:100644 100644 9685438... 6f9f3c3... M gnetlist/tests/common/outputs/vipec/netattrib-output.net
:100644 100644 6e9bd91... 7e018f9... M gnetlist/tests/common/outputs/vipec/powersupply-output.net
:100644 100644 4bf29fe... 7fae39f... M gnetlist/tests/hierarchy/hierarchy.geda
:100644 100644 d9ccdb8... 93b391f... M gnetlist/tests/multiequal.spice-sdb
:100644 100644 684efb0... 5910ebd... M gnetlist/tests/netattrib.geda
:100644 100644 a338584... c7a407b... M gnetlist/tests/powersupply.allegro
:100644 100644 86ab354... 0f6eea0... M gnetlist/tests/powersupply.bae
:100644 100644 3471ddb... b4bc97c... M gnetlist/tests/powersupply.geda
:100644 100644 dd9b9bd... 2892cf5... M gnetlist/tests/powersupply.maxascii
:100644 100644 3aa5cd9... 0688481... M gnetlist/tests/powersupply.pads
:100644 100644 0dd831a... a376138... M gnetlist/tests/powersupply.protelII
:100644 100644 96576c4... 56453f0... M gnetlist/tests/powersupply.tango
:100644 100644 0d2d410... 6bf97c5... M gnetlist/tests/stack_1.geda
=========
Changes
=========
commit 2d888258d954c993aa03e4a1beb7b03e62df4d95
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Thu Jan 8 00:45:28 2009 +0000
gnetlist: Avoid depending on GHashTable ordering for output consistency
If the GLib hash table changes (which it has in late versions of GLib),
the netlist output ordering changes due to our mis-use of GHashTable to
list all unique component names without enforcing any eplicit order on
the enumeration of the hash table contents.
Since ordering may be important to backends, want to have known output
ordering whilst removing duplicate entrys, but without an explicit sort
of the refdes list.
This commit introduces an incremental build of the list, first checking
the hash table for a hit, and only adding the new refdes if it wasn't
already in the has table. This is gives the output a predictable order
(based on the input), rather than inserting all refdes into the hash
table, and building the list in whatever order the table implentation
traverses them in.
This change does unfortunately means a large number or ordering related
changes are also made in the gnetlist test suite's golden files.
There are also some non-ordering changes in the checked in golden files.
These is encountered in the pretty well obsolete PCBboard backend - which
errors out when it hits certain components it can't find footprints for.
Changing the ordering changes the point at which it dies, and thus the
netlist output. Lets just accept these changes as is.
diff --git a/gnetlist/src/g_netlist.c b/gnetlist/src/g_netlist.c
index aa9a7b6..f8ef142 100644
--- a/gnetlist/src/g_netlist.c
+++ b/gnetlist/src/g_netlist.c
@@ -45,18 +45,6 @@ void g_set_project_current(TOPLEVEL * pr_current)
}
-static void
-hash_table_2_list (gpointer key,
- gpointer value,
- gpointer user_data)
-{
- SCM* plist = (SCM*)user_data;
-
- *plist = scm_cons (scm_makfrom0str ((char*)value),
- *plist);
-}
-
-
SCM g_scm_c_get_uref (TOPLEVEL *toplevel, OBJECT *object)
{
SCM func = scm_variable_ref (scm_c_lookup ("get-uref"));
@@ -84,13 +72,14 @@ SCM g_get_packages(SCM level)
if (nl_current->component_uref != NULL) {
/* add component_uref in the hash table */
/* uniqueness of component_uref is guaranteed by the hashtable */
- g_hash_table_insert (ht,
- nl_current->component_uref,
- nl_current->component_uref);
+
+ if (g_hash_table_lookup (ht, nl_current->component_uref) == NULL) {
+ g_hash_table_insert (ht, nl_current->component_uref,
+ nl_current->component_uref);
+ list = scm_cons (scm_makfrom0str (nl_current->component_uref), list);
+ }
}
}
- /* now create a scheme list of the entries in the hash table */
- g_hash_table_foreach (ht, hash_table_2_list, &list);
g_hash_table_destroy (ht);
return list;
diff --git a/gnetlist/tests/common/outputs/PCBboard/cascade-output.net b/gnetlist/tests/common/outputs/PCBboard/cascade-output.net
index 65641ae..6d5de41 100644
--- a/gnetlist/tests/common/outputs/PCBboard/cascade-output.net
+++ b/gnetlist/tests/common/outputs/PCBboard/cascade-output.net
@@ -6,6 +6,10 @@ Flags(0x000000d0)
Groups("1,2,3,s:4,5,6,c:7:8:")
Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
PKG_none(cascade-amp,AMP2,unknown)
+PKG_none(cascade-transformer,T1,unknown)
+PKG_none(cascade-mixer,MX1,unknown)
+PKG_none(cascade-filter,FL1,unknown)
+PKG_none(cascade-defaults,DEF1,unknown)
PKG_none(cascade-amp,AMP1,unknown)
PKG_none(cascade-source,SOURCE,unknown)
Layer(1 "solder")
diff --git a/gnetlist/tests/common/outputs/allegro/JD-output.net b/gnetlist/tests/common/outputs/allegro/JD-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include-output.net b/gnetlist/tests/common/outputs/allegro/JD_Include-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net b/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
index 5492bf8..f7d2890 100644
--- a/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
-! CAPACITOR! 20p; Cm
! model! model; A1
-! RESISTOR! 1k; Rt
-! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
-! LVD! LVD; X1
+! CAPACITOR! 20p; Cm
+! CAPACITOR! 20p; Cp
! RESISTOR! 1meg; Rlp
-none! VOLTAGE_SOURCE! DC 3.3V; Vdd
! RESISTOR! 500k; Rlm
-! CAPACITOR! 20p; Cp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! RESISTOR! 1k; Rt
! RESISTOR! 5.6k; Rb
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
$NETS
Vdd1; Rlp.2,
M1.B,
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
index d48fc78..cb4cd25 100644
--- a/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
@@ -1,28 +1,28 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-! CAPACITOR! 2.2uF; Cout
-! RESISTOR! 10; R5
+! CAPACITOR! 2.2uF; C2
! RESISTOR! 2.8K; R4
+! RESISTOR! 28K; R3
+! RESISTOR! 1; R8
+! CAPACITOR! 1pF; CE2
! RESISTOR! 100; RE2
+! RESISTOR! 3.3K; RC1
! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! CAPACITOR! 2.2uF; C1
! directive! .options TEMP=25; A3
-! RESISTOR! 28K; R3
! include! include; A2
-! RESISTOR! 100; RE1
-! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
! model! model; A1
-! RESISTOR! 2K; R2
+none! VOLTAGE_SOURCE! DC 15V; VCC
none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
-! RESISTOR! 28K; R1
-! CAPACITOR! 2.2uF; C2
-! CAPACITOR! 1pF; CE2
-! CAPACITOR! 2.2uF; C1
! CAPACITOR! 1pF; CE1
-! RESISTOR! 1; R8
-none! VOLTAGE_SOURCE! DC 15V; VCC
-! RESISTOR! 1K; RC2
-! RESISTOR! 3.3K; RC1
+! CAPACITOR! 2.2uF; Cout
! RESISTOR! 100K; RL
+! RESISTOR! 1K; RC2
+! RESISTOR! 100; RE1
+! RESISTOR! 2K; R2
+! RESISTOR! 28K; R1
+! RESISTOR! 10; R5
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
$NETS
unnamed_net2; C2.1,
R8.2
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
index d48fc78..cb4cd25 100644
--- a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
@@ -1,28 +1,28 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-! CAPACITOR! 2.2uF; Cout
-! RESISTOR! 10; R5
+! CAPACITOR! 2.2uF; C2
! RESISTOR! 2.8K; R4
+! RESISTOR! 28K; R3
+! RESISTOR! 1; R8
+! CAPACITOR! 1pF; CE2
! RESISTOR! 100; RE2
+! RESISTOR! 3.3K; RC1
! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! CAPACITOR! 2.2uF; C1
! directive! .options TEMP=25; A3
-! RESISTOR! 28K; R3
! include! include; A2
-! RESISTOR! 100; RE1
-! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
! model! model; A1
-! RESISTOR! 2K; R2
+none! VOLTAGE_SOURCE! DC 15V; VCC
none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
-! RESISTOR! 28K; R1
-! CAPACITOR! 2.2uF; C2
-! CAPACITOR! 1pF; CE2
-! CAPACITOR! 2.2uF; C1
! CAPACITOR! 1pF; CE1
-! RESISTOR! 1; R8
-none! VOLTAGE_SOURCE! DC 15V; VCC
-! RESISTOR! 1K; RC2
-! RESISTOR! 3.3K; RC1
+! CAPACITOR! 2.2uF; Cout
! RESISTOR! 100K; RL
+! RESISTOR! 1K; RC2
+! RESISTOR! 100; RE1
+! RESISTOR! 2K; R2
+! RESISTOR! 28K; R1
+! RESISTOR! 10; R5
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
$NETS
unnamed_net2; C2.1,
R8.2
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
index d48fc78..cb4cd25 100644
--- a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
@@ -1,28 +1,28 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-! CAPACITOR! 2.2uF; Cout
-! RESISTOR! 10; R5
+! CAPACITOR! 2.2uF; C2
! RESISTOR! 2.8K; R4
+! RESISTOR! 28K; R3
+! RESISTOR! 1; R8
+! CAPACITOR! 1pF; CE2
! RESISTOR! 100; RE2
+! RESISTOR! 3.3K; RC1
! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! CAPACITOR! 2.2uF; C1
! directive! .options TEMP=25; A3
-! RESISTOR! 28K; R3
! include! include; A2
-! RESISTOR! 100; RE1
-! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
! model! model; A1
-! RESISTOR! 2K; R2
+none! VOLTAGE_SOURCE! DC 15V; VCC
none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
-! RESISTOR! 28K; R1
-! CAPACITOR! 2.2uF; C2
-! CAPACITOR! 1pF; CE2
-! CAPACITOR! 2.2uF; C1
! CAPACITOR! 1pF; CE1
-! RESISTOR! 1; R8
-none! VOLTAGE_SOURCE! DC 15V; VCC
-! RESISTOR! 1K; RC2
-! RESISTOR! 3.3K; RC1
+! CAPACITOR! 2.2uF; Cout
! RESISTOR! 100K; RL
+! RESISTOR! 1K; RC2
+! RESISTOR! 100; RE1
+! RESISTOR! 2K; R2
+! RESISTOR! 28K; R1
+! RESISTOR! 10; R5
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
$NETS
unnamed_net2; C2.1,
R8.2
diff --git a/gnetlist/tests/common/outputs/allegro/cascade-output.net b/gnetlist/tests/common/outputs/allegro/cascade-output.net
index 9ad1608..c90384e 100644
--- a/gnetlist/tests/common/outputs/allegro/cascade-output.net
+++ b/gnetlist/tests/common/outputs/allegro/cascade-output.net
@@ -1,13 +1,13 @@
(Allegro netlister by M. Ettus)
$PACKAGES
none! cascade-amp! cascade-amp; AMP2
+none! cascade-transformer! cascade-transformer; T1
+none! cascade-mixer! cascade-mixer; MX1
+none! cascade-filter! cascade-filter; FL1
+none! cascade-defaults! cascade-defaults; DEF1
none! cascade-amp! cascade-amp; AMP1
none! cascade-source! cascade-source; SOURCE
! cascade-defaults-top! cascade-defaults-top; DEFAULTS
-none! cascade-mixer! cascade-mixer; MX1
-none! cascade-defaults! cascade-defaults; DEF1
-none! cascade-transformer! cascade-transformer; T1
-none! cascade-filter! cascade-filter; FL1
$NETS
unnamed_net6; AMP2.1,
T1.2
diff --git a/gnetlist/tests/common/outputs/allegro/multiequal-output.net b/gnetlist/tests/common/outputs/allegro/multiequal-output.net
index f59daf7..10505ef 100644
--- a/gnetlist/tests/common/outputs/allegro/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/allegro/multiequal-output.net
@@ -1,8 +1,8 @@
(Allegro netlister by M. Ettus)
$PACKAGES
none! VOLTAGE_SOURCE! DC 1V; V1
-! options! abotol=1e-11; A1
! RESISTOR! 20; R1
+! options! abotol=1e-11; A1
$NETS
GND; V1.2,
R1.1
diff --git a/gnetlist/tests/common/outputs/allegro/netattrib-output.net b/gnetlist/tests/common/outputs/allegro/netattrib-output.net
index ac3f34a..b04beef 100644
--- a/gnetlist/tests/common/outputs/allegro/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/allegro/netattrib-output.net
@@ -1,9 +1,9 @@
(Allegro netlister by M. Ettus)
$PACKAGES
! FUSE! FUSE; F1
-DIP14! 7400! 7400; U100
DIP14! 7404! 7404; U300
DIP14! 7404! 7404; U200
+DIP14! 7400! 7400; U100
$NETS
unnamed_net1; U300.2
netattrib; U200.2,
diff --git a/gnetlist/tests/common/outputs/allegro/powersupply-output.net b/gnetlist/tests/common/outputs/allegro/powersupply-output.net
index a338584..c7a407b 100644
--- a/gnetlist/tests/common/outputs/allegro/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/allegro/powersupply-output.net
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-! FUSE! FUSE; F1
-! RESISTOR! 220; R2
-! MAINS_CONNECTOR! MAINS_CONNECTOR; CONN1
+! LM317! LM317; U2
! POLARIZED_CAPACITOR! 1uf; C4
-! VARIABLE_RESISTOR! 5k; R1
! POLARIZED_CAPACITOR! 22uF; C3
+! VARIABLE_RESISTOR! 5k; R1
! POLARIZED_CAPACITOR! 0.1uF; C2
-! SPST! SPST; S1
+! RESISTOR! 220; R2
! POLARIZED_CAPACITOR! 2200uF; C1
+! SPST! SPST; S1
+! MAINS_CONNECTOR! MAINS_CONNECTOR; CONN1
! transformer! transformer; T1
-! LM317! LM317; U2
+! FUSE! FUSE; F1
! DIODE-BRIDGE! DIODE-BRIDGE; U1
$NETS
ten; U2.1,
diff --git a/gnetlist/tests/common/outputs/bae/JD-output.net b/gnetlist/tests/common/outputs/bae/JD-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include-output.net b/gnetlist/tests/common/outputs/bae/JD_Include-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD_Include-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort-output.net b/gnetlist/tests/common/outputs/bae/JD_Sort-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net
index 2878a95..8e9f05b 100644
--- a/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- V1 : none;
- Cm : unknown;
A1 : unknown;
- Rt : unknown;
- M1 : unknown;
- X1 : unknown;
+ Cm : unknown;
+ Cp : unknown;
Rlp : unknown;
- Vdd : none;
Rlm : unknown;
- Cp : unknown;
+ Vdd : none;
+ V1 : none;
+ Rt : unknown;
Rb : unknown;
+ M1 : unknown;
+ X1 : unknown;
CONNECT
/'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
/'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net
index 6450391..cfa7ed6 100644
--- a/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net
@@ -1,28 +1,28 @@
LAYOUT board;
PARTS
- Cout : unknown;
- R5 : unknown;
+ C2 : unknown;
R4 : unknown;
+ R3 : unknown;
+ R8 : unknown;
+ CE2 : unknown;
RE2 : unknown;
+ RC1 : unknown;
Q2 : unknown;
+ C1 : unknown;
A3 : unknown;
- R3 : unknown;
A2 : unknown;
- RE1 : unknown;
- Q1 : unknown;
A1 : unknown;
- R2 : unknown;
+ VCC : none;
Vinput : none;
- R1 : unknown;
- C2 : unknown;
- CE2 : unknown;
- C1 : unknown;
CE1 : unknown;
- R8 : unknown;
- VCC : none;
- RC2 : unknown;
- RC1 : unknown;
+ Cout : unknown;
RL : unknown;
+ RC2 : unknown;
+ RE1 : unknown;
+ R2 : unknown;
+ R1 : unknown;
+ R5 : unknown;
+ Q1 : unknown;
CONNECT
/'unnamed_net2'/ C2.1=R8.2;
/'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net
index 6450391..cfa7ed6 100644
--- a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net
@@ -1,28 +1,28 @@
LAYOUT board;
PARTS
- Cout : unknown;
- R5 : unknown;
+ C2 : unknown;
R4 : unknown;
+ R3 : unknown;
+ R8 : unknown;
+ CE2 : unknown;
RE2 : unknown;
+ RC1 : unknown;
Q2 : unknown;
+ C1 : unknown;
A3 : unknown;
- R3 : unknown;
A2 : unknown;
- RE1 : unknown;
- Q1 : unknown;
A1 : unknown;
- R2 : unknown;
+ VCC : none;
Vinput : none;
- R1 : unknown;
- C2 : unknown;
- CE2 : unknown;
- C1 : unknown;
CE1 : unknown;
- R8 : unknown;
- VCC : none;
- RC2 : unknown;
- RC1 : unknown;
+ Cout : unknown;
RL : unknown;
+ RC2 : unknown;
+ RE1 : unknown;
+ R2 : unknown;
+ R1 : unknown;
+ R5 : unknown;
+ Q1 : unknown;
CONNECT
/'unnamed_net2'/ C2.1=R8.2;
/'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net
index 6450391..cfa7ed6 100644
--- a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net
@@ -1,28 +1,28 @@
LAYOUT board;
PARTS
- Cout : unknown;
- R5 : unknown;
+ C2 : unknown;
R4 : unknown;
+ R3 : unknown;
+ R8 : unknown;
+ CE2 : unknown;
RE2 : unknown;
+ RC1 : unknown;
Q2 : unknown;
+ C1 : unknown;
A3 : unknown;
- R3 : unknown;
A2 : unknown;
- RE1 : unknown;
- Q1 : unknown;
A1 : unknown;
- R2 : unknown;
+ VCC : none;
Vinput : none;
- R1 : unknown;
- C2 : unknown;
- CE2 : unknown;
- C1 : unknown;
CE1 : unknown;
- R8 : unknown;
- VCC : none;
- RC2 : unknown;
- RC1 : unknown;
+ Cout : unknown;
RL : unknown;
+ RC2 : unknown;
+ RE1 : unknown;
+ R2 : unknown;
+ R1 : unknown;
+ R5 : unknown;
+ Q1 : unknown;
CONNECT
/'unnamed_net2'/ C2.1=R8.2;
/'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
diff --git a/gnetlist/tests/common/outputs/bae/cascade-output.net b/gnetlist/tests/common/outputs/bae/cascade-output.net
index fbef6eb..b09a073 100644
--- a/gnetlist/tests/common/outputs/bae/cascade-output.net
+++ b/gnetlist/tests/common/outputs/bae/cascade-output.net
@@ -1,13 +1,13 @@
LAYOUT board;
PARTS
AMP2 : none;
+ T1 : none;
+ MX1 : none;
+ FL1 : none;
+ DEF1 : none;
AMP1 : none;
SOURCE : none;
DEFAULTS : unknown;
- MX1 : none;
- DEF1 : none;
- T1 : none;
- FL1 : none;
CONNECT
/'unnamed_net6'/ AMP2.1=T1.2;
/'unnamed_net5'/ T1.1=MX1.2;
diff --git a/gnetlist/tests/common/outputs/bae/multiequal-output.net b/gnetlist/tests/common/outputs/bae/multiequal-output.net
index 0cd5f05..5e7d7ae 100644
--- a/gnetlist/tests/common/outputs/bae/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/bae/multiequal-output.net
@@ -1,8 +1,8 @@
LAYOUT board;
PARTS
V1 : none;
- A1 : unknown;
R1 : unknown;
+ A1 : unknown;
CONNECT
/'GND'/ V1.2=R1.1;
/'unnamed_net1'/ V1.1=R1.2;
diff --git a/gnetlist/tests/common/outputs/bae/netattrib-output.net b/gnetlist/tests/common/outputs/bae/netattrib-output.net
index 8534472..359311e 100644
--- a/gnetlist/tests/common/outputs/bae/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/bae/netattrib-output.net
@@ -1,9 +1,9 @@
LAYOUT board;
PARTS
F1 : unknown;
- U100 : DIP14;
U300 : DIP14;
U200 : DIP14;
+ U100 : DIP14;
CONNECT
/'unnamed_net1'/ U300.2;
/'netattrib'/ U200.2=U100.5;
diff --git a/gnetlist/tests/common/outputs/bae/powersupply-output.net b/gnetlist/tests/common/outputs/bae/powersupply-output.net
index 86ab354..0f6eea0 100644
--- a/gnetlist/tests/common/outputs/bae/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/bae/powersupply-output.net
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- F1 : unknown;
- R2 : unknown;
- CONN1 : unknown;
+ U2 : unknown;
C4 : unknown;
- R1 : unknown;
C3 : unknown;
+ R1 : unknown;
C2 : unknown;
- S1 : unknown;
+ R2 : unknown;
C1 : unknown;
+ S1 : unknown;
+ CONN1 : unknown;
T1 : unknown;
- U2 : unknown;
+ F1 : unknown;
U1 : unknown;
CONNECT
/'ten'/ U2.1=R1.2=C3.1=R2.1;
diff --git a/gnetlist/tests/common/outputs/bom/JD-output.net b/gnetlist/tests/common/outputs/bom/JD-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include-output.net b/gnetlist/tests/common/outputs/bom/JD_Include-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD_Include-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort-output.net b/gnetlist/tests/common/outputs/bom/JD_Sort-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net
index e7a17b1..f6a6bef 100644
--- a/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net
@@ -1,12 +1,12 @@
refdes refdes value device
-V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
-Cm Cm 20p CAPACITOR
A1 A1 unknown model
-Rt Rt 1k RESISTOR
-M1 M1 unknown PMOS_TRANSISTOR
-X1 X1 unknown LVD
+Cm Cm 20p CAPACITOR
+Cp Cp 20p CAPACITOR
Rlp Rlp 1meg RESISTOR
-Vdd Vdd DC 3.3V VOLTAGE_SOURCE
Rlm Rlm 500k RESISTOR
-Cp Cp 20p CAPACITOR
+Vdd Vdd DC 3.3V VOLTAGE_SOURCE
+V1 V1 pulse 3.3 0 1u 10p 10p 1.25u 2.5u vpulse
+Rt Rt 1k RESISTOR
Rb Rb 5.6k RESISTOR
+M1 M1 unknown PMOS_TRANSISTOR
+X1 X1 unknown LVD
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net
index ebb4a75..6884764 100644
--- a/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net
@@ -1,24 +1,24 @@
refdes refdes value device
-Cout Cout 2.2uF CAPACITOR
-R5 R5 10 RESISTOR
+C2 C2 2.2uF CAPACITOR
R4 R4 2.8K RESISTOR
+R3 R3 28K RESISTOR
+R8 R8 1 RESISTOR
+CE2 CE2 1pF CAPACITOR
RE2 RE2 100 RESISTOR
+RC1 RC1 3.3K RESISTOR
Q2 Q2 unknown NPN_TRANSISTOR
+C1 C1 2.2uF CAPACITOR
A3 A3 .options TEMP=25 directive
-R3 R3 28K RESISTOR
A2 A2 unknown include
-RE1 RE1 100 RESISTOR
-Q1 Q1 unknown NPN_TRANSISTOR
A1 A1 unknown model
-R2 R2 2K RESISTOR
+VCC VCC DC 15V VOLTAGE_SOURCE
Vinput Vinput DC 1.6V AC 10MV SIN(0 1MV 1KHZ) vsin
-R1 R1 28K RESISTOR
-C2 C2 2.2uF CAPACITOR
-CE2 CE2 1pF CAPACITOR
-C1 C1 2.2uF CAPACITOR
CE1 CE1 1pF CAPACITOR
-R8 R8 1 RESISTOR
-VCC VCC DC 15V VOLTAGE_SOURCE
-RC2 RC2 1K RESISTOR
-RC1 RC1 3.3K RESISTOR
+Cout Cout 2.2uF CAPACITOR
RL RL 100K RESISTOR
+RC2 RC2 1K RESISTOR
+RE1 RE1 100 RESISTOR
+R2 R2 2K RESISTOR
+R1 R1 28K RESISTOR
+R5 R5 10 RESISTOR
+Q1 Q1 unknown NPN_TRANSISTOR
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net
index ebb4a75..6884764 100644
--- a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net
@@ -1,24 +1,24 @@
refdes refdes value device
-Cout Cout 2.2uF CAPACITOR
-R5 R5 10 RESISTOR
+C2 C2 2.2uF CAPACITOR
R4 R4 2.8K RESISTOR
+R3 R3 28K RESISTOR
+R8 R8 1 RESISTOR
+CE2 CE2 1pF CAPACITOR
RE2 RE2 100 RESISTOR
+RC1 RC1 3.3K RESISTOR
Q2 Q2 unknown NPN_TRANSISTOR
+C1 C1 2.2uF CAPACITOR
A3 A3 .options TEMP=25 directive
-R3 R3 28K RESISTOR
A2 A2 unknown include
-RE1 RE1 100 RESISTOR
-Q1 Q1 unknown NPN_TRANSISTOR
A1 A1 unknown model
-R2 R2 2K RESISTOR
+VCC VCC DC 15V VOLTAGE_SOURCE
Vinput Vinput DC 1.6V AC 10MV SIN(0 1MV 1KHZ) vsin
-R1 R1 28K RESISTOR
-C2 C2 2.2uF CAPACITOR
-CE2 CE2 1pF CAPACITOR
-C1 C1 2.2uF CAPACITOR
CE1 CE1 1pF CAPACITOR
-R8 R8 1 RESISTOR
-VCC VCC DC 15V VOLTAGE_SOURCE
-RC2 RC2 1K RESISTOR
-RC1 RC1 3.3K RESISTOR
+Cout Cout 2.2uF CAPACITOR
RL RL 100K RESISTOR
+RC2 RC2 1K RESISTOR
+RE1 RE1 100 RESISTOR
+R2 R2 2K RESISTOR
+R1 R1 28K RESISTOR
+R5 R5 10 RESISTOR
+Q1 Q1 unknown NPN_TRANSISTOR
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net
index ebb4a75..6884764 100644
--- a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net
@@ -1,24 +1,24 @@
refdes refdes value device
-Cout Cout 2.2uF CAPACITOR
-R5 R5 10 RESISTOR
+C2 C2 2.2uF CAPACITOR
R4 R4 2.8K RESISTOR
+R3 R3 28K RESISTOR
+R8 R8 1 RESISTOR
+CE2 CE2 1pF CAPACITOR
RE2 RE2 100 RESISTOR
+RC1 RC1 3.3K RESISTOR
Q2 Q2 unknown NPN_TRANSISTOR
+C1 C1 2.2uF CAPACITOR
A3 A3 .options TEMP=25 directive
-R3 R3 28K RESISTOR
A2 A2 unknown include
-RE1 RE1 100 RESISTOR
-Q1 Q1 unknown NPN_TRANSISTOR
A1 A1 unknown model
-R2 R2 2K RESISTOR
+VCC VCC DC 15V VOLTAGE_SOURCE
Vinput Vinput DC 1.6V AC 10MV SIN(0 1MV 1KHZ) vsin
-R1 R1 28K RESISTOR
-C2 C2 2.2uF CAPACITOR
-CE2 CE2 1pF CAPACITOR
-C1 C1 2.2uF CAPACITOR
CE1 CE1 1pF CAPACITOR
-R8 R8 1 RESISTOR
-VCC VCC DC 15V VOLTAGE_SOURCE
-RC2 RC2 1K RESISTOR
-RC1 RC1 3.3K RESISTOR
+Cout Cout 2.2uF CAPACITOR
RL RL 100K RESISTOR
+RC2 RC2 1K RESISTOR
+RE1 RE1 100 RESISTOR
+R2 R2 2K RESISTOR
+R1 R1 28K RESISTOR
+R5 R5 10 RESISTOR
+Q1 Q1 unknown NPN_TRANSISTOR
diff --git a/gnetlist/tests/common/outputs/bom/cascade-output.net b/gnetlist/tests/common/outputs/bom/cascade-output.net
index d13c8ae..c742ecb 100644
--- a/gnetlist/tests/common/outputs/bom/cascade-output.net
+++ b/gnetlist/tests/common/outputs/bom/cascade-output.net
@@ -1,9 +1,9 @@
refdes refdes value device
AMP2 AMP2 unknown cascade-amp
+T1 T1 unknown cascade-transformer
+MX1 MX1 unknown cascade-mixer
+FL1 FL1 unknown cascade-filter
+DEF1 DEF1 unknown cascade-defaults
AMP1 AMP1 unknown cascade-amp
SOURCE SOURCE unknown cascade-source
DEFAULTS DEFAULTS unknown cascade-defaults-top
-MX1 MX1 unknown cascade-mixer
-DEF1 DEF1 unknown cascade-defaults
-T1 T1 unknown cascade-transformer
-FL1 FL1 unknown cascade-filter
diff --git a/gnetlist/tests/common/outputs/bom/multiequal-output.net b/gnetlist/tests/common/outputs/bom/multiequal-output.net
index fa479d6..a10be70 100644
--- a/gnetlist/tests/common/outputs/bom/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/bom/multiequal-output.net
@@ -1,4 +1,4 @@
refdes refdes value device
V1 V1 DC 1V VOLTAGE_SOURCE
-A1 A1 abotol=1e-11 options
R1 R1 20 RESISTOR
+A1 A1 abotol=1e-11 options
diff --git a/gnetlist/tests/common/outputs/bom/netattrib-output.net b/gnetlist/tests/common/outputs/bom/netattrib-output.net
index 6d12770..bed8838 100644
--- a/gnetlist/tests/common/outputs/bom/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/bom/netattrib-output.net
@@ -1,5 +1,5 @@
refdes refdes value device
F1 F1 unknown FUSE
-U100 U100 unknown 7400
U300 U300 unknown 7404
U200 U200 unknown 7404
+U100 U100 unknown 7400
diff --git a/gnetlist/tests/common/outputs/bom/powersupply-output.net b/gnetlist/tests/common/outputs/bom/powersupply-output.net
index 42c7e2f..79a31a7 100644
--- a/gnetlist/tests/common/outputs/bom/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/bom/powersupply-output.net
@@ -1,13 +1,13 @@
refdes refdes value device
-F1 F1 unknown FUSE
-R2 R2 220 RESISTOR
-CONN1 CONN1 unknown MAINS_CONNECTOR
+U2 U2 unknown LM317
C4 C4 1uf POLARIZED_CAPACITOR
-R1 R1 5k VARIABLE_RESISTOR
C3 C3 22uF POLARIZED_CAPACITOR
+R1 R1 5k VARIABLE_RESISTOR
C2 C2 0.1uF POLARIZED_CAPACITOR
-S1 S1 unknown SPST
+R2 R2 220 RESISTOR
C1 C1 2200uF POLARIZED_CAPACITOR
+S1 S1 unknown SPST
+CONN1 CONN1 unknown MAINS_CONNECTOR
T1 T1 unknown transformer
-U2 U2 unknown LM317
+F1 F1 unknown FUSE
U1 U1 unknown DIODE-BRIDGE
diff --git a/gnetlist/tests/common/outputs/bom2/JD-output.net b/gnetlist/tests/common/outputs/bom2/JD-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include-output.net b/gnetlist/tests/common/outputs/bom2/JD_Include-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net b/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net
index 3d13386..5c04b06 100644
--- a/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net
@@ -1,12 +1,12 @@
refdes:refdes:value:device:qty
-Rb:Rb:5.6k:RESISTOR:1
-Cp:Cp:20p:CAPACITOR:1
-Rlm:Rlm:500k:RESISTOR:1
-Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
-Rlp:Rlp:1meg:RESISTOR:1
X1:X1:unknown:LVD:1
M1:M1:unknown:PMOS_TRANSISTOR:1
+Rb:Rb:5.6k:RESISTOR:1
Rt:Rt:1k:RESISTOR:1
-A1:A1:unknown:model:1
-Cm:Cm:20p:CAPACITOR:1
V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse:1
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE:1
+Rlm:Rlm:500k:RESISTOR:1
+Rlp:Rlp:1meg:RESISTOR:1
+Cp:Cp:20p:CAPACITOR:1
+Cm:Cm:20p:CAPACITOR:1
+A1:A1:unknown:model:1
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net
index 77f6e4f..8112a83 100644
--- a/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net
@@ -1,24 +1,24 @@
refdes:refdes:value:device:qty
-RL:RL:100K:RESISTOR:1
-RC1:RC1:3.3K:RESISTOR:1
+Q1:Q1:unknown:NPN_TRANSISTOR:1
+R5:R5:10:RESISTOR:1
+R1:R1:28K:RESISTOR:1
+R2:R2:2K:RESISTOR:1
+RE1:RE1:100:RESISTOR:1
RC2:RC2:1K:RESISTOR:1
-VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
-R8:R8:1:RESISTOR:1
+RL:RL:100K:RESISTOR:1
+Cout:Cout:2.2uF:CAPACITOR:1
CE1:CE1:1pF:CAPACITOR:1
-C1:C1:2.2uF:CAPACITOR:1
-CE2:CE2:1pF:CAPACITOR:1
-C2:C2:2.2uF:CAPACITOR:1
-R1:R1:28K:RESISTOR:1
Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin:1
-R2:R2:2K:RESISTOR:1
+VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
A1:A1:unknown:model:1
-Q1:Q1:unknown:NPN_TRANSISTOR:1
-RE1:RE1:100:RESISTOR:1
A2:A2:unknown:include:1
-R3:R3:28K:RESISTOR:1
A3:A3:.options TEMP=25:directive:1
+C1:C1:2.2uF:CAPACITOR:1
Q2:Q2:unknown:NPN_TRANSISTOR:1
+RC1:RC1:3.3K:RESISTOR:1
RE2:RE2:100:RESISTOR:1
+CE2:CE2:1pF:CAPACITOR:1
+R8:R8:1:RESISTOR:1
+R3:R3:28K:RESISTOR:1
R4:R4:2.8K:RESISTOR:1
-R5:R5:10:RESISTOR:1
-Cout:Cout:2.2uF:CAPACITOR:1
+C2:C2:2.2uF:CAPACITOR:1
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net
index 77f6e4f..8112a83 100644
--- a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net
@@ -1,24 +1,24 @@
refdes:refdes:value:device:qty
-RL:RL:100K:RESISTOR:1
-RC1:RC1:3.3K:RESISTOR:1
+Q1:Q1:unknown:NPN_TRANSISTOR:1
+R5:R5:10:RESISTOR:1
+R1:R1:28K:RESISTOR:1
+R2:R2:2K:RESISTOR:1
+RE1:RE1:100:RESISTOR:1
RC2:RC2:1K:RESISTOR:1
-VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
-R8:R8:1:RESISTOR:1
+RL:RL:100K:RESISTOR:1
+Cout:Cout:2.2uF:CAPACITOR:1
CE1:CE1:1pF:CAPACITOR:1
-C1:C1:2.2uF:CAPACITOR:1
-CE2:CE2:1pF:CAPACITOR:1
-C2:C2:2.2uF:CAPACITOR:1
-R1:R1:28K:RESISTOR:1
Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin:1
-R2:R2:2K:RESISTOR:1
+VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
A1:A1:unknown:model:1
-Q1:Q1:unknown:NPN_TRANSISTOR:1
-RE1:RE1:100:RESISTOR:1
A2:A2:unknown:include:1
-R3:R3:28K:RESISTOR:1
A3:A3:.options TEMP=25:directive:1
+C1:C1:2.2uF:CAPACITOR:1
Q2:Q2:unknown:NPN_TRANSISTOR:1
+RC1:RC1:3.3K:RESISTOR:1
RE2:RE2:100:RESISTOR:1
+CE2:CE2:1pF:CAPACITOR:1
+R8:R8:1:RESISTOR:1
+R3:R3:28K:RESISTOR:1
R4:R4:2.8K:RESISTOR:1
-R5:R5:10:RESISTOR:1
-Cout:Cout:2.2uF:CAPACITOR:1
+C2:C2:2.2uF:CAPACITOR:1
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net
index 77f6e4f..8112a83 100644
--- a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net
@@ -1,24 +1,24 @@
refdes:refdes:value:device:qty
-RL:RL:100K:RESISTOR:1
-RC1:RC1:3.3K:RESISTOR:1
+Q1:Q1:unknown:NPN_TRANSISTOR:1
+R5:R5:10:RESISTOR:1
+R1:R1:28K:RESISTOR:1
+R2:R2:2K:RESISTOR:1
+RE1:RE1:100:RESISTOR:1
RC2:RC2:1K:RESISTOR:1
-VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
-R8:R8:1:RESISTOR:1
+RL:RL:100K:RESISTOR:1
+Cout:Cout:2.2uF:CAPACITOR:1
CE1:CE1:1pF:CAPACITOR:1
-C1:C1:2.2uF:CAPACITOR:1
-CE2:CE2:1pF:CAPACITOR:1
-C2:C2:2.2uF:CAPACITOR:1
-R1:R1:28K:RESISTOR:1
Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin:1
-R2:R2:2K:RESISTOR:1
+VCC:VCC:DC 15V:VOLTAGE_SOURCE:1
A1:A1:unknown:model:1
-Q1:Q1:unknown:NPN_TRANSISTOR:1
-RE1:RE1:100:RESISTOR:1
A2:A2:unknown:include:1
-R3:R3:28K:RESISTOR:1
A3:A3:.options TEMP=25:directive:1
+C1:C1:2.2uF:CAPACITOR:1
Q2:Q2:unknown:NPN_TRANSISTOR:1
+RC1:RC1:3.3K:RESISTOR:1
RE2:RE2:100:RESISTOR:1
+CE2:CE2:1pF:CAPACITOR:1
+R8:R8:1:RESISTOR:1
+R3:R3:28K:RESISTOR:1
R4:R4:2.8K:RESISTOR:1
-R5:R5:10:RESISTOR:1
-Cout:Cout:2.2uF:CAPACITOR:1
+C2:C2:2.2uF:CAPACITOR:1
diff --git a/gnetlist/tests/common/outputs/bom2/cascade-output.net b/gnetlist/tests/common/outputs/bom2/cascade-output.net
index d7acdf8..3907507 100644
--- a/gnetlist/tests/common/outputs/bom2/cascade-output.net
+++ b/gnetlist/tests/common/outputs/bom2/cascade-output.net
@@ -1,9 +1,9 @@
refdes:refdes:value:device:qty
-FL1:FL1:unknown:cascade-filter:1
-T1:T1:unknown:cascade-transformer:1
-DEF1:DEF1:unknown:cascade-defaults:1
-MX1:MX1:unknown:cascade-mixer:1
DEFAULTS:DEFAULTS:unknown:cascade-defaults-top:1
SOURCE:SOURCE:unknown:cascade-source:1
AMP1:AMP1:unknown:cascade-amp:1
+DEF1:DEF1:unknown:cascade-defaults:1
+FL1:FL1:unknown:cascade-filter:1
+MX1:MX1:unknown:cascade-mixer:1
+T1:T1:unknown:cascade-transformer:1
AMP2:AMP2:unknown:cascade-amp:1
diff --git a/gnetlist/tests/common/outputs/bom2/multiequal-output.net b/gnetlist/tests/common/outputs/bom2/multiequal-output.net
index c2a4d43..96541cd 100644
--- a/gnetlist/tests/common/outputs/bom2/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/bom2/multiequal-output.net
@@ -1,4 +1,4 @@
refdes:refdes:value:device:qty
-R1:R1:20:RESISTOR:1
A1:A1:abotol=1e-11:options:1
+R1:R1:20:RESISTOR:1
V1:V1:DC 1V:VOLTAGE_SOURCE:1
diff --git a/gnetlist/tests/common/outputs/bom2/netattrib-output.net b/gnetlist/tests/common/outputs/bom2/netattrib-output.net
index f345f29..e6992a1 100644
--- a/gnetlist/tests/common/outputs/bom2/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/bom2/netattrib-output.net
@@ -1,5 +1,5 @@
refdes:refdes:value:device:qty
+U100:U100:unknown:7400:1
U200:U200:unknown:7404:1
U300:U300:unknown:7404:1
-U100:U100:unknown:7400:1
F1:F1:unknown:FUSE:1
diff --git a/gnetlist/tests/common/outputs/bom2/powersupply-output.net b/gnetlist/tests/common/outputs/bom2/powersupply-output.net
index fd66a08..4f339d5 100644
--- a/gnetlist/tests/common/outputs/bom2/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/bom2/powersupply-output.net
@@ -1,13 +1,13 @@
refdes:refdes:value:device:qty
U1:U1:unknown:DIODE-BRIDGE:1
-U2:U2:unknown:LM317:1
+F1:F1:unknown:FUSE:1
T1:T1:unknown:transformer:1
-C1:C1:2200uF:POLARIZED_CAPACITOR:1
+CONN1:CONN1:unknown:MAINS_CONNECTOR:1
S1:S1:unknown:SPST:1
+C1:C1:2200uF:POLARIZED_CAPACITOR:1
+R2:R2:220:RESISTOR:1
C2:C2:0.1uF:POLARIZED_CAPACITOR:1
-C3:C3:22uF:POLARIZED_CAPACITOR:1
R1:R1:5k:VARIABLE_RESISTOR:1
+C3:C3:22uF:POLARIZED_CAPACITOR:1
C4:C4:1uf:POLARIZED_CAPACITOR:1
-CONN1:CONN1:unknown:MAINS_CONNECTOR:1
-R2:R2:220:RESISTOR:1
-F1:F1:unknown:FUSE:1
+U2:U2:unknown:LM317:1
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net
index aa8646b..be254a9 100644
--- a/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net
@@ -1,4 +1,4 @@
Q2 Does not have attribute: value
A2 Does not have attribute: value
-Q1 Does not have attribute: value
A1 Does not have attribute: value
+Q1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net
index aa8646b..be254a9 100644
--- a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net
@@ -1,4 +1,4 @@
Q2 Does not have attribute: value
A2 Does not have attribute: value
-Q1 Does not have attribute: value
A1 Does not have attribute: value
+Q1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net
index aa8646b..be254a9 100644
--- a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net
@@ -1,4 +1,4 @@
Q2 Does not have attribute: value
A2 Does not have attribute: value
-Q1 Does not have attribute: value
A1 Does not have attribute: value
+Q1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/cascade-output.net b/gnetlist/tests/common/outputs/drc/cascade-output.net
index 8792376..88cb8c6 100644
--- a/gnetlist/tests/common/outputs/drc/cascade-output.net
+++ b/gnetlist/tests/common/outputs/drc/cascade-output.net
@@ -1,9 +1,9 @@
AMP2 Does not have attribute: value
+T1 Does not have attribute: value
+MX1 Does not have attribute: value
+FL1 Does not have attribute: value
+DEF1 Does not have attribute: value
AMP1 Does not have attribute: value
SOURCE Does not have attribute: value
DEFAULTS Does not have attribute: value
-MX1 Does not have attribute: value
-DEF1 Does not have attribute: value
-T1 Does not have attribute: value
-FL1 Does not have attribute: value
Net GND has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/netattrib-output.net b/gnetlist/tests/common/outputs/drc/netattrib-output.net
index db5b794..039c370 100644
--- a/gnetlist/tests/common/outputs/drc/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/drc/netattrib-output.net
@@ -1,5 +1,5 @@
F1 Does not have attribute: value
-U100 Does not have attribute: value
U300 Does not have attribute: value
U200 Does not have attribute: value
+U100 Does not have attribute: value
Net unnamed_net1 has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/powersupply-output.net b/gnetlist/tests/common/outputs/drc/powersupply-output.net
index f29bd92..5de58de 100644
--- a/gnetlist/tests/common/outputs/drc/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/drc/powersupply-output.net
@@ -1,7 +1,7 @@
-F1 Does not have attribute: value
-CONN1 Does not have attribute: value
+U2 Does not have attribute: value
S1 Does not have attribute: value
+CONN1 Does not have attribute: value
T1 Does not have attribute: value
-U2 Does not have attribute: value
+F1 Does not have attribute: value
U1 Does not have attribute: value
Net GND has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc2/netattrib-output.net b/gnetlist/tests/common/outputs/drc2/netattrib-output.net
index 7a4e5e0..37d0882 100644
--- a/gnetlist/tests/common/outputs/drc2/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/drc2/netattrib-output.net
@@ -22,9 +22,6 @@ Checking slots...
Checking duplicated slots...
Checking unused slots...
-WARNING: Unused slot 2 of uref U100
-WARNING: Unused slot 3 of uref U100
-WARNING: Unused slot 4 of uref U100
WARNING: Unused slot 2 of uref U300
WARNING: Unused slot 3 of uref U300
WARNING: Unused slot 4 of uref U300
@@ -35,6 +32,9 @@ WARNING: Unused slot 3 of uref U200
WARNING: Unused slot 4 of uref U200
WARNING: Unused slot 5 of uref U200
WARNING: Unused slot 6 of uref U200
+WARNING: Unused slot 2 of uref U100
+WARNING: Unused slot 3 of uref U100
+WARNING: Unused slot 4 of uref U100
Found 13 warnings.
Found 5 errors.
diff --git a/gnetlist/tests/common/outputs/eagle/JD-output.net b/gnetlist/tests/common/outputs/eagle/JD-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include-output.net b/gnetlist/tests/common/outputs/eagle/JD_Include-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net b/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net
index df919e4..47ef95e 100644
--- a/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net
@@ -1,26 +1,26 @@
;
-ADD 'V1' none@smd-ipc (1 1);
-VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
-ADD 'Cm' unknown@smd-ipc (1 1);
-VALUE 'Cm' '20p';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'Rt' unknown@smd-ipc (1 1);
-VALUE 'Rt' '1k';
-ADD 'M1' unknown@smd-ipc (1 1);
-VALUE 'M1' 'PMOS_TRANSISTOR';
-ADD 'X1' unknown@smd-ipc (1 1);
-VALUE 'X1' 'LVD';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
ADD 'Rlp' unknown@smd-ipc (1 1);
VALUE 'Rlp' '1meg';
-ADD 'Vdd' none@smd-ipc (1 1);
-VALUE 'Vdd' 'DC 3.3V';
ADD 'Rlm' unknown@smd-ipc (1 1);
VALUE 'Rlm' '500k';
-ADD 'Cp' unknown@smd-ipc (1 1);
-VALUE 'Cp' '20p';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
ADD 'Rb' unknown@smd-ipc (1 1);
VALUE 'Rb' '5.6k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
SIGNAL 'VDD1'
'Rlp' '2'
'M1' 'B'
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net
index e4a8277..25b583e 100644
--- a/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net
@@ -1,50 +1,50 @@
;
-ADD 'Cout' unknown@smd-ipc (1 1);
-VALUE 'Cout' '2.2uF';
-ADD 'R5' unknown@smd-ipc (1 1);
-VALUE 'R5' '10';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
ADD 'R4' unknown@smd-ipc (1 1);
VALUE 'R4' '2.8K';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
ADD 'RE2' unknown@smd-ipc (1 1);
VALUE 'RE2' '100';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
ADD 'Q2' unknown@smd-ipc (1 1);
VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
ADD 'A3' unknown@smd-ipc (1 1);
VALUE 'A3' '.options TEMP=25';
-ADD 'R3' unknown@smd-ipc (1 1);
-VALUE 'R3' '28K';
ADD 'A2' unknown@smd-ipc (1 1);
VALUE 'A2' 'include';
-ADD 'RE1' unknown@smd-ipc (1 1);
-VALUE 'RE1' '100';
-ADD 'Q1' unknown@smd-ipc (1 1);
-VALUE 'Q1' 'NPN_TRANSISTOR';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'R2' unknown@smd-ipc (1 1);
-VALUE 'R2' '2K';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
ADD 'Vinput' none@smd-ipc (1 1);
VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
-ADD 'R1' unknown@smd-ipc (1 1);
-VALUE 'R1' '28K';
-ADD 'C2' unknown@smd-ipc (1 1);
-VALUE 'C2' '2.2uF';
-ADD 'CE2' unknown@smd-ipc (1 1);
-VALUE 'CE2' '1pF';
-ADD 'C1' unknown@smd-ipc (1 1);
-VALUE 'C1' '2.2uF';
ADD 'CE1' unknown@smd-ipc (1 1);
VALUE 'CE1' '1pF';
-ADD 'R8' unknown@smd-ipc (1 1);
-VALUE 'R8' '1';
-ADD 'VCC' none@smd-ipc (1 1);
-VALUE 'VCC' 'DC 15V';
-ADD 'RC2' unknown@smd-ipc (1 1);
-VALUE 'RC2' '1K';
-ADD 'RC1' unknown@smd-ipc (1 1);
-VALUE 'RC1' '3.3K';
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
ADD 'RL' unknown@smd-ipc (1 1);
VALUE 'RL' '100K';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
SIGNAL 'UNNAMED_NET2'
'C2' '1'
'R8' '2'
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net
index e4a8277..25b583e 100644
--- a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net
@@ -1,50 +1,50 @@
;
-ADD 'Cout' unknown@smd-ipc (1 1);
-VALUE 'Cout' '2.2uF';
-ADD 'R5' unknown@smd-ipc (1 1);
-VALUE 'R5' '10';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
ADD 'R4' unknown@smd-ipc (1 1);
VALUE 'R4' '2.8K';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
ADD 'RE2' unknown@smd-ipc (1 1);
VALUE 'RE2' '100';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
ADD 'Q2' unknown@smd-ipc (1 1);
VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
ADD 'A3' unknown@smd-ipc (1 1);
VALUE 'A3' '.options TEMP=25';
-ADD 'R3' unknown@smd-ipc (1 1);
-VALUE 'R3' '28K';
ADD 'A2' unknown@smd-ipc (1 1);
VALUE 'A2' 'include';
-ADD 'RE1' unknown@smd-ipc (1 1);
-VALUE 'RE1' '100';
-ADD 'Q1' unknown@smd-ipc (1 1);
-VALUE 'Q1' 'NPN_TRANSISTOR';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'R2' unknown@smd-ipc (1 1);
-VALUE 'R2' '2K';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
ADD 'Vinput' none@smd-ipc (1 1);
VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
-ADD 'R1' unknown@smd-ipc (1 1);
-VALUE 'R1' '28K';
-ADD 'C2' unknown@smd-ipc (1 1);
-VALUE 'C2' '2.2uF';
-ADD 'CE2' unknown@smd-ipc (1 1);
-VALUE 'CE2' '1pF';
-ADD 'C1' unknown@smd-ipc (1 1);
-VALUE 'C1' '2.2uF';
ADD 'CE1' unknown@smd-ipc (1 1);
VALUE 'CE1' '1pF';
-ADD 'R8' unknown@smd-ipc (1 1);
-VALUE 'R8' '1';
-ADD 'VCC' none@smd-ipc (1 1);
-VALUE 'VCC' 'DC 15V';
-ADD 'RC2' unknown@smd-ipc (1 1);
-VALUE 'RC2' '1K';
-ADD 'RC1' unknown@smd-ipc (1 1);
-VALUE 'RC1' '3.3K';
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
ADD 'RL' unknown@smd-ipc (1 1);
VALUE 'RL' '100K';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
SIGNAL 'UNNAMED_NET2'
'C2' '1'
'R8' '2'
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net
index e4a8277..25b583e 100644
--- a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net
@@ -1,50 +1,50 @@
;
-ADD 'Cout' unknown@smd-ipc (1 1);
-VALUE 'Cout' '2.2uF';
-ADD 'R5' unknown@smd-ipc (1 1);
-VALUE 'R5' '10';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
ADD 'R4' unknown@smd-ipc (1 1);
VALUE 'R4' '2.8K';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
ADD 'RE2' unknown@smd-ipc (1 1);
VALUE 'RE2' '100';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
ADD 'Q2' unknown@smd-ipc (1 1);
VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
ADD 'A3' unknown@smd-ipc (1 1);
VALUE 'A3' '.options TEMP=25';
-ADD 'R3' unknown@smd-ipc (1 1);
-VALUE 'R3' '28K';
ADD 'A2' unknown@smd-ipc (1 1);
VALUE 'A2' 'include';
-ADD 'RE1' unknown@smd-ipc (1 1);
-VALUE 'RE1' '100';
-ADD 'Q1' unknown@smd-ipc (1 1);
-VALUE 'Q1' 'NPN_TRANSISTOR';
ADD 'A1' unknown@smd-ipc (1 1);
VALUE 'A1' 'model';
-ADD 'R2' unknown@smd-ipc (1 1);
-VALUE 'R2' '2K';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
ADD 'Vinput' none@smd-ipc (1 1);
VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
-ADD 'R1' unknown@smd-ipc (1 1);
-VALUE 'R1' '28K';
-ADD 'C2' unknown@smd-ipc (1 1);
-VALUE 'C2' '2.2uF';
-ADD 'CE2' unknown@smd-ipc (1 1);
-VALUE 'CE2' '1pF';
-ADD 'C1' unknown@smd-ipc (1 1);
-VALUE 'C1' '2.2uF';
ADD 'CE1' unknown@smd-ipc (1 1);
VALUE 'CE1' '1pF';
-ADD 'R8' unknown@smd-ipc (1 1);
-VALUE 'R8' '1';
-ADD 'VCC' none@smd-ipc (1 1);
-VALUE 'VCC' 'DC 15V';
-ADD 'RC2' unknown@smd-ipc (1 1);
-VALUE 'RC2' '1K';
-ADD 'RC1' unknown@smd-ipc (1 1);
-VALUE 'RC1' '3.3K';
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
ADD 'RL' unknown@smd-ipc (1 1);
VALUE 'RL' '100K';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
SIGNAL 'UNNAMED_NET2'
'C2' '1'
'R8' '2'
diff --git a/gnetlist/tests/common/outputs/eagle/cascade-output.net b/gnetlist/tests/common/outputs/eagle/cascade-output.net
index e94f679..b04f0cf 100644
--- a/gnetlist/tests/common/outputs/eagle/cascade-output.net
+++ b/gnetlist/tests/common/outputs/eagle/cascade-output.net
@@ -1,20 +1,20 @@
;
ADD 'AMP2' none@smd-ipc (1 1);
VALUE 'AMP2' 'cascade-amp';
+ADD 'T1' none@smd-ipc (1 1);
+VALUE 'T1' 'cascade-transformer';
+ADD 'MX1' none@smd-ipc (1 1);
+VALUE 'MX1' 'cascade-mixer';
+ADD 'FL1' none@smd-ipc (1 1);
+VALUE 'FL1' 'cascade-filter';
+ADD 'DEF1' none@smd-ipc (1 1);
+VALUE 'DEF1' 'cascade-defaults';
ADD 'AMP1' none@smd-ipc (1 1);
VALUE 'AMP1' 'cascade-amp';
ADD 'SOURCE' none@smd-ipc (1 1);
VALUE 'SOURCE' 'cascade-source';
ADD 'DEFAULTS' unknown@smd-ipc (1 1);
VALUE 'DEFAULTS' 'cascade-defaults-top';
-ADD 'MX1' none@smd-ipc (1 1);
-VALUE 'MX1' 'cascade-mixer';
-ADD 'DEF1' none@smd-ipc (1 1);
-VALUE 'DEF1' 'cascade-defaults';
-ADD 'T1' none@smd-ipc (1 1);
-VALUE 'T1' 'cascade-transformer';
-ADD 'FL1' none@smd-ipc (1 1);
-VALUE 'FL1' 'cascade-filter';
SIGNAL 'UNNAMED_NET6'
'AMP2' '1'
'T1' '2'
diff --git a/gnetlist/tests/common/outputs/eagle/multiequal-output.net b/gnetlist/tests/common/outputs/eagle/multiequal-output.net
index 978d0da..2a4cb86 100644
--- a/gnetlist/tests/common/outputs/eagle/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/eagle/multiequal-output.net
@@ -1,10 +1,10 @@
;
ADD 'V1' none@smd-ipc (1 1);
VALUE 'V1' 'DC 1V';
-ADD 'A1' unknown@smd-ipc (1 1);
-VALUE 'A1' 'abotol=1e-11';
ADD 'R1' unknown@smd-ipc (1 1);
VALUE 'R1' '20';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'abotol=1e-11';
SIGNAL 'GND'
'V1' '2'
'R1' '1'
diff --git a/gnetlist/tests/common/outputs/eagle/netattrib-output.net b/gnetlist/tests/common/outputs/eagle/netattrib-output.net
index 4ab78c3..806e948 100644
--- a/gnetlist/tests/common/outputs/eagle/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/eagle/netattrib-output.net
@@ -1,12 +1,12 @@
;
ADD 'F1' unknown@smd-ipc (1 1);
VALUE 'F1' 'FUSE';
-ADD 'U100' DIP14@smd-ipc (1 1);
-VALUE 'U100' '7400';
ADD 'U300' DIP14@smd-ipc (1 1);
VALUE 'U300' '7404';
ADD 'U200' DIP14@smd-ipc (1 1);
VALUE 'U200' '7404';
+ADD 'U100' DIP14@smd-ipc (1 1);
+VALUE 'U100' '7400';
SIGNAL 'UNNAMED_NET1'
'U300' '2'
;
diff --git a/gnetlist/tests/common/outputs/eagle/powersupply-output.net b/gnetlist/tests/common/outputs/eagle/powersupply-output.net
index 16e8ae8..b4167dc 100644
--- a/gnetlist/tests/common/outputs/eagle/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/eagle/powersupply-output.net
@@ -1,26 +1,26 @@
;
-ADD 'F1' unknown@smd-ipc (1 1);
-VALUE 'F1' 'FUSE';
-ADD 'R2' unknown@smd-ipc (1 1);
-VALUE 'R2' '220';
-ADD 'CONN1' unknown@smd-ipc (1 1);
-VALUE 'CONN1' 'MAINS_CONNECTOR';
+ADD 'U2' unknown@smd-ipc (1 1);
+VALUE 'U2' 'LM317';
ADD 'C4' unknown@smd-ipc (1 1);
VALUE 'C4' '1uf';
-ADD 'R1' unknown@smd-ipc (1 1);
-VALUE 'R1' '5k';
ADD 'C3' unknown@smd-ipc (1 1);
VALUE 'C3' '22uF';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '5k';
ADD 'C2' unknown@smd-ipc (1 1);
VALUE 'C2' '0.1uF';
-ADD 'S1' unknown@smd-ipc (1 1);
-VALUE 'S1' 'SPST';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '220';
ADD 'C1' unknown@smd-ipc (1 1);
VALUE 'C1' '2200uF';
+ADD 'S1' unknown@smd-ipc (1 1);
+VALUE 'S1' 'SPST';
+ADD 'CONN1' unknown@smd-ipc (1 1);
+VALUE 'CONN1' 'MAINS_CONNECTOR';
ADD 'T1' unknown@smd-ipc (1 1);
VALUE 'T1' 'transformer';
-ADD 'U2' unknown@smd-ipc (1 1);
-VALUE 'U2' 'LM317';
+ADD 'F1' unknown@smd-ipc (1 1);
+VALUE 'F1' 'FUSE';
ADD 'U1' unknown@smd-ipc (1 1);
VALUE 'U1' 'DIODE-BRIDGE';
SIGNAL 'TEN'
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD-output.net b/gnetlist/tests/common/outputs/futurenet2/JD-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net
index 10530f4..53284c4 100644
--- a/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net
@@ -1,11 +1,9 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,V1
-DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,I,1-1,5,23,1
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
)
(SYM,2
DATA,2,CM
@@ -15,18 +13,55 @@ PIN,,GND,1-1,5,23,2
PIN,,M,1-1,5,23,1
)
(SYM,3
-DATA,2,A1
-DATA,3,model
+DATA,2,CP
+DATA,3,20p
DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
)
(SYM,4
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,5
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,6
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,7
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,8
DATA,2,RT
DATA,3,1k
DATA,4,unknown
PIN,,P,1-1,5,23,1
PIN,,M,1-1,5,23,2
)
-(SYM,5
+(SYM,9
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+(SYM,10
DATA,2,M1
DATA,3,PMOS_TRANSISTOR
DATA,4,unknown
@@ -35,7 +70,7 @@ PIN,,LVH,1-1,5,23,D
PIN,,VDD1,1-1,5,23,B
PIN,,VDD1,1-1,5,23,S
)
-(SYM,6
+(SYM,11
DATA,2,X1
DATA,3,LVD
DATA,4,unknown
@@ -47,41 +82,6 @@ PIN,,I,1-1,5,23,1
PIN,,P,1-1,5,23,5
PIN,,M,1-1,5,23,4
)
-(SYM,7
-DATA,2,RLP
-DATA,3,1meg
-DATA,4,unknown
-PIN,,P,1-1,5,23,1
-PIN,,VDD1,1-1,5,23,2
-)
-(SYM,8
-DATA,2,VDD
-DATA,3,DC 3.3V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VDD1,1-1,5,23,1
-)
-(SYM,9
-DATA,2,RLM
-DATA,3,500k
-DATA,4,unknown
-PIN,,M,1-1,5,23,1
-PIN,,GND,1-1,5,23,2
-)
-(SYM,10
-DATA,2,CP
-DATA,3,20p
-DATA,4,unknown
-PIN,,GND,1-1,5,23,2
-PIN,,P,1-1,5,23,1
-)
-(SYM,11
-DATA,2,RB
-DATA,3,5.6k
-DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,LVH,1-1,5,23,2
-)
)
SIG,VDD1,1-1,5,VDD1
SIG,GND,1-1,5,GND
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net
index 8ed0786..1e8f865 100644
--- a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net
@@ -1,161 +1,161 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,COUT
+DATA,2,C2
DATA,3,2.2uF
DATA,4,unknown
-PIN,,VOUT,1-1,5,23,2
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
)
(SYM,2
-DATA,2,R5
-DATA,3,10
-DATA,4,unknown
-PIN,,VIN,1-1,5,23,1
-PIN,,NET1,1-1,5,23,2
-)
-(SYM,3
DATA,2,R4
DATA,3,2.8K
DATA,4,unknown
PIN,,GND,1-1,5,23,1
PIN,,VBASE2,1-1,5,23,2
)
+(SYM,3
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
(SYM,4
-DATA,2,RE2
-DATA,3,100
+DATA,2,R8
+DATA,3,1
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM2,1-1,5,23,2
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
)
(SYM,5
-DATA,2,Q2
-DATA,3,NPN_TRANSISTOR
+DATA,2,CE2
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,VEM2,1-1,5,23,1
-PIN,,VCOLL2,1-1,5,23,3
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,6
-DATA,2,A3
-DATA,3,.options TEMP=25
+DATA,2,RE2
+DATA,3,100
DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
)
(SYM,7
-DATA,2,R3
-DATA,3,28K
+DATA,2,RC1
+DATA,3,3.3K
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,8
-DATA,2,A2
-DATA,3,include
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
)
(SYM,9
-DATA,2,RE1
-DATA,3,100
+DATA,2,C1
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM1,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
)
(SYM,10
-DATA,2,Q1
-DATA,3,NPN_TRANSISTOR
+DATA,2,A3
+DATA,3,.options TEMP=25
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,VEM1,1-1,5,23,1
-PIN,,VCOLL1,1-1,5,23,3
)
(SYM,11
-DATA,2,A1
-DATA,3,model
+DATA,2,A2
+DATA,3,include
DATA,4,unknown
)
(SYM,12
-DATA,2,R2
-DATA,3,2K
+DATA,2,A1
+DATA,3,model
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VBASE1,1-1,5,23,2
)
(SYM,13
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,14
DATA,2,VINPUT
DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DATA,4,none
PIN,,GND,1-1,5,23,2
PIN,,VIN,1-1,5,23,1
)
-(SYM,14
-DATA,2,R1
-DATA,3,28K
-DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
-)
(SYM,15
-DATA,2,C2
-DATA,3,2.2uF
+DATA,2,CE1
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,NET2,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,16
-DATA,2,CE2
-DATA,3,1pF
+DATA,2,COUT
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,VEM2,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
)
(SYM,17
-DATA,2,C1
-DATA,3,2.2uF
+DATA,2,RL
+DATA,3,100K
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,NET1,1-1,5,23,1
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
)
(SYM,18
-DATA,2,CE1
-DATA,3,1pF
+DATA,2,RC2
+DATA,3,1K
DATA,4,unknown
-PIN,,VEM1,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
)
(SYM,19
-DATA,2,R8
-DATA,3,1
+DATA,2,RE1
+DATA,3,100
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,NET2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
)
(SYM,20
-DATA,2,VCC
-DATA,3,DC 15V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VCC,1-1,5,23,1
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
)
(SYM,21
-DATA,2,RC2
-DATA,3,1K
+DATA,2,R1
+DATA,3,28K
DATA,4,unknown
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,22
-DATA,2,RC1
-DATA,3,3.3K
+DATA,2,R5
+DATA,3,10
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
)
(SYM,23
-DATA,2,RL
-DATA,3,100K
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VOUT,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
)
)
SIG,NET2,1-1,5,NET2
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net
index 8ed0786..1e8f865 100644
--- a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net
@@ -1,161 +1,161 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,COUT
+DATA,2,C2
DATA,3,2.2uF
DATA,4,unknown
-PIN,,VOUT,1-1,5,23,2
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
)
(SYM,2
-DATA,2,R5
-DATA,3,10
-DATA,4,unknown
-PIN,,VIN,1-1,5,23,1
-PIN,,NET1,1-1,5,23,2
-)
-(SYM,3
DATA,2,R4
DATA,3,2.8K
DATA,4,unknown
PIN,,GND,1-1,5,23,1
PIN,,VBASE2,1-1,5,23,2
)
+(SYM,3
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
(SYM,4
-DATA,2,RE2
-DATA,3,100
+DATA,2,R8
+DATA,3,1
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM2,1-1,5,23,2
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
)
(SYM,5
-DATA,2,Q2
-DATA,3,NPN_TRANSISTOR
+DATA,2,CE2
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,VEM2,1-1,5,23,1
-PIN,,VCOLL2,1-1,5,23,3
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,6
-DATA,2,A3
-DATA,3,.options TEMP=25
+DATA,2,RE2
+DATA,3,100
DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
)
(SYM,7
-DATA,2,R3
-DATA,3,28K
+DATA,2,RC1
+DATA,3,3.3K
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,8
-DATA,2,A2
-DATA,3,include
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
)
(SYM,9
-DATA,2,RE1
-DATA,3,100
+DATA,2,C1
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM1,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
)
(SYM,10
-DATA,2,Q1
-DATA,3,NPN_TRANSISTOR
+DATA,2,A3
+DATA,3,.options TEMP=25
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,VEM1,1-1,5,23,1
-PIN,,VCOLL1,1-1,5,23,3
)
(SYM,11
-DATA,2,A1
-DATA,3,model
+DATA,2,A2
+DATA,3,include
DATA,4,unknown
)
(SYM,12
-DATA,2,R2
-DATA,3,2K
+DATA,2,A1
+DATA,3,model
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VBASE1,1-1,5,23,2
)
(SYM,13
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,14
DATA,2,VINPUT
DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DATA,4,none
PIN,,GND,1-1,5,23,2
PIN,,VIN,1-1,5,23,1
)
-(SYM,14
-DATA,2,R1
-DATA,3,28K
-DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
-)
(SYM,15
-DATA,2,C2
-DATA,3,2.2uF
+DATA,2,CE1
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,NET2,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,16
-DATA,2,CE2
-DATA,3,1pF
+DATA,2,COUT
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,VEM2,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
)
(SYM,17
-DATA,2,C1
-DATA,3,2.2uF
+DATA,2,RL
+DATA,3,100K
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,NET1,1-1,5,23,1
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
)
(SYM,18
-DATA,2,CE1
-DATA,3,1pF
+DATA,2,RC2
+DATA,3,1K
DATA,4,unknown
-PIN,,VEM1,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
)
(SYM,19
-DATA,2,R8
-DATA,3,1
+DATA,2,RE1
+DATA,3,100
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,NET2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
)
(SYM,20
-DATA,2,VCC
-DATA,3,DC 15V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VCC,1-1,5,23,1
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
)
(SYM,21
-DATA,2,RC2
-DATA,3,1K
+DATA,2,R1
+DATA,3,28K
DATA,4,unknown
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,22
-DATA,2,RC1
-DATA,3,3.3K
+DATA,2,R5
+DATA,3,10
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
)
(SYM,23
-DATA,2,RL
-DATA,3,100K
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VOUT,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
)
)
SIG,NET2,1-1,5,NET2
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net
index 8ed0786..1e8f865 100644
--- a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net
@@ -1,161 +1,161 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,COUT
+DATA,2,C2
DATA,3,2.2uF
DATA,4,unknown
-PIN,,VOUT,1-1,5,23,2
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
)
(SYM,2
-DATA,2,R5
-DATA,3,10
-DATA,4,unknown
-PIN,,VIN,1-1,5,23,1
-PIN,,NET1,1-1,5,23,2
-)
-(SYM,3
DATA,2,R4
DATA,3,2.8K
DATA,4,unknown
PIN,,GND,1-1,5,23,1
PIN,,VBASE2,1-1,5,23,2
)
+(SYM,3
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
(SYM,4
-DATA,2,RE2
-DATA,3,100
+DATA,2,R8
+DATA,3,1
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM2,1-1,5,23,2
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
)
(SYM,5
-DATA,2,Q2
-DATA,3,NPN_TRANSISTOR
+DATA,2,CE2
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,VEM2,1-1,5,23,1
-PIN,,VCOLL2,1-1,5,23,3
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,6
-DATA,2,A3
-DATA,3,.options TEMP=25
+DATA,2,RE2
+DATA,3,100
DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
)
(SYM,7
-DATA,2,R3
-DATA,3,28K
+DATA,2,RC1
+DATA,3,3.3K
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,8
-DATA,2,A2
-DATA,3,include
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
)
(SYM,9
-DATA,2,RE1
-DATA,3,100
+DATA,2,C1
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VEM1,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
)
(SYM,10
-DATA,2,Q1
-DATA,3,NPN_TRANSISTOR
+DATA,2,A3
+DATA,3,.options TEMP=25
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,VEM1,1-1,5,23,1
-PIN,,VCOLL1,1-1,5,23,3
)
(SYM,11
-DATA,2,A1
-DATA,3,model
+DATA,2,A2
+DATA,3,include
DATA,4,unknown
)
(SYM,12
-DATA,2,R2
-DATA,3,2K
+DATA,2,A1
+DATA,3,model
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VBASE1,1-1,5,23,2
)
(SYM,13
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,14
DATA,2,VINPUT
DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DATA,4,none
PIN,,GND,1-1,5,23,2
PIN,,VIN,1-1,5,23,1
)
-(SYM,14
-DATA,2,R1
-DATA,3,28K
-DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
-)
(SYM,15
-DATA,2,C2
-DATA,3,2.2uF
+DATA,2,CE1
+DATA,3,1pF
DATA,4,unknown
-PIN,,VBASE2,1-1,5,23,2
-PIN,,NET2,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
)
(SYM,16
-DATA,2,CE2
-DATA,3,1pF
+DATA,2,COUT
+DATA,3,2.2uF
DATA,4,unknown
-PIN,,VEM2,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
)
(SYM,17
-DATA,2,C1
-DATA,3,2.2uF
+DATA,2,RL
+DATA,3,100K
DATA,4,unknown
-PIN,,VBASE1,1-1,5,23,2
-PIN,,NET1,1-1,5,23,1
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
)
(SYM,18
-DATA,2,CE1
-DATA,3,1pF
+DATA,2,RC2
+DATA,3,1K
DATA,4,unknown
-PIN,,VEM1,1-1,5,23,2
-PIN,,GND,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
)
(SYM,19
-DATA,2,R8
-DATA,3,1
+DATA,2,RE1
+DATA,3,100
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,NET2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
)
(SYM,20
-DATA,2,VCC
-DATA,3,DC 15V
-DATA,4,none
-PIN,,GND,1-1,5,23,2
-PIN,,VCC,1-1,5,23,1
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
)
(SYM,21
-DATA,2,RC2
-DATA,3,1K
+DATA,2,R1
+DATA,3,28K
DATA,4,unknown
-PIN,,VCOLL2,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,1
PIN,,VCC,1-1,5,23,2
)
(SYM,22
-DATA,2,RC1
-DATA,3,3.3K
+DATA,2,R5
+DATA,3,10
DATA,4,unknown
-PIN,,VCOLL1,1-1,5,23,1
-PIN,,VCC,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
)
(SYM,23
-DATA,2,RL
-DATA,3,100K
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
DATA,4,unknown
-PIN,,GND,1-1,5,23,1
-PIN,,VOUT,1-1,5,23,2
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
)
)
SIG,NET2,1-1,5,NET2
diff --git a/gnetlist/tests/common/outputs/futurenet2/cascade-output.net b/gnetlist/tests/common/outputs/futurenet2/cascade-output.net
index 0dac53a..04030e1 100644
--- a/gnetlist/tests/common/outputs/futurenet2/cascade-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/cascade-output.net
@@ -8,51 +8,51 @@ PIN,,#f,1-1,5,23,2
PIN,,NET6,1-1,5,23,1
)
(SYM,2
-DATA,2,AMP1
-DATA,3,cascade-amp
+DATA,2,T1
+DATA,3,cascade-transformer
DATA,4,none
-PIN,,NET2,1-1,5,23,2
-PIN,,NET1,1-1,5,23,1
+PIN,,NET6,1-1,5,23,2
+PIN,,NET5,1-1,5,23,1
)
(SYM,3
-DATA,2,SOURCE
-DATA,3,cascade-source
-DATA,4,none
-PIN,,NET1,1-1,5,23,1
-)
-(SYM,4
-DATA,2,DEFAULTS
-DATA,3,cascade-defaults-top
-DATA,4,unknown
-PIN,,GND,1-1,5,23,unknown
-)
-(SYM,5
DATA,2,MX1
DATA,3,cascade-mixer
DATA,4,none
PIN,,NET5,1-1,5,23,2
PIN,,NET4,1-1,5,23,1
)
-(SYM,6
+(SYM,4
+DATA,2,FL1
+DATA,3,cascade-filter
+DATA,4,none
+PIN,,NET4,1-1,5,23,2
+PIN,,NET3,1-1,5,23,1
+)
+(SYM,5
DATA,2,DEF1
DATA,3,cascade-defaults
DATA,4,none
PIN,,NET3,1-1,5,23,2
PIN,,NET2,1-1,5,23,1
)
+(SYM,6
+DATA,2,AMP1
+DATA,3,cascade-amp
+DATA,4,none
+PIN,,NET2,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
(SYM,7
-DATA,2,T1
-DATA,3,cascade-transformer
+DATA,2,SOURCE
+DATA,3,cascade-source
DATA,4,none
-PIN,,NET6,1-1,5,23,2
-PIN,,NET5,1-1,5,23,1
+PIN,,NET1,1-1,5,23,1
)
(SYM,8
-DATA,2,FL1
-DATA,3,cascade-filter
-DATA,4,none
-PIN,,NET4,1-1,5,23,2
-PIN,,NET3,1-1,5,23,1
+DATA,2,DEFAULTS
+DATA,3,cascade-defaults-top
+DATA,4,unknown
+PIN,,GND,1-1,5,23,unknown
)
)
SIG,NET6,1-1,5,NET6
diff --git a/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net b/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net
index 6f5b71a..3e61295 100644
--- a/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net
@@ -8,17 +8,17 @@ PIN,,GND,1-1,5,23,2
PIN,,NET1,1-1,5,23,1
)
(SYM,2
-DATA,2,A1
-DATA,3,abotol=1e-11
-DATA,4,unknown
-)
-(SYM,3
DATA,2,R1
DATA,3,20
DATA,4,unknown
PIN,,GND,1-1,5,23,1
PIN,,NET1,1-1,5,23,2
)
+(SYM,3
+DATA,2,A1
+DATA,3,abotol=1e-11
+DATA,4,unknown
+)
)
SIG,GND,1-1,5,GND
SIG,NET1,1-1,5,NET1
diff --git a/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net b/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net
index 1cf6d8d..d01fbda 100644
--- a/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net
@@ -8,17 +8,6 @@ PIN,,#f,1-1,5,23,2
PIN,,ONE,1-1,5,23,1
)
(SYM,2
-DATA,2,U100
-DATA,3,7400
-DATA,4,DIP14
-PIN,,NETATTRI,1-1,5,23,unknown
-PIN,,GND,1-1,5,23,unknown
-PIN,,VCC,1-1,5,23,unknown
-PIN,,#f,1-1,5,23,1
-PIN,,#f,1-1,5,23,2
-PIN,,ONE,1-1,5,23,3
-)
-(SYM,3
DATA,2,U300
DATA,3,7404
DATA,4,DIP14
@@ -27,7 +16,7 @@ PIN,,GND,1-1,5,23,unknown
PIN,,NET1,1-1,5,23,2
PIN,,ONE,1-1,5,23,1
)
-(SYM,4
+(SYM,3
DATA,2,U200
DATA,3,7404
DATA,4,DIP14
@@ -36,6 +25,17 @@ PIN,,GND,1-1,5,23,unknown
PIN,,NETATTRI,1-1,5,23,2
PIN,,ONE,1-1,5,23,1
)
+(SYM,4
+DATA,2,U100
+DATA,3,7400
+DATA,4,DIP14
+PIN,,NETATTRI,1-1,5,23,unknown
+PIN,,GND,1-1,5,23,unknown
+PIN,,VCC,1-1,5,23,unknown
+PIN,,#f,1-1,5,23,1
+PIN,,#f,1-1,5,23,2
+PIN,,ONE,1-1,5,23,3
+)
)
SIG,NET1,1-1,5,NET1
SIG,NETATTRI,1-1,5,NETATTRI
diff --git a/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net b/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net
index d63b98c..d0afdbf 100644
--- a/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net
@@ -1,35 +1,28 @@
PINLIST,2
(DRAWING,GEDA.PIN,1-1
(SYM,1
-DATA,2,F1
-DATA,3,FUSE
-DATA,4,unknown
-PIN,,THREE,1-1,5,23,2
-PIN,,TWO,1-1,5,23,1
-)
-(SYM,2
-DATA,2,R2
-DATA,3,220
+DATA,2,U2
+DATA,3,LM317
DATA,4,unknown
PIN,,TEN,1-1,5,23,1
+PIN,,EIGHT,1-1,5,23,3
PIN,,ELEVEN,1-1,5,23,2
)
-(SYM,3
-DATA,2,CONN1
-DATA,3,MAINS_CONNECTOR
-DATA,4,unknown
-PIN,,GND,1-1,5,23,3
-PIN,,FIVE,1-1,5,23,2
-PIN,,ONE,1-1,5,23,1
-)
-(SYM,4
+(SYM,2
DATA,2,C4
DATA,3,1uf
DATA,4,unknown
PIN,,NINE,1-1,5,23,2
PIN,,ELEVEN,1-1,5,23,1
)
-(SYM,5
+(SYM,3
+DATA,2,C3
+DATA,3,22uF
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,2
+PIN,,TEN,1-1,5,23,1
+)
+(SYM,4
DATA,2,R1
DATA,3,5k
DATA,4,unknown
@@ -37,16 +30,23 @@ PIN,,NINE,1-1,5,23,1
PIN,,TEN,1-1,5,23,2
PIN,,NINE,1-1,5,23,3
)
-(SYM,6
-DATA,2,C3
-DATA,3,22uF
+(SYM,5
+DATA,2,C2
+DATA,3,0.1uF
DATA,4,unknown
PIN,,NINE,1-1,5,23,2
+PIN,,EIGHT,1-1,5,23,1
+)
+(SYM,6
+DATA,2,R2
+DATA,3,220
+DATA,4,unknown
PIN,,TEN,1-1,5,23,1
+PIN,,ELEVEN,1-1,5,23,2
)
(SYM,7
-DATA,2,C2
-DATA,3,0.1uF
+DATA,2,C1
+DATA,3,2200uF
DATA,4,unknown
PIN,,NINE,1-1,5,23,2
PIN,,EIGHT,1-1,5,23,1
@@ -59,11 +59,12 @@ PIN,,ONE,1-1,5,23,1
PIN,,TWO,1-1,5,23,2
)
(SYM,9
-DATA,2,C1
-DATA,3,2200uF
+DATA,2,CONN1
+DATA,3,MAINS_CONNECTOR
DATA,4,unknown
-PIN,,NINE,1-1,5,23,2
-PIN,,EIGHT,1-1,5,23,1
+PIN,,GND,1-1,5,23,3
+PIN,,FIVE,1-1,5,23,2
+PIN,,ONE,1-1,5,23,1
)
(SYM,10
DATA,2,T1
@@ -75,12 +76,11 @@ PIN,,THREE,1-1,5,23,1
PIN,,FIVE,1-1,5,23,2
)
(SYM,11
-DATA,2,U2
-DATA,3,LM317
+DATA,2,F1
+DATA,3,FUSE
DATA,4,unknown
-PIN,,TEN,1-1,5,23,1
-PIN,,EIGHT,1-1,5,23,3
-PIN,,ELEVEN,1-1,5,23,2
+PIN,,THREE,1-1,5,23,2
+PIN,,TWO,1-1,5,23,1
)
(SYM,12
DATA,2,U1
diff --git a/gnetlist/tests/common/outputs/geda/JD-output.net b/gnetlist/tests/common/outputs/geda/JD-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include-output.net b/gnetlist/tests/common/outputs/geda/JD_Include-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD_Include-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort-output.net b/gnetlist/tests/common/outputs/geda/JD_Sort-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net
index b885bfb..15863e0 100644
--- a/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net
@@ -7,17 +7,17 @@ END header
START components
-V1 device=vpulse
-Cm device=CAPACITOR
A1 device=model
-Rt device=RESISTOR
-M1 device=PMOS_TRANSISTOR
-X1 device=LVD
+Cm device=CAPACITOR
+Cp device=CAPACITOR
Rlp device=RESISTOR
-Vdd device=VOLTAGE_SOURCE
Rlm device=RESISTOR
-Cp device=CAPACITOR
+Vdd device=VOLTAGE_SOURCE
+V1 device=vpulse
+Rt device=RESISTOR
Rb device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
END components
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net
index c595660..8ad8b09 100644
--- a/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net
@@ -7,29 +7,29 @@ END header
START components
-Cout device=CAPACITOR
-R5 device=RESISTOR
+C2 device=CAPACITOR
R4 device=RESISTOR
+R3 device=RESISTOR
+R8 device=RESISTOR
+CE2 device=CAPACITOR
RE2 device=RESISTOR
+RC1 device=RESISTOR
Q2 device=NPN_TRANSISTOR
+C1 device=CAPACITOR
A3 device=directive
-R3 device=RESISTOR
A2 device=include
-RE1 device=RESISTOR
-Q1 device=NPN_TRANSISTOR
A1 device=model
-R2 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
Vinput device=vsin
-R1 device=RESISTOR
-C2 device=CAPACITOR
-CE2 device=CAPACITOR
-C1 device=CAPACITOR
CE1 device=CAPACITOR
-R8 device=RESISTOR
-VCC device=VOLTAGE_SOURCE
-RC2 device=RESISTOR
-RC1 device=RESISTOR
+Cout device=CAPACITOR
RL device=RESISTOR
+RC2 device=RESISTOR
+RE1 device=RESISTOR
+R2 device=RESISTOR
+R1 device=RESISTOR
+R5 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
END components
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net
index c595660..8ad8b09 100644
--- a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net
@@ -7,29 +7,29 @@ END header
START components
-Cout device=CAPACITOR
-R5 device=RESISTOR
+C2 device=CAPACITOR
R4 device=RESISTOR
+R3 device=RESISTOR
+R8 device=RESISTOR
+CE2 device=CAPACITOR
RE2 device=RESISTOR
+RC1 device=RESISTOR
Q2 device=NPN_TRANSISTOR
+C1 device=CAPACITOR
A3 device=directive
-R3 device=RESISTOR
A2 device=include
-RE1 device=RESISTOR
-Q1 device=NPN_TRANSISTOR
A1 device=model
-R2 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
Vinput device=vsin
-R1 device=RESISTOR
-C2 device=CAPACITOR
-CE2 device=CAPACITOR
-C1 device=CAPACITOR
CE1 device=CAPACITOR
-R8 device=RESISTOR
-VCC device=VOLTAGE_SOURCE
-RC2 device=RESISTOR
-RC1 device=RESISTOR
+Cout device=CAPACITOR
RL device=RESISTOR
+RC2 device=RESISTOR
+RE1 device=RESISTOR
+R2 device=RESISTOR
+R1 device=RESISTOR
+R5 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
END components
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net
index c595660..8ad8b09 100644
--- a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net
@@ -7,29 +7,29 @@ END header
START components
-Cout device=CAPACITOR
-R5 device=RESISTOR
+C2 device=CAPACITOR
R4 device=RESISTOR
+R3 device=RESISTOR
+R8 device=RESISTOR
+CE2 device=CAPACITOR
RE2 device=RESISTOR
+RC1 device=RESISTOR
Q2 device=NPN_TRANSISTOR
+C1 device=CAPACITOR
A3 device=directive
-R3 device=RESISTOR
A2 device=include
-RE1 device=RESISTOR
-Q1 device=NPN_TRANSISTOR
A1 device=model
-R2 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
Vinput device=vsin
-R1 device=RESISTOR
-C2 device=CAPACITOR
-CE2 device=CAPACITOR
-C1 device=CAPACITOR
CE1 device=CAPACITOR
-R8 device=RESISTOR
-VCC device=VOLTAGE_SOURCE
-RC2 device=RESISTOR
-RC1 device=RESISTOR
+Cout device=CAPACITOR
RL device=RESISTOR
+RC2 device=RESISTOR
+RE1 device=RESISTOR
+R2 device=RESISTOR
+R1 device=RESISTOR
+R5 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
END components
diff --git a/gnetlist/tests/common/outputs/geda/cascade-output.net b/gnetlist/tests/common/outputs/geda/cascade-output.net
index f868cb3..0be75e6 100644
--- a/gnetlist/tests/common/outputs/geda/cascade-output.net
+++ b/gnetlist/tests/common/outputs/geda/cascade-output.net
@@ -8,13 +8,13 @@ END header
START components
AMP2 device=cascade-amp
+T1 device=cascade-transformer
+MX1 device=cascade-mixer
+FL1 device=cascade-filter
+DEF1 device=cascade-defaults
AMP1 device=cascade-amp
SOURCE device=cascade-source
DEFAULTS device=cascade-defaults-top
-MX1 device=cascade-mixer
-DEF1 device=cascade-defaults
-T1 device=cascade-transformer
-FL1 device=cascade-filter
END components
diff --git a/gnetlist/tests/common/outputs/geda/multiequal-output.net b/gnetlist/tests/common/outputs/geda/multiequal-output.net
index a723140..16b00e8 100644
--- a/gnetlist/tests/common/outputs/geda/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/geda/multiequal-output.net
@@ -8,8 +8,8 @@ END header
START components
V1 device=VOLTAGE_SOURCE
-A1 device=options
R1 device=RESISTOR
+A1 device=options
END components
diff --git a/gnetlist/tests/common/outputs/geda/netattrib-output.net b/gnetlist/tests/common/outputs/geda/netattrib-output.net
index 684efb0..5910ebd 100644
--- a/gnetlist/tests/common/outputs/geda/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/geda/netattrib-output.net
@@ -8,9 +8,9 @@ END header
START components
F1 device=FUSE
-U100 device=7400
U300 device=7404
U200 device=7404
+U100 device=7400
END components
diff --git a/gnetlist/tests/common/outputs/geda/powersupply-output.net b/gnetlist/tests/common/outputs/geda/powersupply-output.net
index 3471ddb..b4bc97c 100644
--- a/gnetlist/tests/common/outputs/geda/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/geda/powersupply-output.net
@@ -7,17 +7,17 @@ END header
START components
-F1 device=FUSE
-R2 device=RESISTOR
-CONN1 device=MAINS_CONNECTOR
+U2 device=LM317
C4 device=POLARIZED_CAPACITOR
-R1 device=VARIABLE_RESISTOR
C3 device=POLARIZED_CAPACITOR
+R1 device=VARIABLE_RESISTOR
C2 device=POLARIZED_CAPACITOR
-S1 device=SPST
+R2 device=RESISTOR
C1 device=POLARIZED_CAPACITOR
+S1 device=SPST
+CONN1 device=MAINS_CONNECTOR
T1 device=transformer
-U2 device=LM317
+F1 device=FUSE
U1 device=DIODE-BRIDGE
END components
diff --git a/gnetlist/tests/common/outputs/gossip/JD-output.net b/gnetlist/tests/common/outputs/gossip/JD-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include-output.net b/gnetlist/tests/common/outputs/gossip/JD_Include-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net b/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net
index 3417249..ee04f41 100644
--- a/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net
@@ -6,14 +6,14 @@
(use-library unknown *)
(define-block (not found (
(signals (Vdd1 GND LVH i p m))
- (V1)
- (Cm)
(A1)
- (Rt)
- (M1)
- (X1)
+ (Cm)
+ (Cp)
(Rlp)
- (Vdd)
(Rlm)
- (Cp)
+ (Vdd)
+ (V1)
+ (Rt)
(Rb)
+ (M1)
+ (X1)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net
index e75132d..7f0bcf4 100644
--- a/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net
@@ -6,26 +6,26 @@
(use-library unknown *)
(define-block (not found (
(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
- (Cout)
- (R5)
+ (C2)
(R4)
+ (R3)
+ (R8)
+ (CE2)
(RE2)
+ (RC1)
(Q2)
+ (C1)
(A3)
- (R3)
(A2)
- (RE1)
- (Q1)
(A1)
- (R2)
+ (VCC)
(Vinput)
- (R1)
- (C2)
- (CE2)
- (C1)
(CE1)
- (R8)
- (VCC)
- (RC2)
- (RC1)
+ (Cout)
(RL)
+ (RC2)
+ (RE1)
+ (R2)
+ (R1)
+ (R5)
+ (Q1)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net
index e75132d..7f0bcf4 100644
--- a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net
@@ -6,26 +6,26 @@
(use-library unknown *)
(define-block (not found (
(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
- (Cout)
- (R5)
+ (C2)
(R4)
+ (R3)
+ (R8)
+ (CE2)
(RE2)
+ (RC1)
(Q2)
+ (C1)
(A3)
- (R3)
(A2)
- (RE1)
- (Q1)
(A1)
- (R2)
+ (VCC)
(Vinput)
- (R1)
- (C2)
- (CE2)
- (C1)
(CE1)
- (R8)
- (VCC)
- (RC2)
- (RC1)
+ (Cout)
(RL)
+ (RC2)
+ (RE1)
+ (R2)
+ (R1)
+ (R5)
+ (Q1)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net
index e75132d..7f0bcf4 100644
--- a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net
@@ -6,26 +6,26 @@
(use-library unknown *)
(define-block (not found (
(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
- (Cout)
- (R5)
+ (C2)
(R4)
+ (R3)
+ (R8)
+ (CE2)
(RE2)
+ (RC1)
(Q2)
+ (C1)
(A3)
- (R3)
(A2)
- (RE1)
- (Q1)
(A1)
- (R2)
+ (VCC)
(Vinput)
- (R1)
- (C2)
- (CE2)
- (C1)
(CE1)
- (R8)
- (VCC)
- (RC2)
- (RC1)
+ (Cout)
(RL)
+ (RC2)
+ (RE1)
+ (R2)
+ (R1)
+ (R5)
+ (Q1)
diff --git a/gnetlist/tests/common/outputs/gossip/cascade-output.net b/gnetlist/tests/common/outputs/gossip/cascade-output.net
index 66837c8..5a2175a 100644
--- a/gnetlist/tests/common/outputs/gossip/cascade-output.net
+++ b/gnetlist/tests/common/outputs/gossip/cascade-output.net
@@ -7,10 +7,10 @@
(define-block (not found (
(signals (unnamed_net6 unnamed_net5 unnamed_net4 unnamed_net3 unnamed_net2 unnamed_net1 GND))
(AMP2)
+ (T1)
+ (MX1)
+ (FL1)
+ (DEF1)
(AMP1)
(SOURCE)
(DEFAULTS)
- (MX1)
- (DEF1)
- (T1)
- (FL1)
diff --git a/gnetlist/tests/common/outputs/gossip/multiequal-output.net b/gnetlist/tests/common/outputs/gossip/multiequal-output.net
index d40c383..70d6ef9 100644
--- a/gnetlist/tests/common/outputs/gossip/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/gossip/multiequal-output.net
@@ -7,5 +7,5 @@
(define-block (not found (
(signals (GND unnamed_net1))
(V1)
- (A1)
(R1)
+ (A1)
diff --git a/gnetlist/tests/common/outputs/gossip/netattrib-output.net b/gnetlist/tests/common/outputs/gossip/netattrib-output.net
index 6ab10f4..d8d4eb8 100644
--- a/gnetlist/tests/common/outputs/gossip/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/gossip/netattrib-output.net
@@ -7,6 +7,6 @@
(define-block (not found (
(signals (unnamed_net1 netattrib GND Vcc one))
(F1)
- (U100)
(U300)
(U200)
+ (U100)
diff --git a/gnetlist/tests/common/outputs/gossip/powersupply-output.net b/gnetlist/tests/common/outputs/gossip/powersupply-output.net
index 4398267..e5d15cb 100644
--- a/gnetlist/tests/common/outputs/gossip/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/gossip/powersupply-output.net
@@ -6,15 +6,15 @@
(use-library unknown *)
(define-block (not found (
(signals (ten eleven GND one five three two six seven nine eight))
- (F1)
- (R2)
- (CONN1)
+ (U2)
(C4)
- (R1)
(C3)
+ (R1)
(C2)
- (S1)
+ (R2)
(C1)
+ (S1)
+ (CONN1)
(T1)
- (U2)
+ (F1)
(U1)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
index 825885f..9c073e0 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
-PKG_unknown(unknown,Cm,20p)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,Rt,1k)
-PKG_unknown(unknown,M1,unknown)
-PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,Cp,20p)
PKG_unknown(unknown,Rlp,1meg)
-PKG_none(none,Vdd,DC 3.3V)
PKG_unknown(unknown,Rlm,500k)
-PKG_unknown(unknown,Cp,20p)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Rt,1k)
PKG_unknown(unknown,Rb,5.6k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
index b7db44a..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
@@ -10,29 +10,29 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_unknown(unknown,Cout,2.2uF)
-PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,A3,.options TEMP=25)
-PKG_unknown(unknown,R3,28K)
PKG_unknown(unknown,A2,unknown)
-PKG_unknown(unknown,RE1,100)
-PKG_unknown(unknown,Q1,unknown)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,R2,2K)
+PKG_none(none,VCC,DC 15V)
PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
-PKG_unknown(unknown,R1,28K)
-PKG_unknown(unknown,C2,2.2uF)
-PKG_unknown(unknown,CE2,1pF)
-PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,CE1,1pF)
-PKG_unknown(unknown,R8,1)
-PKG_none(none,VCC,DC 15V)
-PKG_unknown(unknown,RC2,1K)
-PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Cout,2.2uF)
PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
index b7db44a..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
@@ -10,29 +10,29 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_unknown(unknown,Cout,2.2uF)
-PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,A3,.options TEMP=25)
-PKG_unknown(unknown,R3,28K)
PKG_unknown(unknown,A2,unknown)
-PKG_unknown(unknown,RE1,100)
-PKG_unknown(unknown,Q1,unknown)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,R2,2K)
+PKG_none(none,VCC,DC 15V)
PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
-PKG_unknown(unknown,R1,28K)
-PKG_unknown(unknown,C2,2.2uF)
-PKG_unknown(unknown,CE2,1pF)
-PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,CE1,1pF)
-PKG_unknown(unknown,R8,1)
-PKG_none(none,VCC,DC 15V)
-PKG_unknown(unknown,RC2,1K)
-PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Cout,2.2uF)
PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
index b7db44a..94f9896 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
@@ -10,29 +10,29 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_unknown(unknown,Cout,2.2uF)
-PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,C2,2.2uF)
PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,R8,1)
+PKG_unknown(unknown,CE2,1pF)
PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,RC1,3.3K)
PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,A3,.options TEMP=25)
-PKG_unknown(unknown,R3,28K)
PKG_unknown(unknown,A2,unknown)
-PKG_unknown(unknown,RE1,100)
-PKG_unknown(unknown,Q1,unknown)
PKG_unknown(unknown,A1,unknown)
-PKG_unknown(unknown,R2,2K)
+PKG_none(none,VCC,DC 15V)
PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
-PKG_unknown(unknown,R1,28K)
-PKG_unknown(unknown,C2,2.2uF)
-PKG_unknown(unknown,CE2,1pF)
-PKG_unknown(unknown,C1,2.2uF)
PKG_unknown(unknown,CE1,1pF)
-PKG_unknown(unknown,R8,1)
-PKG_none(none,VCC,DC 15V)
-PKG_unknown(unknown,RC2,1K)
-PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,Cout,2.2uF)
PKG_unknown(unknown,RL,100K)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,R2,2K)
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,Q1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
index 0e39df7..3f5c511 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
@@ -11,13 +11,13 @@ Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_none(none,AMP2,unknown)
+PKG_none(none,T1,unknown)
+PKG_none(none,MX1,unknown)
+PKG_none(none,FL1,unknown)
+PKG_none(none,DEF1,unknown)
PKG_none(none,AMP1,unknown)
PKG_none(none,SOURCE,unknown)
PKG_unknown(unknown,DEFAULTS,unknown)
-PKG_none(none,MX1,unknown)
-PKG_none(none,DEF1,unknown)
-PKG_none(none,T1,unknown)
-PKG_none(none,FL1,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
index 497a18d..2bdf919 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
@@ -11,8 +11,8 @@ Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_none(none,V1,DC 1V)
-PKG_unknown(unknown,A1,abotol=1e-11)
PKG_unknown(unknown,R1,20)
+PKG_unknown(unknown,A1,abotol=1e-11)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
index a30399d..c40fb5b 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
@@ -11,9 +11,9 @@ Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
PKG_unknown(unknown,F1,unknown)
-PKG_DIP14(DIP14,U100,unknown)
PKG_DIP14(DIP14,U300,unknown)
PKG_DIP14(DIP14,U200,unknown)
+PKG_DIP14(DIP14,U100,unknown)
Layer(1 "component")
(
)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
index 42cffb4..3804abe 100644
--- a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
@@ -10,17 +10,17 @@ DRC[1000 1000 1000 1000 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
-PKG_unknown(unknown,F1,unknown)
-PKG_unknown(unknown,R2,220)
-PKG_unknown(unknown,CONN1,unknown)
+PKG_unknown(unknown,U2,unknown)
PKG_unknown(unknown,C4,1uf)
-PKG_unknown(unknown,R1,5k)
PKG_unknown(unknown,C3,22uF)
+PKG_unknown(unknown,R1,5k)
PKG_unknown(unknown,C2,0.1uF)
-PKG_unknown(unknown,S1,unknown)
+PKG_unknown(unknown,R2,220)
PKG_unknown(unknown,C1,2200uF)
+PKG_unknown(unknown,S1,unknown)
+PKG_unknown(unknown,CONN1,unknown)
PKG_unknown(unknown,T1,unknown)
-PKG_unknown(unknown,U2,unknown)
+PKG_unknown(unknown,F1,unknown)
PKG_unknown(unknown,U1,unknown)
Layer(1 "component")
(
diff --git a/gnetlist/tests/common/outputs/mathematica/JD-output.net b/gnetlist/tests/common/outputs/mathematica/JD-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net
index 1b203f4..b9a9d07 100644
--- a/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net
@@ -32,17 +32,17 @@ i["V1","1"]+i["X1","1"]==0,
i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
modelEquations={
-vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
-capacitor[value->20p]["Cm"],
model[value->a1]["A1"],
-resistor[value->1k]["Rt"],
-pmos_transistor[value->m1]["M1"],
-lvd[value->x1]["X1"],
+capacitor[value->20p]["Cm"],
+capacitor[value->20p]["Cp"],
resistor[value->1meg]["Rlp"],
-voltage_source[value->DC 3.3V]["Vdd"],
resistor[value->500k]["Rlm"],
-capacitor[value->20p]["Cp"],
-resistor[value->5.6k]["Rb"]};
+voltage_source[value->DC 3.3V]["Vdd"],
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+resistor[value->1k]["Rt"],
+resistor[value->5.6k]["Rb"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"]};
variables={
v["Vdd1"],
v["LVH"],
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net
index b6e4434..866d8fe 100644
--- a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net
@@ -53,29 +53,29 @@ i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
modelEquations={
-capacitor[value->2.2uF]["Cout"],
-resistor[value->10]["R5"],
+capacitor[value->2.2uF]["C2"],
resistor[value->2.8K]["R4"],
+resistor[value->28K]["R3"],
+resistor[value->1]["R8"],
+capacitor[value->1pF]["CE2"],
resistor[value->100]["RE2"],
+resistor[value->3.3K]["RC1"],
npn_transistor[value->q2]["Q2"],
+capacitor[value->2.2uF]["C1"],
directive[value->.options TEMP=25]["A3"],
-resistor[value->28K]["R3"],
include[value->a2]["A2"],
-resistor[value->100]["RE1"],
-npn_transistor[value->q1]["Q1"],
model[value->a1]["A1"],
-resistor[value->2K]["R2"],
+voltage_source[value->DC 15V]["VCC"],
vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
-resistor[value->28K]["R1"],
-capacitor[value->2.2uF]["C2"],
-capacitor[value->1pF]["CE2"],
-capacitor[value->2.2uF]["C1"],
capacitor[value->1pF]["CE1"],
-resistor[value->1]["R8"],
-voltage_source[value->DC 15V]["VCC"],
+capacitor[value->2.2uF]["Cout"],
+resistor[value->100K]["RL"],
resistor[value->1K]["RC2"],
-resistor[value->3.3K]["RC1"],
-resistor[value->100K]["RL"]};
+resistor[value->100]["RE1"],
+resistor[value->2K]["R2"],
+resistor[value->28K]["R1"],
+resistor[value->10]["R5"],
+npn_transistor[value->q1]["Q1"]};
variables={
v["unnamed_net2"],
v["Vbase2"],
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net
index b6e4434..866d8fe 100644
--- a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net
@@ -53,29 +53,29 @@ i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
modelEquations={
-capacitor[value->2.2uF]["Cout"],
-resistor[value->10]["R5"],
+capacitor[value->2.2uF]["C2"],
resistor[value->2.8K]["R4"],
+resistor[value->28K]["R3"],
+resistor[value->1]["R8"],
+capacitor[value->1pF]["CE2"],
resistor[value->100]["RE2"],
+resistor[value->3.3K]["RC1"],
npn_transistor[value->q2]["Q2"],
+capacitor[value->2.2uF]["C1"],
directive[value->.options TEMP=25]["A3"],
-resistor[value->28K]["R3"],
include[value->a2]["A2"],
-resistor[value->100]["RE1"],
-npn_transistor[value->q1]["Q1"],
model[value->a1]["A1"],
-resistor[value->2K]["R2"],
+voltage_source[value->DC 15V]["VCC"],
vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
-resistor[value->28K]["R1"],
-capacitor[value->2.2uF]["C2"],
-capacitor[value->1pF]["CE2"],
-capacitor[value->2.2uF]["C1"],
capacitor[value->1pF]["CE1"],
-resistor[value->1]["R8"],
-voltage_source[value->DC 15V]["VCC"],
+capacitor[value->2.2uF]["Cout"],
+resistor[value->100K]["RL"],
resistor[value->1K]["RC2"],
-resistor[value->3.3K]["RC1"],
-resistor[value->100K]["RL"]};
+resistor[value->100]["RE1"],
+resistor[value->2K]["R2"],
+resistor[value->28K]["R1"],
+resistor[value->10]["R5"],
+npn_transistor[value->q1]["Q1"]};
variables={
v["unnamed_net2"],
v["Vbase2"],
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net
index b6e4434..866d8fe 100644
--- a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net
@@ -53,29 +53,29 @@ i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
modelEquations={
-capacitor[value->2.2uF]["Cout"],
-resistor[value->10]["R5"],
+capacitor[value->2.2uF]["C2"],
resistor[value->2.8K]["R4"],
+resistor[value->28K]["R3"],
+resistor[value->1]["R8"],
+capacitor[value->1pF]["CE2"],
resistor[value->100]["RE2"],
+resistor[value->3.3K]["RC1"],
npn_transistor[value->q2]["Q2"],
+capacitor[value->2.2uF]["C1"],
directive[value->.options TEMP=25]["A3"],
-resistor[value->28K]["R3"],
include[value->a2]["A2"],
-resistor[value->100]["RE1"],
-npn_transistor[value->q1]["Q1"],
model[value->a1]["A1"],
-resistor[value->2K]["R2"],
+voltage_source[value->DC 15V]["VCC"],
vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
-resistor[value->28K]["R1"],
-capacitor[value->2.2uF]["C2"],
-capacitor[value->1pF]["CE2"],
-capacitor[value->2.2uF]["C1"],
capacitor[value->1pF]["CE1"],
-resistor[value->1]["R8"],
-voltage_source[value->DC 15V]["VCC"],
+capacitor[value->2.2uF]["Cout"],
+resistor[value->100K]["RL"],
resistor[value->1K]["RC2"],
-resistor[value->3.3K]["RC1"],
-resistor[value->100K]["RL"]};
+resistor[value->100]["RE1"],
+resistor[value->2K]["R2"],
+resistor[value->28K]["R1"],
+resistor[value->10]["R5"],
+npn_transistor[value->q1]["Q1"]};
variables={
v["unnamed_net2"],
v["Vbase2"],
diff --git a/gnetlist/tests/common/outputs/mathematica/cascade-output.net b/gnetlist/tests/common/outputs/mathematica/cascade-output.net
index c154417..98fae8c 100644
--- a/gnetlist/tests/common/outputs/mathematica/cascade-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/cascade-output.net
@@ -20,13 +20,13 @@ i["DEF1","1"]+i["AMP1","2"]==0,
i["AMP1","1"]+i["SOURCE","1"]==0};
modelEquations={
cascade-amp[value->amp2]["AMP2"],
-cascade-amp[value->amp1]["AMP1"],
-cascade-source[value->source]["SOURCE"],
-cascade-defaults-top[value->defaults]["DEFAULTS"],
+cascade-transformer[value->t1]["T1"],
cascade-mixer[value->mx1]["MX1"],
+cascade-filter[value->fl1]["FL1"],
cascade-defaults[value->def1]["DEF1"],
-cascade-transformer[value->t1]["T1"],
-cascade-filter[value->fl1]["FL1"]};
+cascade-amp[value->amp1]["AMP1"],
+cascade-source[value->source]["SOURCE"],
+cascade-defaults-top[value->defaults]["DEFAULTS"]};
variables={
v["unnamed_net6"],
v["unnamed_net5"],
diff --git a/gnetlist/tests/common/outputs/mathematica/multiequal-output.net b/gnetlist/tests/common/outputs/mathematica/multiequal-output.net
index bc10b94..ffb9374 100644
--- a/gnetlist/tests/common/outputs/mathematica/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/multiequal-output.net
@@ -6,8 +6,8 @@ nodeEquations={
i["V1","1"]+i["R1","2"]==0};
modelEquations={
voltage_source[value->DC 1V]["V1"],
-options[value->abotol=1e-11]["A1"],
-resistor[value->20]["R1"]};
+resistor[value->20]["R1"],
+options[value->abotol=1e-11]["A1"]};
variables={
v["unnamed_net1"],
i["V1","2"],
diff --git a/gnetlist/tests/common/outputs/mathematica/netattrib-output.net b/gnetlist/tests/common/outputs/mathematica/netattrib-output.net
index d83c0b1..ba8beaf 100644
--- a/gnetlist/tests/common/outputs/mathematica/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/netattrib-output.net
@@ -18,9 +18,9 @@ i["U300","14"]+i["U200","14"]+i["U100","14"]==0,
i["F1","1"]+i["U300","1"]+i["U200","1"]+i["U100","3"]==0};
modelEquations={
fuse[value->f1]["F1"],
-7400[value->u100]["U100"],
7404[value->u300]["U300"],
-7404[value->u200]["U200"]};
+7404[value->u200]["U200"],
+7400[value->u100]["U100"]};
variables={
v["unnamed_net1"],
v["netattrib"],
diff --git a/gnetlist/tests/common/outputs/mathematica/powersupply-output.net b/gnetlist/tests/common/outputs/mathematica/powersupply-output.net
index ae09c90..36634a5 100644
--- a/gnetlist/tests/common/outputs/mathematica/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/mathematica/powersupply-output.net
@@ -41,17 +41,17 @@ i["T1","4"]+i["U1","3"]==0,
i["C4","2"]+i["C3","2"]+i["R1","3"]+i["R1","1"]+i["C2","2"]+i["C1","2"]+i["U1","2"]==0,
i["U2","3"]+i["C2","1"]+i["C1","1"]+i["U1","1"]==0};
modelEquations={
-fuse[value->f1]["F1"],
-resistor[value->220]["R2"],
-mains_connector[value->conn1]["CONN1"],
+lm317[value->u2]["U2"],
polarized_capacitor[value->1uf]["C4"],
-variable_resistor[value->5k]["R1"],
polarized_capacitor[value->22uF]["C3"],
+variable_resistor[value->5k]["R1"],
polarized_capacitor[value->0.1uF]["C2"],
-spst[value->s1]["S1"],
+resistor[value->220]["R2"],
polarized_capacitor[value->2200uF]["C1"],
+spst[value->s1]["S1"],
+mains_connector[value->conn1]["CONN1"],
transformer[value->t1]["T1"],
-lm317[value->u2]["U2"],
+fuse[value->f1]["F1"],
diode-bridge[value->u1]["U1"]};
variables={
v["ten"],
diff --git a/gnetlist/tests/common/outputs/maxascii/JD-output.net b/gnetlist/tests/common/outputs/maxascii/JD-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net
index b98bead..676b117 100644
--- a/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP V1 "none"
-*COMP Cm "unknown"
*COMP A1 "unknown"
-*COMP Rt "unknown"
-*COMP M1 "unknown"
-*COMP X1 "unknown"
+*COMP Cm "unknown"
+*COMP Cp "unknown"
*COMP Rlp "unknown"
-*COMP Vdd "none"
*COMP Rlm "unknown"
-*COMP Cp "unknown"
+*COMP Vdd "none"
+*COMP V1 "none"
+*COMP Rt "unknown"
*COMP Rb "unknown"
+*COMP M1 "unknown"
+*COMP X1 "unknown"
*NET "Vdd1"
*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
*NET "GND"
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net
index 2a0eb09..3cb3943 100644
--- a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net
@@ -1,28 +1,28 @@
*OrCAD
*START
-*COMP Cout "unknown"
-*COMP R5 "unknown"
+*COMP C2 "unknown"
*COMP R4 "unknown"
+*COMP R3 "unknown"
+*COMP R8 "unknown"
+*COMP CE2 "unknown"
*COMP RE2 "unknown"
+*COMP RC1 "unknown"
*COMP Q2 "unknown"
+*COMP C1 "unknown"
*COMP A3 "unknown"
-*COMP R3 "unknown"
*COMP A2 "unknown"
-*COMP RE1 "unknown"
-*COMP Q1 "unknown"
*COMP A1 "unknown"
-*COMP R2 "unknown"
+*COMP VCC "none"
*COMP Vinput "none"
-*COMP R1 "unknown"
-*COMP C2 "unknown"
-*COMP CE2 "unknown"
-*COMP C1 "unknown"
*COMP CE1 "unknown"
-*COMP R8 "unknown"
-*COMP VCC "none"
-*COMP RC2 "unknown"
-*COMP RC1 "unknown"
+*COMP Cout "unknown"
*COMP RL "unknown"
+*COMP RC2 "unknown"
+*COMP RE1 "unknown"
+*COMP R2 "unknown"
+*COMP R1 "unknown"
+*COMP R5 "unknown"
+*COMP Q1 "unknown"
*NET "unnamed_net2"
*NET "unnamed_net2" C2."1" R8."2"
*NET "Vbase2"
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net
index 2a0eb09..3cb3943 100644
--- a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net
@@ -1,28 +1,28 @@
*OrCAD
*START
-*COMP Cout "unknown"
-*COMP R5 "unknown"
+*COMP C2 "unknown"
*COMP R4 "unknown"
+*COMP R3 "unknown"
+*COMP R8 "unknown"
+*COMP CE2 "unknown"
*COMP RE2 "unknown"
+*COMP RC1 "unknown"
*COMP Q2 "unknown"
+*COMP C1 "unknown"
*COMP A3 "unknown"
-*COMP R3 "unknown"
*COMP A2 "unknown"
-*COMP RE1 "unknown"
-*COMP Q1 "unknown"
*COMP A1 "unknown"
-*COMP R2 "unknown"
+*COMP VCC "none"
*COMP Vinput "none"
-*COMP R1 "unknown"
-*COMP C2 "unknown"
-*COMP CE2 "unknown"
-*COMP C1 "unknown"
*COMP CE1 "unknown"
-*COMP R8 "unknown"
-*COMP VCC "none"
-*COMP RC2 "unknown"
-*COMP RC1 "unknown"
+*COMP Cout "unknown"
*COMP RL "unknown"
+*COMP RC2 "unknown"
+*COMP RE1 "unknown"
+*COMP R2 "unknown"
+*COMP R1 "unknown"
+*COMP R5 "unknown"
+*COMP Q1 "unknown"
*NET "unnamed_net2"
*NET "unnamed_net2" C2."1" R8."2"
*NET "Vbase2"
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net
index 2a0eb09..3cb3943 100644
--- a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net
@@ -1,28 +1,28 @@
*OrCAD
*START
-*COMP Cout "unknown"
-*COMP R5 "unknown"
+*COMP C2 "unknown"
*COMP R4 "unknown"
+*COMP R3 "unknown"
+*COMP R8 "unknown"
+*COMP CE2 "unknown"
*COMP RE2 "unknown"
+*COMP RC1 "unknown"
*COMP Q2 "unknown"
+*COMP C1 "unknown"
*COMP A3 "unknown"
-*COMP R3 "unknown"
*COMP A2 "unknown"
-*COMP RE1 "unknown"
-*COMP Q1 "unknown"
*COMP A1 "unknown"
-*COMP R2 "unknown"
+*COMP VCC "none"
*COMP Vinput "none"
-*COMP R1 "unknown"
-*COMP C2 "unknown"
-*COMP CE2 "unknown"
-*COMP C1 "unknown"
*COMP CE1 "unknown"
-*COMP R8 "unknown"
-*COMP VCC "none"
-*COMP RC2 "unknown"
-*COMP RC1 "unknown"
+*COMP Cout "unknown"
*COMP RL "unknown"
+*COMP RC2 "unknown"
+*COMP RE1 "unknown"
+*COMP R2 "unknown"
+*COMP R1 "unknown"
+*COMP R5 "unknown"
+*COMP Q1 "unknown"
*NET "unnamed_net2"
*NET "unnamed_net2" C2."1" R8."2"
*NET "Vbase2"
diff --git a/gnetlist/tests/common/outputs/maxascii/cascade-output.net b/gnetlist/tests/common/outputs/maxascii/cascade-output.net
index 626660d..3fd37b3 100644
--- a/gnetlist/tests/common/outputs/maxascii/cascade-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/cascade-output.net
@@ -1,13 +1,13 @@
*OrCAD
*START
*COMP AMP2 "none"
+*COMP T1 "none"
+*COMP MX1 "none"
+*COMP FL1 "none"
+*COMP DEF1 "none"
*COMP AMP1 "none"
*COMP SOURCE "none"
*COMP DEFAULTS "unknown"
-*COMP MX1 "none"
-*COMP DEF1 "none"
-*COMP T1 "none"
-*COMP FL1 "none"
*NET "unnamed_net6"
*NET "unnamed_net6" AMP2."1" T1."2"
*NET "unnamed_net5"
diff --git a/gnetlist/tests/common/outputs/maxascii/multiequal-output.net b/gnetlist/tests/common/outputs/maxascii/multiequal-output.net
index 5e0d9f7..86f4902 100644
--- a/gnetlist/tests/common/outputs/maxascii/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/multiequal-output.net
@@ -1,8 +1,8 @@
*OrCAD
*START
*COMP V1 "none"
-*COMP A1 "unknown"
*COMP R1 "unknown"
+*COMP A1 "unknown"
*NET "GND"
*NET "GND" V1."2" R1."1"
*NET "unnamed_net1"
diff --git a/gnetlist/tests/common/outputs/maxascii/netattrib-output.net b/gnetlist/tests/common/outputs/maxascii/netattrib-output.net
index e5bfeb3..d823c0c 100644
--- a/gnetlist/tests/common/outputs/maxascii/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/netattrib-output.net
@@ -1,9 +1,9 @@
*OrCAD
*START
*COMP F1 "unknown"
-*COMP U100 "DIP14"
*COMP U300 "DIP14"
*COMP U200 "DIP14"
+*COMP U100 "DIP14"
*NET "unnamed_net1"
*NET "unnamed_net1" U300."2"
*NET "netattrib"
diff --git a/gnetlist/tests/common/outputs/maxascii/powersupply-output.net b/gnetlist/tests/common/outputs/maxascii/powersupply-output.net
index dd9b9bd..2892cf5 100644
--- a/gnetlist/tests/common/outputs/maxascii/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/maxascii/powersupply-output.net
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP F1 "unknown"
-*COMP R2 "unknown"
-*COMP CONN1 "unknown"
+*COMP U2 "unknown"
*COMP C4 "unknown"
-*COMP R1 "unknown"
*COMP C3 "unknown"
+*COMP R1 "unknown"
*COMP C2 "unknown"
-*COMP S1 "unknown"
+*COMP R2 "unknown"
*COMP C1 "unknown"
+*COMP S1 "unknown"
+*COMP CONN1 "unknown"
*COMP T1 "unknown"
-*COMP U2 "unknown"
+*COMP F1 "unknown"
*COMP U1 "unknown"
*NET "ten"
*NET "ten" U2."1" R1."2" C3."1" R2."1"
diff --git a/gnetlist/tests/common/outputs/osmond/JD-output.net b/gnetlist/tests/common/outputs/osmond/JD-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include-output.net b/gnetlist/tests/common/outputs/osmond/JD_Include-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net b/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net
index 36c7463..1ef6fb4 100644
--- a/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net
@@ -1,14 +1,14 @@
-Part none { Name V1 }
-Part unknown { Name Cm }
Part unknown { Name A1 }
-Part unknown { Name Rt }
-Part unknown { Name M1 }
-Part unknown { Name X1 }
+Part unknown { Name Cm }
+Part unknown { Name Cp }
Part unknown { Name Rlp }
-Part none { Name Vdd }
Part unknown { Name Rlm }
-Part unknown { Name Cp }
+Part none { Name Vdd }
+Part none { Name V1 }
+Part unknown { Name Rt }
Part unknown { Name Rb }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
Signal "Vdd1"
{ Rlp-2 M1-B M1-S Vdd-1 X1-6 }
Signal "GND"
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net
index a5ee1e7..8746aa8 100644
--- a/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net
@@ -1,26 +1,26 @@
-Part unknown { Name Cout }
-Part unknown { Name R5 }
+Part unknown { Name C2 }
Part unknown { Name R4 }
+Part unknown { Name R3 }
+Part unknown { Name R8 }
+Part unknown { Name CE2 }
Part unknown { Name RE2 }
+Part unknown { Name RC1 }
Part unknown { Name Q2 }
+Part unknown { Name C1 }
Part unknown { Name A3 }
-Part unknown { Name R3 }
Part unknown { Name A2 }
-Part unknown { Name RE1 }
-Part unknown { Name Q1 }
Part unknown { Name A1 }
-Part unknown { Name R2 }
+Part none { Name VCC }
Part none { Name Vinput }
-Part unknown { Name R1 }
-Part unknown { Name C2 }
-Part unknown { Name CE2 }
-Part unknown { Name C1 }
Part unknown { Name CE1 }
-Part unknown { Name R8 }
-Part none { Name VCC }
-Part unknown { Name RC2 }
-Part unknown { Name RC1 }
+Part unknown { Name Cout }
Part unknown { Name RL }
+Part unknown { Name RC2 }
+Part unknown { Name RE1 }
+Part unknown { Name R2 }
+Part unknown { Name R1 }
+Part unknown { Name R5 }
+Part unknown { Name Q1 }
Signal "unnamed_net2"
{ C2-1 R8-2 }
Signal "Vbase2"
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net
index a5ee1e7..8746aa8 100644
--- a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net
@@ -1,26 +1,26 @@
-Part unknown { Name Cout }
-Part unknown { Name R5 }
+Part unknown { Name C2 }
Part unknown { Name R4 }
+Part unknown { Name R3 }
+Part unknown { Name R8 }
+Part unknown { Name CE2 }
Part unknown { Name RE2 }
+Part unknown { Name RC1 }
Part unknown { Name Q2 }
+Part unknown { Name C1 }
Part unknown { Name A3 }
-Part unknown { Name R3 }
Part unknown { Name A2 }
-Part unknown { Name RE1 }
-Part unknown { Name Q1 }
Part unknown { Name A1 }
-Part unknown { Name R2 }
+Part none { Name VCC }
Part none { Name Vinput }
-Part unknown { Name R1 }
-Part unknown { Name C2 }
-Part unknown { Name CE2 }
-Part unknown { Name C1 }
Part unknown { Name CE1 }
-Part unknown { Name R8 }
-Part none { Name VCC }
-Part unknown { Name RC2 }
-Part unknown { Name RC1 }
+Part unknown { Name Cout }
Part unknown { Name RL }
+Part unknown { Name RC2 }
+Part unknown { Name RE1 }
+Part unknown { Name R2 }
+Part unknown { Name R1 }
+Part unknown { Name R5 }
+Part unknown { Name Q1 }
Signal "unnamed_net2"
{ C2-1 R8-2 }
Signal "Vbase2"
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net
index a5ee1e7..8746aa8 100644
--- a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net
@@ -1,26 +1,26 @@
-Part unknown { Name Cout }
-Part unknown { Name R5 }
+Part unknown { Name C2 }
Part unknown { Name R4 }
+Part unknown { Name R3 }
+Part unknown { Name R8 }
+Part unknown { Name CE2 }
Part unknown { Name RE2 }
+Part unknown { Name RC1 }
Part unknown { Name Q2 }
+Part unknown { Name C1 }
Part unknown { Name A3 }
-Part unknown { Name R3 }
Part unknown { Name A2 }
-Part unknown { Name RE1 }
-Part unknown { Name Q1 }
Part unknown { Name A1 }
-Part unknown { Name R2 }
+Part none { Name VCC }
Part none { Name Vinput }
-Part unknown { Name R1 }
-Part unknown { Name C2 }
-Part unknown { Name CE2 }
-Part unknown { Name C1 }
Part unknown { Name CE1 }
-Part unknown { Name R8 }
-Part none { Name VCC }
-Part unknown { Name RC2 }
-Part unknown { Name RC1 }
+Part unknown { Name Cout }
Part unknown { Name RL }
+Part unknown { Name RC2 }
+Part unknown { Name RE1 }
+Part unknown { Name R2 }
+Part unknown { Name R1 }
+Part unknown { Name R5 }
+Part unknown { Name Q1 }
Signal "unnamed_net2"
{ C2-1 R8-2 }
Signal "Vbase2"
diff --git a/gnetlist/tests/common/outputs/osmond/cascade-output.net b/gnetlist/tests/common/outputs/osmond/cascade-output.net
index e282543..7470a21 100644
--- a/gnetlist/tests/common/outputs/osmond/cascade-output.net
+++ b/gnetlist/tests/common/outputs/osmond/cascade-output.net
@@ -1,11 +1,11 @@
Part none { Name AMP2 }
+Part none { Name T1 }
+Part none { Name MX1 }
+Part none { Name FL1 }
+Part none { Name DEF1 }
Part none { Name AMP1 }
Part none { Name SOURCE }
Part unknown { Name DEFAULTS }
-Part none { Name MX1 }
-Part none { Name DEF1 }
-Part none { Name T1 }
-Part none { Name FL1 }
Signal "unnamed_net6"
{ AMP2-1 T1-2 }
Signal "unnamed_net5"
diff --git a/gnetlist/tests/common/outputs/osmond/multiequal-output.net b/gnetlist/tests/common/outputs/osmond/multiequal-output.net
index f692926..fe3c642 100644
--- a/gnetlist/tests/common/outputs/osmond/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/osmond/multiequal-output.net
@@ -1,6 +1,6 @@
Part none { Name V1 }
-Part unknown { Name A1 }
Part unknown { Name R1 }
+Part unknown { Name A1 }
Signal "GND"
{ V1-2 R1-1 }
Signal "unnamed_net1"
diff --git a/gnetlist/tests/common/outputs/osmond/netattrib-output.net b/gnetlist/tests/common/outputs/osmond/netattrib-output.net
index 5a73ae9..677e5c6 100644
--- a/gnetlist/tests/common/outputs/osmond/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/osmond/netattrib-output.net
@@ -1,7 +1,7 @@
Part unknown { Name F1 }
-Part DIP14 { Name U100 }
Part DIP14 { Name U300 }
Part DIP14 { Name U200 }
+Part DIP14 { Name U100 }
Signal "unnamed_net1"
{ U300-2 }
Signal "netattrib"
diff --git a/gnetlist/tests/common/outputs/osmond/powersupply-output.net b/gnetlist/tests/common/outputs/osmond/powersupply-output.net
index aee49b2..ffb999f 100644
--- a/gnetlist/tests/common/outputs/osmond/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/osmond/powersupply-output.net
@@ -1,14 +1,14 @@
-Part unknown { Name F1 }
-Part unknown { Name R2 }
-Part unknown { Name CONN1 }
+Part unknown { Name U2 }
Part unknown { Name C4 }
-Part unknown { Name R1 }
Part unknown { Name C3 }
+Part unknown { Name R1 }
Part unknown { Name C2 }
-Part unknown { Name S1 }
+Part unknown { Name R2 }
Part unknown { Name C1 }
+Part unknown { Name S1 }
+Part unknown { Name CONN1 }
Part unknown { Name T1 }
-Part unknown { Name U2 }
+Part unknown { Name F1 }
Part unknown { Name U1 }
Signal "ten"
{ U2-1 R1-2 C3-1 R2-1 }
diff --git a/gnetlist/tests/common/outputs/pads/JD-output.net b/gnetlist/tests/common/outputs/pads/JD-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include-output.net b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net
index f3a5213..44b3ced 100644
--- a/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-V1 none
-CM unknown
A1 unknown
-RT unknown
-M1 unknown
-X1 unknown
+CM unknown
+CP unknown
RLP unknown
-VDD none
RLM unknown
-CP unknown
+VDD none
+V1 none
+RT unknown
RB unknown
+M1 unknown
+X1 unknown
*NET*
*SIGNAL* VDD1
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
index f443d47..e76e595 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
@@ -1,29 +1,29 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-COUT unknown
-R5 unknown
+C2 unknown
R4 unknown
+R3 unknown
+R8 unknown
+CE2 unknown
RE2 unknown
+RC1 unknown
Q2 unknown
+C1 unknown
A3 unknown
-R3 unknown
A2 unknown
-RE1 unknown
-Q1 unknown
A1 unknown
-R2 unknown
+VCC none
VINPUT none
-R1 unknown
-C2 unknown
-CE2 unknown
-C1 unknown
CE1 unknown
-R8 unknown
-VCC none
-RC2 unknown
-RC1 unknown
+COUT unknown
RL unknown
+RC2 unknown
+RE1 unknown
+R2 unknown
+R1 unknown
+R5 unknown
+Q1 unknown
*NET*
*SIGNAL* UNNAMED_NET2
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
index f443d47..e76e595 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
@@ -1,29 +1,29 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-COUT unknown
-R5 unknown
+C2 unknown
R4 unknown
+R3 unknown
+R8 unknown
+CE2 unknown
RE2 unknown
+RC1 unknown
Q2 unknown
+C1 unknown
A3 unknown
-R3 unknown
A2 unknown
-RE1 unknown
-Q1 unknown
A1 unknown
-R2 unknown
+VCC none
VINPUT none
-R1 unknown
-C2 unknown
-CE2 unknown
-C1 unknown
CE1 unknown
-R8 unknown
-VCC none
-RC2 unknown
-RC1 unknown
+COUT unknown
RL unknown
+RC2 unknown
+RE1 unknown
+R2 unknown
+R1 unknown
+R5 unknown
+Q1 unknown
*NET*
*SIGNAL* UNNAMED_NET2
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
index f443d47..e76e595 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
@@ -1,29 +1,29 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-COUT unknown
-R5 unknown
+C2 unknown
R4 unknown
+R3 unknown
+R8 unknown
+CE2 unknown
RE2 unknown
+RC1 unknown
Q2 unknown
+C1 unknown
A3 unknown
-R3 unknown
A2 unknown
-RE1 unknown
-Q1 unknown
A1 unknown
-R2 unknown
+VCC none
VINPUT none
-R1 unknown
-C2 unknown
-CE2 unknown
-C1 unknown
CE1 unknown
-R8 unknown
-VCC none
-RC2 unknown
-RC1 unknown
+COUT unknown
RL unknown
+RC2 unknown
+RE1 unknown
+R2 unknown
+R1 unknown
+R5 unknown
+Q1 unknown
*NET*
*SIGNAL* UNNAMED_NET2
diff --git a/gnetlist/tests/common/outputs/pads/cascade-output.net b/gnetlist/tests/common/outputs/pads/cascade-output.net
index 52c4cd5..bb0b38b 100644
--- a/gnetlist/tests/common/outputs/pads/cascade-output.net
+++ b/gnetlist/tests/common/outputs/pads/cascade-output.net
@@ -2,13 +2,13 @@
*PART*
AMP2 none
+T1 none
+MX1 none
+FL1 none
+DEF1 none
AMP1 none
SOURCE none
DEFAULTS unknown
-MX1 none
-DEF1 none
-T1 none
-FL1 none
*NET*
*SIGNAL* UNNAMED_NET6
diff --git a/gnetlist/tests/common/outputs/pads/multiequal-output.net b/gnetlist/tests/common/outputs/pads/multiequal-output.net
index d325973..1de68bd 100644
--- a/gnetlist/tests/common/outputs/pads/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/pads/multiequal-output.net
@@ -2,8 +2,8 @@
*PART*
V1 none
-A1 unknown
R1 unknown
+A1 unknown
*NET*
*SIGNAL* GND
diff --git a/gnetlist/tests/common/outputs/pads/netattrib-output.net b/gnetlist/tests/common/outputs/pads/netattrib-output.net
index 332cf53..1540a81 100644
--- a/gnetlist/tests/common/outputs/pads/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/pads/netattrib-output.net
@@ -2,9 +2,9 @@
*PART*
F1 unknown
-U100 DIP14
U300 DIP14
U200 DIP14
+U100 DIP14
*NET*
*SIGNAL* UNNAMED_NET1
diff --git a/gnetlist/tests/common/outputs/pads/powersupply-output.net b/gnetlist/tests/common/outputs/pads/powersupply-output.net
index 3aa5cd9..0688481 100644
--- a/gnetlist/tests/common/outputs/pads/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/pads/powersupply-output.net
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-F1 unknown
-R2 unknown
-CONN1 unknown
+U2 unknown
C4 unknown
-R1 unknown
C3 unknown
+R1 unknown
C2 unknown
-S1 unknown
+R2 unknown
C1 unknown
+S1 unknown
+CONN1 unknown
T1 unknown
-U2 unknown
+F1 unknown
U1 unknown
*NET*
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD-output.net b/gnetlist/tests/common/outputs/pcbpins/JD-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net
index c68ad7b..31f3e8f 100644
--- a/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net
@@ -1,19 +1,39 @@
# Pin name action command file
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
+# Start of element A1
# Start of element Cm
ChangePinName(Cm, 2, 2)
ChangePinName(Cm, 1, 1)
-# Start of element A1
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
# Start of element Rt
ChangePinName(Rt, 1, 1)
ChangePinName(Rt, 2, 2)
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
+
# Start of element M1
ChangePinName(M1, G, G)
ChangePinName(M1, D, D)
@@ -28,23 +48,3 @@ ChangePinName(X1, 3, VH)
ChangePinName(X1, 1, D)
ChangePinName(X1, 5, Y1)
ChangePinName(X1, 4, Y0)
-
-# Start of element Rlp
-ChangePinName(Rlp, 1, 1)
-ChangePinName(Rlp, 2, 2)
-
-# Start of element Vdd
-ChangePinName(Vdd, 2, -)
-ChangePinName(Vdd, 1, +)
-
-# Start of element Rlm
-ChangePinName(Rlm, 1, 1)
-ChangePinName(Rlm, 2, 2)
-
-# Start of element Cp
-ChangePinName(Cp, 2, 2)
-ChangePinName(Cp, 1, 1)
-
-# Start of element Rb
-ChangePinName(Rb, 1, 1)
-ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net
index 3674577..1e7e0fa 100644
--- a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net
@@ -1,89 +1,89 @@
# Pin name action command file
-# Start of element Cout
-ChangePinName(Cout, 2, 2)
-ChangePinName(Cout, 1, 1)
-
-# Start of element R5
-ChangePinName(R5, 1, 1)
-ChangePinName(R5, 2, 2)
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
# Start of element R4
ChangePinName(R4, 1, 1)
ChangePinName(R4, 2, 2)
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
# Start of element RE2
ChangePinName(RE2, 1, 1)
ChangePinName(RE2, 2, 2)
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
# Start of element Q2
ChangePinName(Q2, 2, 2)
ChangePinName(Q2, 1, 1)
ChangePinName(Q2, 3, 3)
-# Start of element A3
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
-# Start of element R3
-ChangePinName(R3, 1, 1)
-ChangePinName(R3, 2, 2)
+# Start of element A3
# Start of element A2
-# Start of element RE1
-ChangePinName(RE1, 1, 1)
-ChangePinName(RE1, 2, 2)
-
-# Start of element Q1
-ChangePinName(Q1, 2, 2)
-ChangePinName(Q1, 1, 1)
-ChangePinName(Q1, 3, 3)
-
# Start of element A1
-# Start of element R2
-ChangePinName(R2, 1, 1)
-ChangePinName(R2, 2, 2)
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
# Start of element Vinput
ChangePinName(Vinput, 2, -)
ChangePinName(Vinput, 1, +)
-# Start of element R1
-ChangePinName(R1, 1, 1)
-ChangePinName(R1, 2, 2)
-
-# Start of element C2
-ChangePinName(C2, 2, 2)
-ChangePinName(C2, 1, 1)
-
-# Start of element CE2
-ChangePinName(CE2, 2, 2)
-ChangePinName(CE2, 1, 1)
-
-# Start of element C1
-ChangePinName(C1, 2, 2)
-ChangePinName(C1, 1, 1)
-
# Start of element CE1
ChangePinName(CE1, 2, 2)
ChangePinName(CE1, 1, 1)
-# Start of element R8
-ChangePinName(R8, 1, 1)
-ChangePinName(R8, 2, 2)
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
-# Start of element VCC
-ChangePinName(VCC, 2, -)
-ChangePinName(VCC, 1, +)
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
# Start of element RC2
ChangePinName(RC2, 1, 1)
ChangePinName(RC2, 2, 2)
-# Start of element RC1
-ChangePinName(RC1, 1, 1)
-ChangePinName(RC1, 2, 2)
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
-# Start of element RL
-ChangePinName(RL, 1, 1)
-ChangePinName(RL, 2, 2)
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net
index 3674577..1e7e0fa 100644
--- a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net
@@ -1,89 +1,89 @@
# Pin name action command file
-# Start of element Cout
-ChangePinName(Cout, 2, 2)
-ChangePinName(Cout, 1, 1)
-
-# Start of element R5
-ChangePinName(R5, 1, 1)
-ChangePinName(R5, 2, 2)
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
# Start of element R4
ChangePinName(R4, 1, 1)
ChangePinName(R4, 2, 2)
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
# Start of element RE2
ChangePinName(RE2, 1, 1)
ChangePinName(RE2, 2, 2)
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
# Start of element Q2
ChangePinName(Q2, 2, 2)
ChangePinName(Q2, 1, 1)
ChangePinName(Q2, 3, 3)
-# Start of element A3
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
-# Start of element R3
-ChangePinName(R3, 1, 1)
-ChangePinName(R3, 2, 2)
+# Start of element A3
# Start of element A2
-# Start of element RE1
-ChangePinName(RE1, 1, 1)
-ChangePinName(RE1, 2, 2)
-
-# Start of element Q1
-ChangePinName(Q1, 2, 2)
-ChangePinName(Q1, 1, 1)
-ChangePinName(Q1, 3, 3)
-
# Start of element A1
-# Start of element R2
-ChangePinName(R2, 1, 1)
-ChangePinName(R2, 2, 2)
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
# Start of element Vinput
ChangePinName(Vinput, 2, -)
ChangePinName(Vinput, 1, +)
-# Start of element R1
-ChangePinName(R1, 1, 1)
-ChangePinName(R1, 2, 2)
-
-# Start of element C2
-ChangePinName(C2, 2, 2)
-ChangePinName(C2, 1, 1)
-
-# Start of element CE2
-ChangePinName(CE2, 2, 2)
-ChangePinName(CE2, 1, 1)
-
-# Start of element C1
-ChangePinName(C1, 2, 2)
-ChangePinName(C1, 1, 1)
-
# Start of element CE1
ChangePinName(CE1, 2, 2)
ChangePinName(CE1, 1, 1)
-# Start of element R8
-ChangePinName(R8, 1, 1)
-ChangePinName(R8, 2, 2)
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
-# Start of element VCC
-ChangePinName(VCC, 2, -)
-ChangePinName(VCC, 1, +)
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
# Start of element RC2
ChangePinName(RC2, 1, 1)
ChangePinName(RC2, 2, 2)
-# Start of element RC1
-ChangePinName(RC1, 1, 1)
-ChangePinName(RC1, 2, 2)
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
-# Start of element RL
-ChangePinName(RL, 1, 1)
-ChangePinName(RL, 2, 2)
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net
index 3674577..1e7e0fa 100644
--- a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net
@@ -1,89 +1,89 @@
# Pin name action command file
-# Start of element Cout
-ChangePinName(Cout, 2, 2)
-ChangePinName(Cout, 1, 1)
-
-# Start of element R5
-ChangePinName(R5, 1, 1)
-ChangePinName(R5, 2, 2)
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
# Start of element R4
ChangePinName(R4, 1, 1)
ChangePinName(R4, 2, 2)
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
# Start of element RE2
ChangePinName(RE2, 1, 1)
ChangePinName(RE2, 2, 2)
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
# Start of element Q2
ChangePinName(Q2, 2, 2)
ChangePinName(Q2, 1, 1)
ChangePinName(Q2, 3, 3)
-# Start of element A3
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
-# Start of element R3
-ChangePinName(R3, 1, 1)
-ChangePinName(R3, 2, 2)
+# Start of element A3
# Start of element A2
-# Start of element RE1
-ChangePinName(RE1, 1, 1)
-ChangePinName(RE1, 2, 2)
-
-# Start of element Q1
-ChangePinName(Q1, 2, 2)
-ChangePinName(Q1, 1, 1)
-ChangePinName(Q1, 3, 3)
-
# Start of element A1
-# Start of element R2
-ChangePinName(R2, 1, 1)
-ChangePinName(R2, 2, 2)
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
# Start of element Vinput
ChangePinName(Vinput, 2, -)
ChangePinName(Vinput, 1, +)
-# Start of element R1
-ChangePinName(R1, 1, 1)
-ChangePinName(R1, 2, 2)
-
-# Start of element C2
-ChangePinName(C2, 2, 2)
-ChangePinName(C2, 1, 1)
-
-# Start of element CE2
-ChangePinName(CE2, 2, 2)
-ChangePinName(CE2, 1, 1)
-
-# Start of element C1
-ChangePinName(C1, 2, 2)
-ChangePinName(C1, 1, 1)
-
# Start of element CE1
ChangePinName(CE1, 2, 2)
ChangePinName(CE1, 1, 1)
-# Start of element R8
-ChangePinName(R8, 1, 1)
-ChangePinName(R8, 2, 2)
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
-# Start of element VCC
-ChangePinName(VCC, 2, -)
-ChangePinName(VCC, 1, +)
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
# Start of element RC2
ChangePinName(RC2, 1, 1)
ChangePinName(RC2, 2, 2)
-# Start of element RC1
-ChangePinName(RC1, 1, 1)
-ChangePinName(RC1, 2, 2)
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
-# Start of element RL
-ChangePinName(RL, 1, 1)
-ChangePinName(RL, 2, 2)
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
diff --git a/gnetlist/tests/common/outputs/pcbpins/cascade-output.net b/gnetlist/tests/common/outputs/pcbpins/cascade-output.net
index 8105894..4ae1b9a 100644
--- a/gnetlist/tests/common/outputs/pcbpins/cascade-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/cascade-output.net
@@ -4,28 +4,28 @@
ChangePinName(AMP2, 2, OUT)
ChangePinName(AMP2, 1, IN)
-# Start of element AMP1
-ChangePinName(AMP1, 2, OUT)
-ChangePinName(AMP1, 1, IN)
-
-# Start of element SOURCE
-ChangePinName(SOURCE, 1, OUT)
-
-# Start of element DEFAULTS
-ChangePinName(DEFAULTS, unknown, unknown)
+# Start of element T1
+ChangePinName(T1, 2, 2)
+ChangePinName(T1, 1, 1)
# Start of element MX1
ChangePinName(MX1, 2, OUT)
ChangePinName(MX1, 1, IN)
+# Start of element FL1
+ChangePinName(FL1, 2, O)
+ChangePinName(FL1, 1, I)
+
# Start of element DEF1
ChangePinName(DEF1, 2, OUT)
ChangePinName(DEF1, 1, IN)
-# Start of element T1
-ChangePinName(T1, 2, 2)
-ChangePinName(T1, 1, 1)
+# Start of element AMP1
+ChangePinName(AMP1, 2, OUT)
+ChangePinName(AMP1, 1, IN)
-# Start of element FL1
-ChangePinName(FL1, 2, O)
-ChangePinName(FL1, 1, I)
+# Start of element SOURCE
+ChangePinName(SOURCE, 1, OUT)
+
+# Start of element DEFAULTS
+ChangePinName(DEFAULTS, unknown, unknown)
diff --git a/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net b/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net
index cd11be3..4b72338 100644
--- a/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net
@@ -4,8 +4,8 @@
ChangePinName(V1, 2, -)
ChangePinName(V1, 1, +)
-# Start of element A1
-
# Start of element R1
ChangePinName(R1, 1, 1)
ChangePinName(R1, 2, 2)
+
+# Start of element A1
diff --git a/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net b/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net
index 8a641ba..fafdbe3 100644
--- a/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net
@@ -4,14 +4,6 @@
ChangePinName(F1, 2, 2)
ChangePinName(F1, 1, 1)
-# Start of element U100
-ChangePinName(U100, unknown, unknown)
-ChangePinName(U100, unknown, unknown)
-ChangePinName(U100, unknown, unknown)
-ChangePinName(U100, 1, A)
-ChangePinName(U100, 2, B)
-ChangePinName(U100, 3, Y)
-
# Start of element U300
ChangePinName(U300, unknown, unknown)
ChangePinName(U300, unknown, unknown)
@@ -23,3 +15,11 @@ ChangePinName(U200, unknown, unknown)
ChangePinName(U200, unknown, unknown)
ChangePinName(U200, 2, Y)
ChangePinName(U200, 1, A)
+
+# Start of element U100
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, 1, A)
+ChangePinName(U100, 2, B)
+ChangePinName(U100, 3, Y)
diff --git a/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net b/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net
index eef4f52..4e72395 100644
--- a/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net
@@ -1,53 +1,53 @@
# Pin name action command file
-# Start of element F1
-ChangePinName(F1, 2, 2)
-ChangePinName(F1, 1, 1)
-
-# Start of element R2
-ChangePinName(R2, 1, 1)
-ChangePinName(R2, 2, 2)
-
-# Start of element CONN1
-ChangePinName(CONN1, 3, 3)
-ChangePinName(CONN1, 2, 2)
-ChangePinName(CONN1, 1, 1)
+# Start of element U2
+ChangePinName(U2, 1, Adjust)
+ChangePinName(U2, 3, Vin)
+ChangePinName(U2, 2, Vout)
# Start of element C4
ChangePinName(C4, 2, -)
ChangePinName(C4, 1, +)
+# Start of element C3
+ChangePinName(C3, 2, -)
+ChangePinName(C3, 1, +)
+
# Start of element R1
ChangePinName(R1, 1, 1)
ChangePinName(R1, 2, 2)
ChangePinName(R1, 3, 3)
-# Start of element C3
-ChangePinName(C3, 2, -)
-ChangePinName(C3, 1, +)
-
# Start of element C2
ChangePinName(C2, 2, -)
ChangePinName(C2, 1, +)
-# Start of element S1
-ChangePinName(S1, 1, 1)
-ChangePinName(S1, 2, 2)
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
# Start of element C1
ChangePinName(C1, 2, -)
ChangePinName(C1, 1, +)
+# Start of element S1
+ChangePinName(S1, 1, 1)
+ChangePinName(S1, 2, 2)
+
+# Start of element CONN1
+ChangePinName(CONN1, 3, 3)
+ChangePinName(CONN1, 2, 2)
+ChangePinName(CONN1, 1, 1)
+
# Start of element T1
ChangePinName(T1, 3, 3)
ChangePinName(T1, 4, 4)
ChangePinName(T1, 1, 1)
ChangePinName(T1, 2, 2)
-# Start of element U2
-ChangePinName(U2, 1, Adjust)
-ChangePinName(U2, 3, Vin)
-ChangePinName(U2, 2, Vout)
+# Start of element F1
+ChangePinName(F1, 2, 2)
+ChangePinName(F1, 1, 1)
# Start of element U1
ChangePinName(U1, 4, 4)
diff --git a/gnetlist/tests/common/outputs/protelII/JD-output.net b/gnetlist/tests/common/outputs/protelII/JD-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include-output.net b/gnetlist/tests/common/outputs/protelII/JD_Include-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD_Include-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net b/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/JD_nomunge-output.net b/gnetlist/tests/common/outputs/protelII/JD_nomunge-output.net
index 17a4b68..3b368a3 100644
--- a/gnetlist/tests/common/outputs/protelII/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/protelII/JD_nomunge-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-V1
+A1
FOOTPRINT
-none
+unknown
PARTTYPE
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+model
DESCRIPTION
-vpulse
+model
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+Cp
FOOTPRINT
unknown
PARTTYPE
-model
+20p
DESCRIPTION
-model
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rt
+Rlp
FOOTPRINT
unknown
PARTTYPE
-1k
+1meg
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-M1
+Rlm
FOOTPRINT
unknown
PARTTYPE
-PMOS_TRANSISTOR
+500k
DESCRIPTION
-PMOS_TRANSISTOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-X1
+Vdd
FOOTPRINT
-unknown
+none
PARTTYPE
-LVD
+DC 3.3V
DESCRIPTION
-LVD
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlp
+V1
FOOTPRINT
-unknown
+none
PARTTYPE
-1meg
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
DESCRIPTION
-RESISTOR
+vpulse
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vdd
+Rt
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 3.3V
+1k
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -465,11 +465,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rlm
+Rb
FOOTPRINT
unknown
PARTTYPE
-500k
+5.6k
DESCRIPTION
RESISTOR
Part Field 1
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Cp
+M1
FOOTPRINT
unknown
PARTTYPE
-20p
+PMOS_TRANSISTOR
DESCRIPTION
-CAPACITOR
+PMOS_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Rb
+X1
FOOTPRINT
unknown
PARTTYPE
-5.6k
+LVD
DESCRIPTION
-RESISTOR
+LVD
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net
index b269748..d34ccc3 100644
--- a/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net
@@ -1,7 +1,7 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-Cout
+C2
FOOTPRINT
unknown
PARTTYPE
@@ -59,11 +59,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R5
+R4
FOOTPRINT
unknown
PARTTYPE
-10
+2.8K
DESCRIPTION
RESISTOR
Part Field 1
@@ -117,11 +117,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R4
+R3
FOOTPRINT
unknown
PARTTYPE
-2.8K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE2
+R8
FOOTPRINT
unknown
PARTTYPE
-100
+1
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q2
+CE2
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+1pF
DESCRIPTION
-NPN_TRANSISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A3
+RE2
FOOTPRINT
unknown
PARTTYPE
-.options TEMP=25
+100
DESCRIPTION
-directive
+RESISTOR
Part Field 1
*
Part Field 2
@@ -349,11 +349,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R3
+RC1
FOOTPRINT
unknown
PARTTYPE
-28K
+3.3K
DESCRIPTION
RESISTOR
Part Field 1
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A2
+Q2
FOOTPRINT
unknown
PARTTYPE
-include
+NPN_TRANSISTOR
DESCRIPTION
-include
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -465,13 +465,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE1
+C1
FOOTPRINT
unknown
PARTTYPE
-100
+2.2uF
DESCRIPTION
-RESISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q1
+A3
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+.options TEMP=25
DESCRIPTION
-NPN_TRANSISTOR
+directive
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+A2
FOOTPRINT
unknown
PARTTYPE
-model
+include
DESCRIPTION
-model
+include
Part Field 1
*
Part Field 2
@@ -639,13 +639,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R2
+A1
FOOTPRINT
unknown
PARTTYPE
-2K
+model
DESCRIPTION
-RESISTOR
+model
Part Field 1
*
Part Field 2
@@ -697,13 +697,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vinput
+VCC
FOOTPRINT
none
PARTTYPE
-DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DC 15V
DESCRIPTION
-vsin
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -755,13 +755,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+Vinput
FOOTPRINT
-unknown
+none
PARTTYPE
-28K
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DESCRIPTION
-RESISTOR
+vsin
Part Field 1
*
Part Field 2
@@ -813,11 +813,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C2
+CE1
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+1pF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -871,11 +871,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE2
+Cout
FOOTPRINT
unknown
PARTTYPE
-1pF
+2.2uF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -929,13 +929,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C1
+RL
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+100K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -987,13 +987,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE1
+RC2
FOOTPRINT
unknown
PARTTYPE
-1pF
+1K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1045,11 +1045,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R8
+RE1
FOOTPRINT
unknown
PARTTYPE
-1
+100
DESCRIPTION
RESISTOR
Part Field 1
@@ -1103,13 +1103,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-VCC
+R2
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 15V
+2K
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1161,11 +1161,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC2
+R1
FOOTPRINT
unknown
PARTTYPE
-1K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -1219,11 +1219,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC1
+R5
FOOTPRINT
unknown
PARTTYPE
-3.3K
+10
DESCRIPTION
RESISTOR
Part Field 1
@@ -1277,13 +1277,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RL
+Q1
FOOTPRINT
unknown
PARTTYPE
-100K
+NPN_TRANSISTOR
DESCRIPTION
-RESISTOR
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Include-output.net
index b269748..d34ccc3 100644
--- a/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Include-output.net
@@ -1,7 +1,7 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-Cout
+C2
FOOTPRINT
unknown
PARTTYPE
@@ -59,11 +59,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R5
+R4
FOOTPRINT
unknown
PARTTYPE
-10
+2.8K
DESCRIPTION
RESISTOR
Part Field 1
@@ -117,11 +117,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R4
+R3
FOOTPRINT
unknown
PARTTYPE
-2.8K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE2
+R8
FOOTPRINT
unknown
PARTTYPE
-100
+1
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q2
+CE2
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+1pF
DESCRIPTION
-NPN_TRANSISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A3
+RE2
FOOTPRINT
unknown
PARTTYPE
-.options TEMP=25
+100
DESCRIPTION
-directive
+RESISTOR
Part Field 1
*
Part Field 2
@@ -349,11 +349,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R3
+RC1
FOOTPRINT
unknown
PARTTYPE
-28K
+3.3K
DESCRIPTION
RESISTOR
Part Field 1
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A2
+Q2
FOOTPRINT
unknown
PARTTYPE
-include
+NPN_TRANSISTOR
DESCRIPTION
-include
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -465,13 +465,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE1
+C1
FOOTPRINT
unknown
PARTTYPE
-100
+2.2uF
DESCRIPTION
-RESISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q1
+A3
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+.options TEMP=25
DESCRIPTION
-NPN_TRANSISTOR
+directive
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+A2
FOOTPRINT
unknown
PARTTYPE
-model
+include
DESCRIPTION
-model
+include
Part Field 1
*
Part Field 2
@@ -639,13 +639,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R2
+A1
FOOTPRINT
unknown
PARTTYPE
-2K
+model
DESCRIPTION
-RESISTOR
+model
Part Field 1
*
Part Field 2
@@ -697,13 +697,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vinput
+VCC
FOOTPRINT
none
PARTTYPE
-DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DC 15V
DESCRIPTION
-vsin
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -755,13 +755,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+Vinput
FOOTPRINT
-unknown
+none
PARTTYPE
-28K
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DESCRIPTION
-RESISTOR
+vsin
Part Field 1
*
Part Field 2
@@ -813,11 +813,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C2
+CE1
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+1pF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -871,11 +871,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE2
+Cout
FOOTPRINT
unknown
PARTTYPE
-1pF
+2.2uF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -929,13 +929,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C1
+RL
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+100K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -987,13 +987,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE1
+RC2
FOOTPRINT
unknown
PARTTYPE
-1pF
+1K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1045,11 +1045,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R8
+RE1
FOOTPRINT
unknown
PARTTYPE
-1
+100
DESCRIPTION
RESISTOR
Part Field 1
@@ -1103,13 +1103,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-VCC
+R2
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 15V
+2K
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1161,11 +1161,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC2
+R1
FOOTPRINT
unknown
PARTTYPE
-1K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -1219,11 +1219,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC1
+R5
FOOTPRINT
unknown
PARTTYPE
-3.3K
+10
DESCRIPTION
RESISTOR
Part Field 1
@@ -1277,13 +1277,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RL
+Q1
FOOTPRINT
unknown
PARTTYPE
-100K
+NPN_TRANSISTOR
DESCRIPTION
-RESISTOR
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Sort-output.net
index b269748..d34ccc3 100644
--- a/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/protelII/TwoStageAmp_Sort-output.net
@@ -1,7 +1,7 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-Cout
+C2
FOOTPRINT
unknown
PARTTYPE
@@ -59,11 +59,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R5
+R4
FOOTPRINT
unknown
PARTTYPE
-10
+2.8K
DESCRIPTION
RESISTOR
Part Field 1
@@ -117,11 +117,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R4
+R3
FOOTPRINT
unknown
PARTTYPE
-2.8K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -175,11 +175,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE2
+R8
FOOTPRINT
unknown
PARTTYPE
-100
+1
DESCRIPTION
RESISTOR
Part Field 1
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q2
+CE2
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+1pF
DESCRIPTION
-NPN_TRANSISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A3
+RE2
FOOTPRINT
unknown
PARTTYPE
-.options TEMP=25
+100
DESCRIPTION
-directive
+RESISTOR
Part Field 1
*
Part Field 2
@@ -349,11 +349,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R3
+RC1
FOOTPRINT
unknown
PARTTYPE
-28K
+3.3K
DESCRIPTION
RESISTOR
Part Field 1
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A2
+Q2
FOOTPRINT
unknown
PARTTYPE
-include
+NPN_TRANSISTOR
DESCRIPTION
-include
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
@@ -465,13 +465,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RE1
+C1
FOOTPRINT
unknown
PARTTYPE
-100
+2.2uF
DESCRIPTION
-RESISTOR
+CAPACITOR
Part Field 1
*
Part Field 2
@@ -523,13 +523,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Q1
+A3
FOOTPRINT
unknown
PARTTYPE
-NPN_TRANSISTOR
+.options TEMP=25
DESCRIPTION
-NPN_TRANSISTOR
+directive
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+A2
FOOTPRINT
unknown
PARTTYPE
-model
+include
DESCRIPTION
-model
+include
Part Field 1
*
Part Field 2
@@ -639,13 +639,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R2
+A1
FOOTPRINT
unknown
PARTTYPE
-2K
+model
DESCRIPTION
-RESISTOR
+model
Part Field 1
*
Part Field 2
@@ -697,13 +697,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-Vinput
+VCC
FOOTPRINT
none
PARTTYPE
-DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DC 15V
DESCRIPTION
-vsin
+VOLTAGE_SOURCE
Part Field 1
*
Part Field 2
@@ -755,13 +755,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+Vinput
FOOTPRINT
-unknown
+none
PARTTYPE
-28K
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
DESCRIPTION
-RESISTOR
+vsin
Part Field 1
*
Part Field 2
@@ -813,11 +813,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C2
+CE1
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+1pF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -871,11 +871,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE2
+Cout
FOOTPRINT
unknown
PARTTYPE
-1pF
+2.2uF
DESCRIPTION
CAPACITOR
Part Field 1
@@ -929,13 +929,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C1
+RL
FOOTPRINT
unknown
PARTTYPE
-2.2uF
+100K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -987,13 +987,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CE1
+RC2
FOOTPRINT
unknown
PARTTYPE
-1pF
+1K
DESCRIPTION
-CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1045,11 +1045,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R8
+RE1
FOOTPRINT
unknown
PARTTYPE
-1
+100
DESCRIPTION
RESISTOR
Part Field 1
@@ -1103,13 +1103,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-VCC
+R2
FOOTPRINT
-none
+unknown
PARTTYPE
-DC 15V
+2K
DESCRIPTION
-VOLTAGE_SOURCE
+RESISTOR
Part Field 1
*
Part Field 2
@@ -1161,11 +1161,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC2
+R1
FOOTPRINT
unknown
PARTTYPE
-1K
+28K
DESCRIPTION
RESISTOR
Part Field 1
@@ -1219,11 +1219,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RC1
+R5
FOOTPRINT
unknown
PARTTYPE
-3.3K
+10
DESCRIPTION
RESISTOR
Part Field 1
@@ -1277,13 +1277,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-RL
+Q1
FOOTPRINT
unknown
PARTTYPE
-100K
+NPN_TRANSISTOR
DESCRIPTION
-RESISTOR
+NPN_TRANSISTOR
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/cascade-output.net b/gnetlist/tests/common/outputs/protelII/cascade-output.net
index 05f7d23..c8c75b0 100644
--- a/gnetlist/tests/common/outputs/protelII/cascade-output.net
+++ b/gnetlist/tests/common/outputs/protelII/cascade-output.net
@@ -59,13 +59,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-AMP1
+T1
FOOTPRINT
none
PARTTYPE
-cascade-amp
+cascade-transformer
DESCRIPTION
-cascade-amp
+cascade-transformer
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-SOURCE
+MX1
FOOTPRINT
none
PARTTYPE
-cascade-source
+cascade-mixer
DESCRIPTION
-cascade-source
+cascade-mixer
Part Field 1
*
Part Field 2
@@ -175,13 +175,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-DEFAULTS
+FL1
FOOTPRINT
-unknown
+none
PARTTYPE
-cascade-defaults-top
+cascade-filter
DESCRIPTION
-cascade-defaults-top
+cascade-filter
Part Field 1
*
Part Field 2
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-MX1
+DEF1
FOOTPRINT
none
PARTTYPE
-cascade-mixer
+cascade-defaults
DESCRIPTION
-cascade-mixer
+cascade-defaults
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-DEF1
+AMP1
FOOTPRINT
none
PARTTYPE
-cascade-defaults
+cascade-amp
DESCRIPTION
-cascade-defaults
+cascade-amp
Part Field 1
*
Part Field 2
@@ -349,13 +349,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-T1
+SOURCE
FOOTPRINT
none
PARTTYPE
-cascade-transformer
+cascade-source
DESCRIPTION
-cascade-transformer
+cascade-source
Part Field 1
*
Part Field 2
@@ -407,13 +407,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-FL1
+DEFAULTS
FOOTPRINT
-none
+unknown
PARTTYPE
-cascade-filter
+cascade-defaults-top
DESCRIPTION
-cascade-filter
+cascade-defaults-top
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/multiequal-output.net b/gnetlist/tests/common/outputs/protelII/multiequal-output.net
index 4614352..d577f9e 100644
--- a/gnetlist/tests/common/outputs/protelII/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/protelII/multiequal-output.net
@@ -59,13 +59,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-A1
+R1
FOOTPRINT
unknown
PARTTYPE
-abotol=1e-11
+20
DESCRIPTION
-options
+RESISTOR
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+A1
FOOTPRINT
unknown
PARTTYPE
-20
+abotol=1e-11
DESCRIPTION
-RESISTOR
+options
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/netattrib-output.net b/gnetlist/tests/common/outputs/protelII/netattrib-output.net
index d06c95d..518684b 100644
--- a/gnetlist/tests/common/outputs/protelII/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/protelII/netattrib-output.net
@@ -59,13 +59,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-U100
+U300
FOOTPRINT
DIP14
PARTTYPE
-7400
+7404
DESCRIPTION
-7400
+7404
Part Field 1
*
Part Field 2
@@ -117,7 +117,7 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-U300
+U200
FOOTPRINT
DIP14
PARTTYPE
@@ -175,13 +175,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-U200
+U100
FOOTPRINT
DIP14
PARTTYPE
-7404
+7400
DESCRIPTION
-7404
+7400
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/protelII/powersupply-output.net b/gnetlist/tests/common/outputs/protelII/powersupply-output.net
index 0dd831a..a376138 100644
--- a/gnetlist/tests/common/outputs/protelII/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/protelII/powersupply-output.net
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-F1
+U2
FOOTPRINT
unknown
PARTTYPE
-FUSE
+LM317
DESCRIPTION
-FUSE
+LM317
Part Field 1
*
Part Field 2
@@ -59,13 +59,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R2
+C4
FOOTPRINT
unknown
PARTTYPE
-220
+1uf
DESCRIPTION
-RESISTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CONN1
+C3
FOOTPRINT
unknown
PARTTYPE
-MAINS_CONNECTOR
+22uF
DESCRIPTION
-MAINS_CONNECTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,13 +175,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C4
+R1
FOOTPRINT
unknown
PARTTYPE
-1uf
+5k
DESCRIPTION
-POLARIZED_CAPACITOR
+VARIABLE_RESISTOR
Part Field 1
*
Part Field 2
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+C2
FOOTPRINT
unknown
PARTTYPE
-5k
+0.1uF
DESCRIPTION
-VARIABLE_RESISTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C3
+R2
FOOTPRINT
unknown
PARTTYPE
-22uF
+220
DESCRIPTION
-POLARIZED_CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -349,11 +349,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C2
+C1
FOOTPRINT
unknown
PARTTYPE
-0.1uF
+2200uF
DESCRIPTION
POLARIZED_CAPACITOR
Part Field 1
@@ -465,13 +465,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C1
+CONN1
FOOTPRINT
unknown
PARTTYPE
-2200uF
+MAINS_CONNECTOR
DESCRIPTION
-POLARIZED_CAPACITOR
+MAINS_CONNECTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-U2
+F1
FOOTPRINT
unknown
PARTTYPE
-LM317
+FUSE
DESCRIPTION
-LM317
+FUSE
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD-output.net
index e1bb285..0a05417 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/JD-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD-output.net
@@ -11,14 +11,14 @@
*^^^^^^^^ End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
*
*============== Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
Cm m 0 20p
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
index 647fbff..c0a926e 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
@@ -7,14 +7,14 @@
*********************************************************
.INCLUDE ./models/openIP_5.cir
*============== Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
Cm m 0 20p
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
index eec3dd1..6d91f4b 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
@@ -7,14 +7,14 @@
*********************************************************
.INCLUDE ./models/openIP_5.cir
*============== Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
Cm m 0 20p
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
+X1 i 0 LVH m p Vdd1 0 unknown_LVD
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
index cfaab32..70bef5b 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
@@ -11,14 +11,14 @@
*^^^^^^^^ End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
*
*============== Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
Cm m 0 20p
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 pch l=3u w=3u m=36
+X1 i 0 LVH m p Vdd1 0 unknown_LVD
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
index 3fa5a97..233a4d1 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
@@ -13,26 +13,26 @@
*^^^^^^^^ End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
*
*============== Begin SPICE netlist of main design ============
-Cout VColl2 Vout 2.2uF
-R5 Vin 1 10
+C2 2 Vbase2 2.2uF
R4 0 Vbase2 2.8K
+R3 Vbase2 Vcc 28K
+R8 Vcoll1 2 1
+CE2 0 Vem2 1pF
RE2 0 Vem2 100
+RC1 Vcoll1 Vcc 3.3K
Q2 VColl2 Vbase2 Vem2 2N3904
+C1 1 Vbase1 2.2uF
.options TEMP=25
-R3 Vbase2 Vcc 28K
.INCLUDE Simulation.cmd
-RE1 0 Vem1 100
-Q1 Vcoll1 Vbase1 Vem1 2N3904
-R2 0 Vbase1 2K
+VCC Vcc 0 DC 15V
Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K
-C2 2 Vbase2 2.2uF
-CE2 0 Vem2 1pF
-C1 1 Vbase1 2.2uF
CE1 0 Vem1 1pF
-R8 Vcoll1 2 1
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K
-RC1 Vcoll1 Vcc 3.3K
+Cout VColl2 Vout 2.2uF
RL 0 Vout 100K
+RC2 VColl2 Vcc 1K
+RE1 0 Vem1 100
+R2 0 Vbase1 2K
+R1 Vbase1 Vcc 28K
+R5 Vin 1 10
+Q1 Vcoll1 Vbase1 Vem1 2N3904
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
index 6b45461..2583d1d 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
@@ -7,26 +7,26 @@
*********************************************************
.INCLUDE ./models/2N3904.mod
*============== Begin SPICE netlist of main design ============
-Cout VColl2 Vout 2.2uF
-R5 Vin 1 10
+C2 2 Vbase2 2.2uF
R4 0 Vbase2 2.8K
+R3 Vbase2 Vcc 28K
+R8 Vcoll1 2 1
+CE2 0 Vem2 1pF
RE2 0 Vem2 100
+RC1 Vcoll1 Vcc 3.3K
Q2 VColl2 Vbase2 Vem2 2N3904
+C1 1 Vbase1 2.2uF
.options TEMP=25
-R3 Vbase2 Vcc 28K
.INCLUDE Simulation.cmd
-RE1 0 Vem1 100
-Q1 Vcoll1 Vbase1 Vem1 2N3904
-R2 0 Vbase1 2K
+VCC Vcc 0 DC 15V
Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K
-C2 2 Vbase2 2.2uF
-CE2 0 Vem2 1pF
-C1 1 Vbase1 2.2uF
CE1 0 Vem1 1pF
-R8 Vcoll1 2 1
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K
-RC1 Vcoll1 Vcc 3.3K
+Cout VColl2 Vout 2.2uF
RL 0 Vout 100K
+RC2 VColl2 Vcc 1K
+RE1 0 Vem1 100
+R2 0 Vbase1 2K
+R1 Vbase1 Vcc 28K
+R5 Vin 1 10
+Q1 Vcoll1 Vbase1 Vem1 2N3904
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net b/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
index 53dbc40..56db97e 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
@@ -7,11 +7,11 @@
*********************************************************
*============== Begin SPICE netlist of main design ============
AMP2 6 unconnected_pin-1 <No valid value attribute found>
+T1 5 6 <No valid value attribute found>
+MX1 4 5 unknown
+FL1 3 4 <No valid value attribute found>
+DEF1 2 3 unknown
AMP1 1 2 <No valid value attribute found>
SOURCE 1 <No valid value attribute found>
DEFAULTS unknown
-MX1 4 5 unknown
-DEF1 2 3 unknown
-T1 5 6 <No valid value attribute found>
-FL1 3 4 <No valid value attribute found>
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net b/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
index 13f8df9..6b94c5c 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
@@ -7,6 +7,6 @@
*********************************************************
*============== Begin SPICE netlist of main design ============
V1 1 0 DC 1V
-.OPTIONS abotol=1e-11
R1 0 1 20
+.OPTIONS abotol=1e-11
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
index 775b16e..c9982c8 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
@@ -7,7 +7,7 @@
*********************************************************
*============== Begin SPICE netlist of main design ============
F1 one unconnected_pin-3 <No valid value attribute found>
-U100 unconnected_pin-2 unconnected_pin-1 one unknown
U300 one 1 unknown
U200 one netattrib unknown
+U100 unconnected_pin-2 unconnected_pin-1 one unknown
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net b/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
index 8902cec..9d6040b 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
@@ -6,16 +6,16 @@
* Documentation at http://www.brorson.com/gEDA/SPICE/ *
*********************************************************
*============== Begin SPICE netlist of main design ============
-F1 two three <No valid value attribute found>
-R2 ten eleven 220
-CONN1 one five 0 <No valid value attribute found>
+U2 ten eleven eight unknown
C4 eleven nine 1uf
-R1 nine ten nine 5k
C3 ten nine 22uF
+R1 nine ten nine 5k
C2 eight nine 0.1uF
-S1 one two <No valid value attribute found>
+R2 ten eleven 220
C1 eight nine 2200uF
+S1 one two <No valid value attribute found>
+CONN1 one five 0 <No valid value attribute found>
T1 three five six seven <No valid value attribute found>
-U2 ten eleven eight unknown
+F1 two three <No valid value attribute found>
U1 eight nine seven six unknown
.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
index 21adb89..210c1f4 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
@@ -7,6 +7,6 @@
*********************************************************
*============== Begin SPICE netlist of main design ============
U100.3 SING_N SING_N SING_N unknown
-U100.2 SING_N SING_N SING_N unknown
U100.1 SING_N_2 unconnected_pin-1 SING_N_2 unknown
+U100.2 SING_N SING_N SING_N unknown
.end
diff --git a/gnetlist/tests/common/outputs/spice/JD-output.net b/gnetlist/tests/common/outputs/spice/JD-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include-output.net b/gnetlist/tests/common/outputs/spice/JD_Include-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD_Include-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort-output.net b/gnetlist/tests/common/outputs/spice/JD_Sort-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
index 9c485da..d5c82c3 100644
--- a/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
@@ -1,13 +1,13 @@
* Spice netlister for gnetlist
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p
A1 <No valid value attribute found>
-Rt p m 1k
-M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
-X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Cm m 0 20p
+Cp p 0 20p
Rlp p Vdd1 1meg
-Vdd Vdd1 0 DC 3.3V
Rlm m 0 500k
-Cp p 0 20p
+Vdd Vdd1 0 DC 3.3V
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Rt p m 1k
Rb 0 LVH 5.6k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
index a91f1a6..5e8b1d9 100644
--- a/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
@@ -1,25 +1,25 @@
* Spice netlister for gnetlist
-Cout VColl2 Vout 2.2uF
-R5 Vin 1 10
+C2 2 Vbase2 2.2uF
R4 0 Vbase2 2.8K
+R3 Vbase2 Vcc 28K
+R8 Vcoll1 2 1
+CE2 0 Vem2 1pF
RE2 0 Vem2 100
+RC1 Vcoll1 Vcc 3.3K
Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+C1 1 Vbase1 2.2uF
A3 .options TEMP=25
-R3 Vbase2 Vcc 28K
A2 <No valid value attribute found>
-RE1 0 Vem1 100
-Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
A1 <No valid value attribute found>
-R2 0 Vbase1 2K
+VCC Vcc 0 DC 15V
Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K
-C2 2 Vbase2 2.2uF
-CE2 0 Vem2 1pF
-C1 1 Vbase1 2.2uF
CE1 0 Vem1 1pF
-R8 Vcoll1 2 1
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K
-RC1 Vcoll1 Vcc 3.3K
+Cout VColl2 Vout 2.2uF
RL 0 Vout 100K
+RC2 VColl2 Vcc 1K
+RE1 0 Vem1 100
+R2 0 Vbase1 2K
+R1 Vbase1 Vcc 28K
+R5 Vin 1 10
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
index a91f1a6..5e8b1d9 100644
--- a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
@@ -1,25 +1,25 @@
* Spice netlister for gnetlist
-Cout VColl2 Vout 2.2uF
-R5 Vin 1 10
+C2 2 Vbase2 2.2uF
R4 0 Vbase2 2.8K
+R3 Vbase2 Vcc 28K
+R8 Vcoll1 2 1
+CE2 0 Vem2 1pF
RE2 0 Vem2 100
+RC1 Vcoll1 Vcc 3.3K
Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+C1 1 Vbase1 2.2uF
A3 .options TEMP=25
-R3 Vbase2 Vcc 28K
A2 <No valid value attribute found>
-RE1 0 Vem1 100
-Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
A1 <No valid value attribute found>
-R2 0 Vbase1 2K
+VCC Vcc 0 DC 15V
Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K
-C2 2 Vbase2 2.2uF
-CE2 0 Vem2 1pF
-C1 1 Vbase1 2.2uF
CE1 0 Vem1 1pF
-R8 Vcoll1 2 1
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K
-RC1 Vcoll1 Vcc 3.3K
+Cout VColl2 Vout 2.2uF
RL 0 Vout 100K
+RC2 VColl2 Vcc 1K
+RE1 0 Vem1 100
+R2 0 Vbase1 2K
+R1 Vbase1 Vcc 28K
+R5 Vin 1 10
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
index a91f1a6..5e8b1d9 100644
--- a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
@@ -1,25 +1,25 @@
* Spice netlister for gnetlist
-Cout VColl2 Vout 2.2uF
-R5 Vin 1 10
+C2 2 Vbase2 2.2uF
R4 0 Vbase2 2.8K
+R3 Vbase2 Vcc 28K
+R8 Vcoll1 2 1
+CE2 0 Vem2 1pF
RE2 0 Vem2 100
+RC1 Vcoll1 Vcc 3.3K
Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+C1 1 Vbase1 2.2uF
A3 .options TEMP=25
-R3 Vbase2 Vcc 28K
A2 <No valid value attribute found>
-RE1 0 Vem1 100
-Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
A1 <No valid value attribute found>
-R2 0 Vbase1 2K
+VCC Vcc 0 DC 15V
Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K
-C2 2 Vbase2 2.2uF
-CE2 0 Vem2 1pF
-C1 1 Vbase1 2.2uF
CE1 0 Vem1 1pF
-R8 Vcoll1 2 1
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K
-RC1 Vcoll1 Vcc 3.3K
+Cout VColl2 Vout 2.2uF
RL 0 Vout 100K
+RC2 VColl2 Vcc 1K
+RE1 0 Vem1 100
+R2 0 Vbase1 2K
+R1 Vbase1 Vcc 28K
+R5 Vin 1 10
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/cascade-output.net b/gnetlist/tests/common/outputs/spice/cascade-output.net
index a578dfa..f466b73 100644
--- a/gnetlist/tests/common/outputs/spice/cascade-output.net
+++ b/gnetlist/tests/common/outputs/spice/cascade-output.net
@@ -1,10 +1,10 @@
* Spice netlister for gnetlist
AMP2 6 unconnected_pin-1 <No valid value attribute found>
+T1 5 6 <No valid value attribute found>
+MX1 4 5 <No valid value attribute found>
+FL1 3 4 <No valid value attribute found>
+DEF1 2 3 <No valid value attribute found>
AMP1 1 2 <No valid value attribute found>
SOURCE 1 <No valid value attribute found>
DEFAULTS ERROR_INVALID_PIN <No valid value attribute found>
-MX1 4 5 <No valid value attribute found>
-DEF1 2 3 <No valid value attribute found>
-T1 5 6 <No valid value attribute found>
-FL1 3 4 <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/multiequal-output.net b/gnetlist/tests/common/outputs/spice/multiequal-output.net
index 0ed4801..1e4a9cc 100644
--- a/gnetlist/tests/common/outputs/spice/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/spice/multiequal-output.net
@@ -1,5 +1,5 @@
* Spice netlister for gnetlist
V1 1 0 DC 1V
-A1 abotol=1e-11
R1 0 1 20
+A1 abotol=1e-11
.END
diff --git a/gnetlist/tests/common/outputs/spice/netattrib-output.net b/gnetlist/tests/common/outputs/spice/netattrib-output.net
index f2d3500..1d4c88e 100644
--- a/gnetlist/tests/common/outputs/spice/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/spice/netattrib-output.net
@@ -1,6 +1,6 @@
* Spice netlister for gnetlist
F1 one unconnected_pin-3 <No valid value attribute found>
-U100 unconnected_pin-2 unconnected_pin-1 one ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
U300 one 1 ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
U200 one netattrib ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+U100 unconnected_pin-2 unconnected_pin-1 one ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/spice/powersupply-output.net b/gnetlist/tests/common/outputs/spice/powersupply-output.net
index f52e908..482a411 100644
--- a/gnetlist/tests/common/outputs/spice/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/spice/powersupply-output.net
@@ -1,14 +1,14 @@
* Spice netlister for gnetlist
-F1 two three <No valid value attribute found>
-R2 ten eleven 220
-CONN1 one five 0 <No valid value attribute found>
+U2 ten eleven eight <No valid value attribute found>
C4 eleven nine 1uf
-R1 nine ten nine 5k
C3 ten nine 22uF
+R1 nine ten nine 5k
C2 eight nine 0.1uF
-S1 one two <No valid value attribute found>
+R2 ten eleven 220
C1 eight nine 2200uF
+S1 one two <No valid value attribute found>
+CONN1 one five 0 <No valid value attribute found>
T1 three five six seven <No valid value attribute found>
-U2 ten eleven eight <No valid value attribute found>
+F1 two three <No valid value attribute found>
U1 eight nine seven six <No valid value attribute found>
.END
diff --git a/gnetlist/tests/common/outputs/systemc/JD-output.net b/gnetlist/tests/common/outputs/systemc/JD-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Include-output.net b/gnetlist/tests/common/outputs/systemc/JD_Include-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD_Include-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Sort-output.net b/gnetlist/tests/common/outputs/systemc/JD_Sort-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD_Sort-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/JD_nomunge-output.net b/gnetlist/tests/common/outputs/systemc/JD_nomunge-output.net
index 8c3783a..9bb9af3 100644
--- a/gnetlist/tests/common/outputs/systemc/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/systemc/JD_nomunge-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "vpulse.h"
-#include "CAPACITOR.h"
#include "model.h"
+#include "CAPACITOR.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "PMOS_TRANSISTOR.h"
-#include "LVD.h"
#include "RESISTOR.h"
#include "VOLTAGE_SOURCE.h"
+#include "vpulse.h"
#include "RESISTOR.h"
-#include "CAPACITOR.h"
#include "RESISTOR.h"
+#include "PMOS_TRANSISTOR.h"
+#include "LVD.h"
SC_MODULE (not found)
{
@@ -35,40 +35,55 @@ sc_signal<0> m;
/* Package instantiations */
-vpulse V1;
-CAPACITOR Cm;
model A1;
-RESISTOR Rt;
-PMOS_TRANSISTOR M1;
-LVD X1;
+CAPACITOR Cm;
+CAPACITOR Cp;
RESISTOR Rlp;
-VOLTAGE_SOURCE Vdd;
RESISTOR Rlm;
-CAPACITOR Cp;
+VOLTAGE_SOURCE Vdd;
+vpulse V1;
+RESISTOR Rt;
RESISTOR Rb;
+PMOS_TRANSISTOR M1;
+LVD X1;
SC_CTOR(not found):
- V1("V1"),
- Cm("Cm"),
A1("A1"),
- Rt("Rt"),
- M1("M1"),
- X1("X1"),
+ Cm("Cm"),
+ Cp("Cp"),
Rlp("Rlp"),
- Vdd("Vdd"),
Rlm("Rlm"),
- Cp("Cp"),
- Rb("Rb")
+ Vdd("Vdd"),
+ V1("V1"),
+ Rt("Rt"),
+ Rb("Rb"),
+ M1("M1"),
+ X1("X1")
{
- V1.1(i);
- V1.2(GND);
-
Cm.1(m);
Cm.2(GND);
+ Cp.1(p);
+ Cp.2(GND);
+
+ Rlp.2(Vdd1);
+ Rlp.1(p);
+
+ Rlm.2(GND);
+ Rlm.1(m);
+
+ Vdd.1(Vdd1);
+ Vdd.2(GND);
+
+ V1.1(i);
+ V1.2(GND);
+
Rt.2(m);
Rt.1(p);
+ Rb.2(LVH);
+ Rb.1(GND);
+
M1.S(Vdd1);
M1.B(Vdd1);
M1.D(LVH);
@@ -81,21 +96,6 @@ SC_CTOR(not found):
X1.2(GND);
X1.6(Vdd1);
X1.7(GND);
-
- Rlp.2(Vdd1);
- Rlp.1(p);
-
- Vdd.1(Vdd1);
- Vdd.2(GND);
-
- Rlm.2(GND);
- Rlm.1(m);
-
- Cp.1(p);
- Cp.2(GND);
-
- Rb.2(LVH);
- Rb.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/systemc/TwoStageAmp-output.net
index bc07ad1..1067781 100644
--- a/gnetlist/tests/common/outputs/systemc/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp-output.net
@@ -12,25 +12,25 @@
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
-#include "NPN_TRANSISTOR.h"
-#include "directive.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "include.h"
#include "RESISTOR.h"
#include "NPN_TRANSISTOR.h"
+#include "CAPACITOR.h"
+#include "directive.h"
+#include "include.h"
#include "model.h"
-#include "RESISTOR.h"
+#include "VOLTAGE_SOURCE.h"
#include "vsin.h"
-#include "RESISTOR.h"
-#include "CAPACITOR.h"
-#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "VOLTAGE_SOURCE.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "NPN_TRANSISTOR.h"
SC_MODULE (not found)
{
@@ -53,116 +53,116 @@ sc_signal<0> Vcoll1;
/* Package instantiations */
-CAPACITOR Cout;
-RESISTOR R5;
+CAPACITOR C2;
RESISTOR R4;
+RESISTOR R3;
+RESISTOR R8;
+CAPACITOR CE2;
RESISTOR RE2;
+RESISTOR RC1;
NPN_TRANSISTOR Q2;
+CAPACITOR C1;
directive A3;
-RESISTOR R3;
include A2;
-RESISTOR RE1;
-NPN_TRANSISTOR Q1;
model A1;
-RESISTOR R2;
+VOLTAGE_SOURCE VCC;
vsin Vinput;
-RESISTOR R1;
-CAPACITOR C2;
-CAPACITOR CE2;
-CAPACITOR C1;
CAPACITOR CE1;
-RESISTOR R8;
-VOLTAGE_SOURCE VCC;
-RESISTOR RC2;
-RESISTOR RC1;
+CAPACITOR Cout;
RESISTOR RL;
+RESISTOR RC2;
+RESISTOR RE1;
+RESISTOR R2;
+RESISTOR R1;
+RESISTOR R5;
+NPN_TRANSISTOR Q1;
SC_CTOR(not found):
- Cout("Cout"),
- R5("R5"),
+ C2("C2"),
R4("R4"),
+ R3("R3"),
+ R8("R8"),
+ CE2("CE2"),
RE2("RE2"),
+ RC1("RC1"),
Q2("Q2"),
+ C1("C1"),
A3("A3"),
- R3("R3"),
A2("A2"),
- RE1("RE1"),
- Q1("Q1"),
A1("A1"),
- R2("R2"),
+ VCC("VCC"),
Vinput("Vinput"),
- R1("R1"),
- C2("C2"),
- CE2("CE2"),
- C1("C1"),
CE1("CE1"),
- R8("R8"),
- VCC("VCC"),
+ Cout("Cout"),
+ RL("RL"),
RC2("RC2"),
- RC1("RC1"),
- RL("RL")
+ RE1("RE1"),
+ R2("R2"),
+ R1("R1"),
+ R5("R5"),
+ Q1("Q1")
{
- Cout.1(VColl2);
- Cout.2(Vout);
-
- R5.2(unnamed_net1);
- R5.1(Vin);
+ C2.1(unnamed_net2);
+ C2.2(Vbase2);
R4.2(Vbase2);
R4.1(GND);
+ R3.2(Vcc);
+ R3.1(Vbase2);
+
+ R8.2(unnamed_net2);
+ R8.1(Vcoll1);
+
+ CE2.1(GND);
+ CE2.2(Vem2);
+
RE2.2(Vem2);
RE2.1(GND);
+ RC1.2(Vcc);
+ RC1.1(Vcoll1);
+
Q2.3(VColl2);
Q2.1(Vem2);
Q2.2(Vbase2);
- R3.2(Vcc);
- R3.1(Vbase2);
-
- RE1.2(Vem1);
- RE1.1(GND);
-
- Q1.3(Vcoll1);
- Q1.1(Vem1);
- Q1.2(Vbase1);
+ C1.1(unnamed_net1);
+ C1.2(Vbase1);
- R2.2(Vbase1);
- R2.1(GND);
+ VCC.1(Vcc);
+ VCC.2(GND);
Vinput.1(Vin);
Vinput.2(GND);
- R1.2(Vcc);
- R1.1(Vbase1);
-
- C2.1(unnamed_net2);
- C2.2(Vbase2);
-
- CE2.1(GND);
- CE2.2(Vem2);
-
- C1.1(unnamed_net1);
- C1.2(Vbase1);
-
CE1.1(GND);
CE1.2(Vem1);
- R8.2(unnamed_net2);
- R8.1(Vcoll1);
+ Cout.1(VColl2);
+ Cout.2(Vout);
- VCC.1(Vcc);
- VCC.2(GND);
+ RL.2(Vout);
+ RL.1(GND);
RC2.2(Vcc);
RC2.1(VColl2);
- RC1.2(Vcc);
- RC1.1(Vcoll1);
+ RE1.2(Vem1);
+ RE1.1(GND);
- RL.2(Vout);
- RL.1(GND);
+ R2.2(Vbase1);
+ R2.1(GND);
+
+ R1.2(Vcc);
+ R1.1(Vbase1);
+
+ R5.2(unnamed_net1);
+ R5.1(Vin);
+
+ Q1.3(Vcoll1);
+ Q1.1(Vem1);
+ Q1.2(Vbase1);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include-output.net
index bc07ad1..1067781 100644
--- a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include-output.net
@@ -12,25 +12,25 @@
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
-#include "NPN_TRANSISTOR.h"
-#include "directive.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "include.h"
#include "RESISTOR.h"
#include "NPN_TRANSISTOR.h"
+#include "CAPACITOR.h"
+#include "directive.h"
+#include "include.h"
#include "model.h"
-#include "RESISTOR.h"
+#include "VOLTAGE_SOURCE.h"
#include "vsin.h"
-#include "RESISTOR.h"
-#include "CAPACITOR.h"
-#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "VOLTAGE_SOURCE.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "NPN_TRANSISTOR.h"
SC_MODULE (not found)
{
@@ -53,116 +53,116 @@ sc_signal<0> Vcoll1;
/* Package instantiations */
-CAPACITOR Cout;
-RESISTOR R5;
+CAPACITOR C2;
RESISTOR R4;
+RESISTOR R3;
+RESISTOR R8;
+CAPACITOR CE2;
RESISTOR RE2;
+RESISTOR RC1;
NPN_TRANSISTOR Q2;
+CAPACITOR C1;
directive A3;
-RESISTOR R3;
include A2;
-RESISTOR RE1;
-NPN_TRANSISTOR Q1;
model A1;
-RESISTOR R2;
+VOLTAGE_SOURCE VCC;
vsin Vinput;
-RESISTOR R1;
-CAPACITOR C2;
-CAPACITOR CE2;
-CAPACITOR C1;
CAPACITOR CE1;
-RESISTOR R8;
-VOLTAGE_SOURCE VCC;
-RESISTOR RC2;
-RESISTOR RC1;
+CAPACITOR Cout;
RESISTOR RL;
+RESISTOR RC2;
+RESISTOR RE1;
+RESISTOR R2;
+RESISTOR R1;
+RESISTOR R5;
+NPN_TRANSISTOR Q1;
SC_CTOR(not found):
- Cout("Cout"),
- R5("R5"),
+ C2("C2"),
R4("R4"),
+ R3("R3"),
+ R8("R8"),
+ CE2("CE2"),
RE2("RE2"),
+ RC1("RC1"),
Q2("Q2"),
+ C1("C1"),
A3("A3"),
- R3("R3"),
A2("A2"),
- RE1("RE1"),
- Q1("Q1"),
A1("A1"),
- R2("R2"),
+ VCC("VCC"),
Vinput("Vinput"),
- R1("R1"),
- C2("C2"),
- CE2("CE2"),
- C1("C1"),
CE1("CE1"),
- R8("R8"),
- VCC("VCC"),
+ Cout("Cout"),
+ RL("RL"),
RC2("RC2"),
- RC1("RC1"),
- RL("RL")
+ RE1("RE1"),
+ R2("R2"),
+ R1("R1"),
+ R5("R5"),
+ Q1("Q1")
{
- Cout.1(VColl2);
- Cout.2(Vout);
-
- R5.2(unnamed_net1);
- R5.1(Vin);
+ C2.1(unnamed_net2);
+ C2.2(Vbase2);
R4.2(Vbase2);
R4.1(GND);
+ R3.2(Vcc);
+ R3.1(Vbase2);
+
+ R8.2(unnamed_net2);
+ R8.1(Vcoll1);
+
+ CE2.1(GND);
+ CE2.2(Vem2);
+
RE2.2(Vem2);
RE2.1(GND);
+ RC1.2(Vcc);
+ RC1.1(Vcoll1);
+
Q2.3(VColl2);
Q2.1(Vem2);
Q2.2(Vbase2);
- R3.2(Vcc);
- R3.1(Vbase2);
-
- RE1.2(Vem1);
- RE1.1(GND);
-
- Q1.3(Vcoll1);
- Q1.1(Vem1);
- Q1.2(Vbase1);
+ C1.1(unnamed_net1);
+ C1.2(Vbase1);
- R2.2(Vbase1);
- R2.1(GND);
+ VCC.1(Vcc);
+ VCC.2(GND);
Vinput.1(Vin);
Vinput.2(GND);
- R1.2(Vcc);
- R1.1(Vbase1);
-
- C2.1(unnamed_net2);
- C2.2(Vbase2);
-
- CE2.1(GND);
- CE2.2(Vem2);
-
- C1.1(unnamed_net1);
- C1.2(Vbase1);
-
CE1.1(GND);
CE1.2(Vem1);
- R8.2(unnamed_net2);
- R8.1(Vcoll1);
+ Cout.1(VColl2);
+ Cout.2(Vout);
- VCC.1(Vcc);
- VCC.2(GND);
+ RL.2(Vout);
+ RL.1(GND);
RC2.2(Vcc);
RC2.1(VColl2);
- RC1.2(Vcc);
- RC1.1(Vcoll1);
+ RE1.2(Vem1);
+ RE1.1(GND);
- RL.2(Vout);
- RL.1(GND);
+ R2.2(Vbase1);
+ R2.1(GND);
+
+ R1.2(Vcc);
+ R1.1(Vbase1);
+
+ R5.2(unnamed_net1);
+ R5.1(Vin);
+
+ Q1.3(Vcoll1);
+ Q1.1(Vem1);
+ Q1.2(Vbase1);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort-output.net
index bc07ad1..1067781 100644
--- a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort-output.net
@@ -12,25 +12,25 @@
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
-#include "NPN_TRANSISTOR.h"
-#include "directive.h"
+#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "include.h"
#include "RESISTOR.h"
#include "NPN_TRANSISTOR.h"
+#include "CAPACITOR.h"
+#include "directive.h"
+#include "include.h"
#include "model.h"
-#include "RESISTOR.h"
+#include "VOLTAGE_SOURCE.h"
#include "vsin.h"
-#include "RESISTOR.h"
-#include "CAPACITOR.h"
-#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "CAPACITOR.h"
#include "RESISTOR.h"
-#include "VOLTAGE_SOURCE.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "RESISTOR.h"
+#include "NPN_TRANSISTOR.h"
SC_MODULE (not found)
{
@@ -53,116 +53,116 @@ sc_signal<0> Vcoll1;
/* Package instantiations */
-CAPACITOR Cout;
-RESISTOR R5;
+CAPACITOR C2;
RESISTOR R4;
+RESISTOR R3;
+RESISTOR R8;
+CAPACITOR CE2;
RESISTOR RE2;
+RESISTOR RC1;
NPN_TRANSISTOR Q2;
+CAPACITOR C1;
directive A3;
-RESISTOR R3;
include A2;
-RESISTOR RE1;
-NPN_TRANSISTOR Q1;
model A1;
-RESISTOR R2;
+VOLTAGE_SOURCE VCC;
vsin Vinput;
-RESISTOR R1;
-CAPACITOR C2;
-CAPACITOR CE2;
-CAPACITOR C1;
CAPACITOR CE1;
-RESISTOR R8;
-VOLTAGE_SOURCE VCC;
-RESISTOR RC2;
-RESISTOR RC1;
+CAPACITOR Cout;
RESISTOR RL;
+RESISTOR RC2;
+RESISTOR RE1;
+RESISTOR R2;
+RESISTOR R1;
+RESISTOR R5;
+NPN_TRANSISTOR Q1;
SC_CTOR(not found):
- Cout("Cout"),
- R5("R5"),
+ C2("C2"),
R4("R4"),
+ R3("R3"),
+ R8("R8"),
+ CE2("CE2"),
RE2("RE2"),
+ RC1("RC1"),
Q2("Q2"),
+ C1("C1"),
A3("A3"),
- R3("R3"),
A2("A2"),
- RE1("RE1"),
- Q1("Q1"),
A1("A1"),
- R2("R2"),
+ VCC("VCC"),
Vinput("Vinput"),
- R1("R1"),
- C2("C2"),
- CE2("CE2"),
- C1("C1"),
CE1("CE1"),
- R8("R8"),
- VCC("VCC"),
+ Cout("Cout"),
+ RL("RL"),
RC2("RC2"),
- RC1("RC1"),
- RL("RL")
+ RE1("RE1"),
+ R2("R2"),
+ R1("R1"),
+ R5("R5"),
+ Q1("Q1")
{
- Cout.1(VColl2);
- Cout.2(Vout);
-
- R5.2(unnamed_net1);
- R5.1(Vin);
+ C2.1(unnamed_net2);
+ C2.2(Vbase2);
R4.2(Vbase2);
R4.1(GND);
+ R3.2(Vcc);
+ R3.1(Vbase2);
+
+ R8.2(unnamed_net2);
+ R8.1(Vcoll1);
+
+ CE2.1(GND);
+ CE2.2(Vem2);
+
RE2.2(Vem2);
RE2.1(GND);
+ RC1.2(Vcc);
+ RC1.1(Vcoll1);
+
Q2.3(VColl2);
Q2.1(Vem2);
Q2.2(Vbase2);
- R3.2(Vcc);
- R3.1(Vbase2);
-
- RE1.2(Vem1);
- RE1.1(GND);
-
- Q1.3(Vcoll1);
- Q1.1(Vem1);
- Q1.2(Vbase1);
+ C1.1(unnamed_net1);
+ C1.2(Vbase1);
- R2.2(Vbase1);
- R2.1(GND);
+ VCC.1(Vcc);
+ VCC.2(GND);
Vinput.1(Vin);
Vinput.2(GND);
- R1.2(Vcc);
- R1.1(Vbase1);
-
- C2.1(unnamed_net2);
- C2.2(Vbase2);
-
- CE2.1(GND);
- CE2.2(Vem2);
-
- C1.1(unnamed_net1);
- C1.2(Vbase1);
-
CE1.1(GND);
CE1.2(Vem1);
- R8.2(unnamed_net2);
- R8.1(Vcoll1);
+ Cout.1(VColl2);
+ Cout.2(Vout);
- VCC.1(Vcc);
- VCC.2(GND);
+ RL.2(Vout);
+ RL.1(GND);
RC2.2(Vcc);
RC2.1(VColl2);
- RC1.2(Vcc);
- RC1.1(Vcoll1);
+ RE1.2(Vem1);
+ RE1.1(GND);
- RL.2(Vout);
- RL.1(GND);
+ R2.2(Vbase1);
+ R2.1(GND);
+
+ R1.2(Vcc);
+ R1.1(Vbase1);
+
+ R5.2(unnamed_net1);
+ R5.1(Vin);
+
+ Q1.3(Vcoll1);
+ Q1.1(Vem1);
+ Q1.2(Vbase1);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/cascade-output.net b/gnetlist/tests/common/outputs/systemc/cascade-output.net
index 14254df..c5df0e6 100644
--- a/gnetlist/tests/common/outputs/systemc/cascade-output.net
+++ b/gnetlist/tests/common/outputs/systemc/cascade-output.net
@@ -9,13 +9,13 @@
#include "systemc.h"
#include "cascade-amp.h"
+#include "cascade-transformer.h"
+#include "cascade-mixer.h"
+#include "cascade-filter.h"
+#include "cascade-defaults.h"
#include "cascade-amp.h"
#include "cascade-source.h"
#include "cascade-defaults-top.h"
-#include "cascade-mixer.h"
-#include "cascade-defaults.h"
-#include "cascade-transformer.h"
-#include "cascade-filter.h"
SC_MODULE (not found)
{
@@ -34,44 +34,44 @@ sc_signal<0> GND;
/* Package instantiations */
cascade-amp AMP2;
+cascade-transformer T1;
+cascade-mixer MX1;
+cascade-filter FL1;
+cascade-defaults DEF1;
cascade-amp AMP1;
cascade-source SOURCE;
cascade-defaults-top DEFAULTS;
-cascade-mixer MX1;
-cascade-defaults DEF1;
-cascade-transformer T1;
-cascade-filter FL1;
SC_CTOR(not found):
AMP2("AMP2"),
- AMP1("AMP1"),
- SOURCE("SOURCE"),
- DEFAULTS("DEFAULTS"),
+ T1("T1"),
MX1("MX1"),
+ FL1("FL1"),
DEF1("DEF1"),
- T1("T1"),
- FL1("FL1")
+ AMP1("AMP1"),
+ SOURCE("SOURCE"),
+ DEFAULTS("DEFAULTS")
{
AMP2.1(unnamed_net6);
- AMP1.1(unnamed_net1);
- AMP1.2(unnamed_net2);
-
- SOURCE.1(unnamed_net1);
-
- DEFAULTS.1(GND);
+ T1.1(unnamed_net5);
+ T1.2(unnamed_net6);
MX1.1(unnamed_net4);
MX1.2(unnamed_net5);
+ FL1.1(unnamed_net3);
+ FL1.2(unnamed_net4);
+
DEF1.1(unnamed_net2);
DEF1.2(unnamed_net3);
- T1.1(unnamed_net5);
- T1.2(unnamed_net6);
+ AMP1.1(unnamed_net1);
+ AMP1.2(unnamed_net2);
- FL1.1(unnamed_net3);
- FL1.2(unnamed_net4);
+ SOURCE.1(unnamed_net1);
+
+ DEFAULTS.1(GND);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/multiequal-output.net b/gnetlist/tests/common/outputs/systemc/multiequal-output.net
index c65bb1a..cc69709 100644
--- a/gnetlist/tests/common/outputs/systemc/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/systemc/multiequal-output.net
@@ -9,8 +9,8 @@
#include "systemc.h"
#include "VOLTAGE_SOURCE.h"
-#include "options.h"
#include "RESISTOR.h"
+#include "options.h"
SC_MODULE (not found)
{
@@ -24,13 +24,13 @@ sc_signal<0> unnamed_net1;
/* Package instantiations */
VOLTAGE_SOURCE V1;
-options A1;
RESISTOR R1;
+options A1;
SC_CTOR(not found):
V1("V1"),
- A1("A1"),
- R1("R1")
+ R1("R1"),
+ A1("A1")
{
V1.1(unnamed_net1);
V1.2(GND);
diff --git a/gnetlist/tests/common/outputs/systemc/netattrib-output.net b/gnetlist/tests/common/outputs/systemc/netattrib-output.net
index 295e05c..d014a09 100644
--- a/gnetlist/tests/common/outputs/systemc/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/systemc/netattrib-output.net
@@ -9,9 +9,9 @@
#include "systemc.h"
#include "FUSE.h"
-#include "7400.h"
#include "7404.h"
#include "7404.h"
+#include "7400.h"
SC_MODULE (not found)
{
@@ -28,23 +28,18 @@ sc_signal<0> one;
/* Package instantiations */
FUSE F1;
-7400 U100;
7404 U300;
7404 U200;
+7400 U100;
SC_CTOR(not found):
F1("F1"),
- U100("U100"),
U300("U300"),
- U200("U200")
+ U200("U200"),
+ U100("U100")
{
F1.1(one);
- U100.3(one);
- U100.14(Vcc);
- U100.7(GND);
- U100.5(netattrib);
-
U300.1(one);
U300.2(unnamed_net1);
U300.7(GND);
@@ -54,6 +49,11 @@ SC_CTOR(not found):
U200.2(netattrib);
U200.7(GND);
U200.14(Vcc);
+
+ U100.3(one);
+ U100.14(Vcc);
+ U100.7(GND);
+ U100.5(netattrib);
}
};
diff --git a/gnetlist/tests/common/outputs/systemc/powersupply-output.net b/gnetlist/tests/common/outputs/systemc/powersupply-output.net
index a12b8de..8b53306 100644
--- a/gnetlist/tests/common/outputs/systemc/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/systemc/powersupply-output.net
@@ -8,17 +8,17 @@
/* Author.....Jaume Masip */
#include "systemc.h"
-#include "FUSE.h"
-#include "RESISTOR.h"
-#include "MAINS_CONNECTOR.h"
+#include "LM317.h"
+#include "POLARIZED_CAPACITOR.h"
#include "POLARIZED_CAPACITOR.h"
#include "VARIABLE_RESISTOR.h"
#include "POLARIZED_CAPACITOR.h"
+#include "RESISTOR.h"
#include "POLARIZED_CAPACITOR.h"
#include "SPST.h"
-#include "POLARIZED_CAPACITOR.h"
+#include "MAINS_CONNECTOR.h"
#include "transformer.h"
-#include "LM317.h"
+#include "FUSE.h"
#include "DIODE-BRIDGE.h"
SC_MODULE (not found)
@@ -41,70 +41,70 @@ sc_signal<0> eight;
/* Package instantiations */
-FUSE F1;
-RESISTOR R2;
-MAINS_CONNECTOR CONN1;
+LM317 U2;
POLARIZED_CAPACITOR C4;
-VARIABLE_RESISTOR R1;
POLARIZED_CAPACITOR C3;
+VARIABLE_RESISTOR R1;
POLARIZED_CAPACITOR C2;
-SPST S1;
+RESISTOR R2;
POLARIZED_CAPACITOR C1;
+SPST S1;
+MAINS_CONNECTOR CONN1;
transformer T1;
-LM317 U2;
+FUSE F1;
DIODE-BRIDGE U1;
SC_CTOR(not found):
- F1("F1"),
- R2("R2"),
- CONN1("CONN1"),
+ U2("U2"),
C4("C4"),
- R1("R1"),
C3("C3"),
+ R1("R1"),
C2("C2"),
- S1("S1"),
+ R2("R2"),
C1("C1"),
+ S1("S1"),
+ CONN1("CONN1"),
T1("T1"),
- U2("U2"),
+ F1("F1"),
U1("U1")
{
- F1.1(two);
- F1.2(three);
-
- R2.2(eleven);
- R2.1(ten);
-
- CONN1.1(one);
- CONN1.2(five);
- CONN1.3(GND);
+ U2.2(eleven);
+ U2.3(eight);
+ U2.1(ten);
C4.1(eleven);
C4.2(nine);
+ C3.1(ten);
+ C3.2(nine);
+
R1.3(nine);
R1.2(ten);
R1.1(nine);
- C3.1(ten);
- C3.2(nine);
-
C2.1(eight);
C2.2(nine);
- S1.2(two);
- S1.1(one);
+ R2.2(eleven);
+ R2.1(ten);
C1.1(eight);
C1.2(nine);
+ S1.2(two);
+ S1.1(one);
+
+ CONN1.1(one);
+ CONN1.2(five);
+ CONN1.3(GND);
+
T1.2(five);
T1.1(three);
T1.4(seven);
T1.3(six);
- U2.2(eleven);
- U2.3(eight);
- U2.1(ten);
+ F1.1(two);
+ F1.2(three);
U1.1(eight);
U1.2(nine);
diff --git a/gnetlist/tests/common/outputs/tango/JD-output.net b/gnetlist/tests/common/outputs/tango/JD-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include-output.net b/gnetlist/tests/common/outputs/tango/JD_Include-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD_Include-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort-output.net b/gnetlist/tests/common/outputs/tango/JD_Sort-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
index e4c961a..246256d 100644
--- a/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
@@ -1,18 +1,4 @@
[
-V1
-none
-vpulse
-pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-
-]
-[
-Cm
-PATTERN
-CAPACITOR
-20p
-
-]
-[
A1
PATTERN
model
@@ -20,31 +6,31 @@ model
]
[
-Rt
+Cm
PATTERN
-RESISTOR
-1k
+CAPACITOR
+20p
]
[
-M1
+Cp
PATTERN
-PMOS_TRANSISTOR
-
+CAPACITOR
+20p
]
[
-X1
+Rlp
PATTERN
-LVD
-
+RESISTOR
+1meg
]
[
-Rlp
+Rlm
PATTERN
RESISTOR
-1meg
+500k
]
[
@@ -55,17 +41,17 @@ DC 3.3V
]
[
-Rlm
-PATTERN
-RESISTOR
-500k
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
]
[
-Cp
+Rt
PATTERN
-CAPACITOR
-20p
+RESISTOR
+1k
]
[
@@ -75,6 +61,20 @@ RESISTOR
5.6k
]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
(
Vdd1
Rlp-2
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
index 42312fd..29bab15 100644
--- a/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
@@ -1,70 +1,77 @@
[
-Cout
+C2
PATTERN
CAPACITOR
2.2uF
]
[
-R5
+R4
PATTERN
RESISTOR
-10
+2.8K
]
[
-R4
+R3
PATTERN
RESISTOR
-2.8K
+28K
]
[
-RE2
+R8
PATTERN
RESISTOR
-100
+1
]
[
-Q2
+CE2
PATTERN
-NPN_TRANSISTOR
-
+CAPACITOR
+1pF
]
[
-A3
+RE2
PATTERN
-directive
-.options TEMP=25
+RESISTOR
+100
]
[
-R3
+RC1
PATTERN
RESISTOR
-28K
+3.3K
]
[
-A2
+Q2
PATTERN
-include
+NPN_TRANSISTOR
]
[
-RE1
+C1
PATTERN
-RESISTOR
-100
+CAPACITOR
+2.2uF
]
[
-Q1
+A3
PATTERN
-NPN_TRANSISTOR
+directive
+.options TEMP=25
+
+]
+[
+A2
+PATTERN
+include
]
@@ -76,10 +83,10 @@ model
]
[
-R2
-PATTERN
-RESISTOR
-2K
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
]
[
@@ -90,73 +97,66 @@ DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
]
[
-R1
+CE1
PATTERN
-RESISTOR
-28K
+CAPACITOR
+1pF
]
[
-C2
+Cout
PATTERN
CAPACITOR
2.2uF
]
[
-CE2
+RL
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100K
]
[
-C1
+RC2
PATTERN
-CAPACITOR
-2.2uF
+RESISTOR
+1K
]
[
-CE1
+RE1
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100
]
[
-R8
+R2
PATTERN
RESISTOR
-1
-
-]
-[
-VCC
-none
-VOLTAGE_SOURCE
-DC 15V
+2K
]
[
-RC2
+R1
PATTERN
RESISTOR
-1K
+28K
]
[
-RC1
+R5
PATTERN
RESISTOR
-3.3K
+10
]
[
-RL
+Q1
PATTERN
-RESISTOR
-100K
+NPN_TRANSISTOR
+
]
(
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
index 42312fd..29bab15 100644
--- a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
@@ -1,70 +1,77 @@
[
-Cout
+C2
PATTERN
CAPACITOR
2.2uF
]
[
-R5
+R4
PATTERN
RESISTOR
-10
+2.8K
]
[
-R4
+R3
PATTERN
RESISTOR
-2.8K
+28K
]
[
-RE2
+R8
PATTERN
RESISTOR
-100
+1
]
[
-Q2
+CE2
PATTERN
-NPN_TRANSISTOR
-
+CAPACITOR
+1pF
]
[
-A3
+RE2
PATTERN
-directive
-.options TEMP=25
+RESISTOR
+100
]
[
-R3
+RC1
PATTERN
RESISTOR
-28K
+3.3K
]
[
-A2
+Q2
PATTERN
-include
+NPN_TRANSISTOR
]
[
-RE1
+C1
PATTERN
-RESISTOR
-100
+CAPACITOR
+2.2uF
]
[
-Q1
+A3
PATTERN
-NPN_TRANSISTOR
+directive
+.options TEMP=25
+
+]
+[
+A2
+PATTERN
+include
]
@@ -76,10 +83,10 @@ model
]
[
-R2
-PATTERN
-RESISTOR
-2K
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
]
[
@@ -90,73 +97,66 @@ DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
]
[
-R1
+CE1
PATTERN
-RESISTOR
-28K
+CAPACITOR
+1pF
]
[
-C2
+Cout
PATTERN
CAPACITOR
2.2uF
]
[
-CE2
+RL
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100K
]
[
-C1
+RC2
PATTERN
-CAPACITOR
-2.2uF
+RESISTOR
+1K
]
[
-CE1
+RE1
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100
]
[
-R8
+R2
PATTERN
RESISTOR
-1
-
-]
-[
-VCC
-none
-VOLTAGE_SOURCE
-DC 15V
+2K
]
[
-RC2
+R1
PATTERN
RESISTOR
-1K
+28K
]
[
-RC1
+R5
PATTERN
RESISTOR
-3.3K
+10
]
[
-RL
+Q1
PATTERN
-RESISTOR
-100K
+NPN_TRANSISTOR
+
]
(
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
index 42312fd..29bab15 100644
--- a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
@@ -1,70 +1,77 @@
[
-Cout
+C2
PATTERN
CAPACITOR
2.2uF
]
[
-R5
+R4
PATTERN
RESISTOR
-10
+2.8K
]
[
-R4
+R3
PATTERN
RESISTOR
-2.8K
+28K
]
[
-RE2
+R8
PATTERN
RESISTOR
-100
+1
]
[
-Q2
+CE2
PATTERN
-NPN_TRANSISTOR
-
+CAPACITOR
+1pF
]
[
-A3
+RE2
PATTERN
-directive
-.options TEMP=25
+RESISTOR
+100
]
[
-R3
+RC1
PATTERN
RESISTOR
-28K
+3.3K
]
[
-A2
+Q2
PATTERN
-include
+NPN_TRANSISTOR
]
[
-RE1
+C1
PATTERN
-RESISTOR
-100
+CAPACITOR
+2.2uF
]
[
-Q1
+A3
PATTERN
-NPN_TRANSISTOR
+directive
+.options TEMP=25
+
+]
+[
+A2
+PATTERN
+include
]
@@ -76,10 +83,10 @@ model
]
[
-R2
-PATTERN
-RESISTOR
-2K
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
]
[
@@ -90,73 +97,66 @@ DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
]
[
-R1
+CE1
PATTERN
-RESISTOR
-28K
+CAPACITOR
+1pF
]
[
-C2
+Cout
PATTERN
CAPACITOR
2.2uF
]
[
-CE2
+RL
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100K
]
[
-C1
+RC2
PATTERN
-CAPACITOR
-2.2uF
+RESISTOR
+1K
]
[
-CE1
+RE1
PATTERN
-CAPACITOR
-1pF
+RESISTOR
+100
]
[
-R8
+R2
PATTERN
RESISTOR
-1
-
-]
-[
-VCC
-none
-VOLTAGE_SOURCE
-DC 15V
+2K
]
[
-RC2
+R1
PATTERN
RESISTOR
-1K
+28K
]
[
-RC1
+R5
PATTERN
RESISTOR
-3.3K
+10
]
[
-RL
+Q1
PATTERN
-RESISTOR
-100K
+NPN_TRANSISTOR
+
]
(
diff --git a/gnetlist/tests/common/outputs/tango/cascade-output.net b/gnetlist/tests/common/outputs/tango/cascade-output.net
index f21920b..07552b1 100644
--- a/gnetlist/tests/common/outputs/tango/cascade-output.net
+++ b/gnetlist/tests/common/outputs/tango/cascade-output.net
@@ -6,51 +6,51 @@ cascade-amp
]
[
-AMP1
+T1
none
-cascade-amp
+cascade-transformer
]
[
-SOURCE
+MX1
none
-cascade-source
+cascade-mixer
]
[
-DEFAULTS
-PATTERN
-cascade-defaults-top
+FL1
+none
+cascade-filter
]
[
-MX1
+DEF1
none
-cascade-mixer
+cascade-defaults
]
[
-DEF1
+AMP1
none
-cascade-defaults
+cascade-amp
]
[
-T1
+SOURCE
none
-cascade-transformer
+cascade-source
]
[
-FL1
-none
-cascade-filter
+DEFAULTS
+PATTERN
+cascade-defaults-top
]
diff --git a/gnetlist/tests/common/outputs/tango/multiequal-output.net b/gnetlist/tests/common/outputs/tango/multiequal-output.net
index 96b14bc..dc357ef 100644
--- a/gnetlist/tests/common/outputs/tango/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/tango/multiequal-output.net
@@ -6,17 +6,17 @@ DC 1V
]
[
-A1
+R1
PATTERN
-options
-abotol=1e-11
+RESISTOR
+20
]
[
-R1
+A1
PATTERN
-RESISTOR
-20
+options
+abotol=1e-11
]
(
diff --git a/gnetlist/tests/common/outputs/tango/netattrib-output.net b/gnetlist/tests/common/outputs/tango/netattrib-output.net
index 6ef1d9d..a859cef 100644
--- a/gnetlist/tests/common/outputs/tango/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/tango/netattrib-output.net
@@ -6,23 +6,23 @@ FUSE
]
[
-U100
+U300
DIP14
-7400
+7404
]
[
-U300
+U200
DIP14
7404
]
[
-U200
+U100
DIP14
-7404
+7400
]
diff --git a/gnetlist/tests/common/outputs/tango/powersupply-output.net b/gnetlist/tests/common/outputs/tango/powersupply-output.net
index 96576c4..56453f0 100644
--- a/gnetlist/tests/common/outputs/tango/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/tango/powersupply-output.net
@@ -1,29 +1,22 @@
[
-F1
+U2
PATTERN
-FUSE
-
+LM317
-]
-[
-R2
-PATTERN
-RESISTOR
-220
]
[
-CONN1
+C4
PATTERN
-MAINS_CONNECTOR
-
+POLARIZED_CAPACITOR
+1uf
]
[
-C4
+C3
PATTERN
POLARIZED_CAPACITOR
-1uf
+22uF
]
[
@@ -34,17 +27,24 @@ VARIABLE_RESISTOR
]
[
-C3
+C2
PATTERN
POLARIZED_CAPACITOR
-22uF
+0.1uF
]
[
-C2
+R2
+PATTERN
+RESISTOR
+220
+
+]
+[
+C1
PATTERN
POLARIZED_CAPACITOR
-0.1uF
+2200uF
]
[
@@ -55,10 +55,10 @@ SPST
]
[
-C1
+CONN1
PATTERN
-POLARIZED_CAPACITOR
-2200uF
+MAINS_CONNECTOR
+
]
[
@@ -69,9 +69,9 @@ transformer
]
[
-U2
+F1
PATTERN
-LM317
+FUSE
]
diff --git a/gnetlist/tests/common/outputs/vams/JD-output.net b/gnetlist/tests/common/outputs/vams/JD-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include-output.net b/gnetlist/tests/common/outputs/vams/JD_Include-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD_Include-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort-output.net b/gnetlist/tests/common/outputs/vams/JD_Sort-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
index 103b337..7dcdf01 100644
--- a/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
@@ -11,11 +11,12 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- V1 : ENTITY vpulse
+ A1 : ENTITY model
GENERIC MAP (
- value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
- PORT MAP ( 1 => i,
- 2 => GND);
+ file => ./models/openIP_5.cir,
+ model-name => unknown_LVD,
+ device => model)
+;
Cm : ENTITY CAPACITOR
GENERIC MAP (
@@ -25,12 +26,36 @@ BEGIN
PORT MAP ( 1 => m,
2 => GND);
- A1 : ENTITY model
+ Cp : ENTITY CAPACITOR
GENERIC MAP (
- file => ./models/openIP_5.cir,
- model-name => unknown_LVD,
- device => model)
-;
+ value => 20p,
+ symversion => 0.1)
+ PORT MAP ( 1 => p,
+ 2 => GND);
+
+ Rlp : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 1meg)
+ PORT MAP ( 2 => Vdd1,
+ 1 => p);
+
+ Rlm : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 500k)
+ PORT MAP ( 2 => GND,
+ 1 => m);
+
+ Vdd : ENTITY VOLTAGE_SOURCE
+ GENERIC MAP (
+ value => DC 3.3V)
+ PORT MAP ( 1 => Vdd1,
+ 2 => GND);
+
+ V1 : ENTITY vpulse
+ GENERIC MAP (
+ value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+ PORT MAP ( 1 => i,
+ 2 => GND);
Rt : ENTITY RESISTOR
GENERIC MAP (
@@ -38,6 +63,13 @@ BEGIN
PORT MAP ( 2 => m,
1 => p);
+ Rb : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 5.6k)
+ PORT MAP ( 2 => LVH,
+ 1 => GND);
+
M1 : ENTITY PMOS_TRANSISTOR
GENERIC MAP (
m => 36,
@@ -59,36 +91,4 @@ BEGIN
2 => GND,
6 => Vdd1,
7 => GND);
-
- Rlp : ENTITY RESISTOR
- GENERIC MAP (
- value => 1meg)
- PORT MAP ( 2 => Vdd1,
- 1 => p);
-
- Vdd : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- value => DC 3.3V)
- PORT MAP ( 1 => Vdd1,
- 2 => GND);
-
- Rlm : ENTITY RESISTOR
- GENERIC MAP (
- value => 500k)
- PORT MAP ( 2 => GND,
- 1 => m);
-
- Cp : ENTITY CAPACITOR
- GENERIC MAP (
- value => 20p,
- symversion => 0.1)
- PORT MAP ( 1 => p,
- 2 => GND);
-
- Rb : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 5.6k)
- PORT MAP ( 2 => LVH,
- 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
index 95a10a5..42676c2 100644
--- a/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
@@ -17,20 +17,13 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- Cout : ENTITY CAPACITOR
+ C2 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => VColl2,
- 2 => Vout);
-
- R5 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 10)
- PORT MAP ( 2 => unnamed_net1,
- 1 => Vin);
+ PORT MAP ( 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : ENTITY RESISTOR
GENERIC MAP (
@@ -39,6 +32,28 @@ BEGIN
PORT MAP ( 2 => Vbase2,
1 => GND);
+ R3 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 1)
+ PORT MAP ( 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 1pF)
+ PORT MAP ( 1 => GND,
+ 2 => Vem2);
+
RE2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
@@ -46,6 +61,13 @@ BEGIN
PORT MAP ( 2 => Vem2,
1 => GND);
+ RC1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 3.3K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : ENTITY NPN_TRANSISTOR
GENERIC MAP (
device => NPN_TRANSISTOR,
@@ -54,40 +76,26 @@ BEGIN
1 => Vem2,
2 => Vbase2);
+ C1 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 2.2uF)
+ PORT MAP ( 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : ENTITY directive
GENERIC MAP (
device => directive,
value => .options TEMP=25)
;
- R3 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase2);
-
A2 : ENTITY include
GENERIC MAP (
device => include,
file => Simulation.cmd)
;
- RE1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 100)
- PORT MAP ( 2 => Vem1,
- 1 => GND);
-
- Q1 : ENTITY NPN_TRANSISTOR
- GENERIC MAP (
- device => NPN_TRANSISTOR,
- model-name => 2N3904)
- PORT MAP ( 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : ENTITY model
GENERIC MAP (
device => model,
@@ -95,12 +103,13 @@ BEGIN
model-name => 2N3904)
;
- R2 : ENTITY RESISTOR
+ VCC : ENTITY VOLTAGE_SOURCE
GENERIC MAP (
- device => RESISTOR,
- value => 2K)
- PORT MAP ( 2 => Vbase1,
- 1 => GND);
+ footprint => none,
+ device => VOLTAGE_SOURCE,
+ value => DC 15V)
+ PORT MAP ( 1 => Vcc,
+ 2 => GND);
Vinput : ENTITY vsin
GENERIC MAP (
@@ -110,59 +119,28 @@ BEGIN
PORT MAP ( 1 => Vin,
2 => GND);
- R1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase1);
-
- C2 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 2.2uF)
- PORT MAP ( 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : ENTITY CAPACITOR
+ CE1 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 1pF)
PORT MAP ( 1 => GND,
- 2 => Vem2);
+ 2 => Vem1);
- C1 : ENTITY CAPACITOR
+ Cout : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => unnamed_net1,
- 2 => Vbase1);
-
- CE1 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 1pF)
- PORT MAP ( 1 => GND,
- 2 => Vem1);
+ PORT MAP ( 1 => VColl2,
+ 2 => Vout);
- R8 : ENTITY RESISTOR
+ RL : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 1)
- PORT MAP ( 2 => unnamed_net2,
- 1 => Vcoll1);
-
- VCC : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- footprint => none,
- device => VOLTAGE_SOURCE,
- value => DC 15V)
- PORT MAP ( 1 => Vcc,
- 2 => GND);
+ value => 100K)
+ PORT MAP ( 2 => Vout,
+ 1 => GND);
RC2 : ENTITY RESISTOR
GENERIC MAP (
@@ -171,17 +149,39 @@ BEGIN
PORT MAP ( 2 => Vcc,
1 => VColl2);
- RC1 : ENTITY RESISTOR
+ RE1 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 3.3K)
- PORT MAP ( 2 => Vcc,
- 1 => Vcoll1);
+ value => 100)
+ PORT MAP ( 2 => Vem1,
+ 1 => GND);
- RL : ENTITY RESISTOR
+ R2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 100K)
- PORT MAP ( 2 => Vout,
+ value => 2K)
+ PORT MAP ( 2 => Vbase1,
1 => GND);
+
+ R1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 10)
+ PORT MAP ( 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : ENTITY NPN_TRANSISTOR
+ GENERIC MAP (
+ device => NPN_TRANSISTOR,
+ model-name => 2N3904)
+ PORT MAP ( 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
index 95a10a5..42676c2 100644
--- a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
@@ -17,20 +17,13 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- Cout : ENTITY CAPACITOR
+ C2 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => VColl2,
- 2 => Vout);
-
- R5 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 10)
- PORT MAP ( 2 => unnamed_net1,
- 1 => Vin);
+ PORT MAP ( 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : ENTITY RESISTOR
GENERIC MAP (
@@ -39,6 +32,28 @@ BEGIN
PORT MAP ( 2 => Vbase2,
1 => GND);
+ R3 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 1)
+ PORT MAP ( 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 1pF)
+ PORT MAP ( 1 => GND,
+ 2 => Vem2);
+
RE2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
@@ -46,6 +61,13 @@ BEGIN
PORT MAP ( 2 => Vem2,
1 => GND);
+ RC1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 3.3K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : ENTITY NPN_TRANSISTOR
GENERIC MAP (
device => NPN_TRANSISTOR,
@@ -54,40 +76,26 @@ BEGIN
1 => Vem2,
2 => Vbase2);
+ C1 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 2.2uF)
+ PORT MAP ( 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : ENTITY directive
GENERIC MAP (
device => directive,
value => .options TEMP=25)
;
- R3 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase2);
-
A2 : ENTITY include
GENERIC MAP (
device => include,
file => Simulation.cmd)
;
- RE1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 100)
- PORT MAP ( 2 => Vem1,
- 1 => GND);
-
- Q1 : ENTITY NPN_TRANSISTOR
- GENERIC MAP (
- device => NPN_TRANSISTOR,
- model-name => 2N3904)
- PORT MAP ( 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : ENTITY model
GENERIC MAP (
device => model,
@@ -95,12 +103,13 @@ BEGIN
model-name => 2N3904)
;
- R2 : ENTITY RESISTOR
+ VCC : ENTITY VOLTAGE_SOURCE
GENERIC MAP (
- device => RESISTOR,
- value => 2K)
- PORT MAP ( 2 => Vbase1,
- 1 => GND);
+ footprint => none,
+ device => VOLTAGE_SOURCE,
+ value => DC 15V)
+ PORT MAP ( 1 => Vcc,
+ 2 => GND);
Vinput : ENTITY vsin
GENERIC MAP (
@@ -110,59 +119,28 @@ BEGIN
PORT MAP ( 1 => Vin,
2 => GND);
- R1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase1);
-
- C2 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 2.2uF)
- PORT MAP ( 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : ENTITY CAPACITOR
+ CE1 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 1pF)
PORT MAP ( 1 => GND,
- 2 => Vem2);
+ 2 => Vem1);
- C1 : ENTITY CAPACITOR
+ Cout : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => unnamed_net1,
- 2 => Vbase1);
-
- CE1 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 1pF)
- PORT MAP ( 1 => GND,
- 2 => Vem1);
+ PORT MAP ( 1 => VColl2,
+ 2 => Vout);
- R8 : ENTITY RESISTOR
+ RL : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 1)
- PORT MAP ( 2 => unnamed_net2,
- 1 => Vcoll1);
-
- VCC : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- footprint => none,
- device => VOLTAGE_SOURCE,
- value => DC 15V)
- PORT MAP ( 1 => Vcc,
- 2 => GND);
+ value => 100K)
+ PORT MAP ( 2 => Vout,
+ 1 => GND);
RC2 : ENTITY RESISTOR
GENERIC MAP (
@@ -171,17 +149,39 @@ BEGIN
PORT MAP ( 2 => Vcc,
1 => VColl2);
- RC1 : ENTITY RESISTOR
+ RE1 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 3.3K)
- PORT MAP ( 2 => Vcc,
- 1 => Vcoll1);
+ value => 100)
+ PORT MAP ( 2 => Vem1,
+ 1 => GND);
- RL : ENTITY RESISTOR
+ R2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 100K)
- PORT MAP ( 2 => Vout,
+ value => 2K)
+ PORT MAP ( 2 => Vbase1,
1 => GND);
+
+ R1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 10)
+ PORT MAP ( 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : ENTITY NPN_TRANSISTOR
+ GENERIC MAP (
+ device => NPN_TRANSISTOR,
+ model-name => 2N3904)
+ PORT MAP ( 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
index 95a10a5..42676c2 100644
--- a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
@@ -17,20 +17,13 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- Cout : ENTITY CAPACITOR
+ C2 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => VColl2,
- 2 => Vout);
-
- R5 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 10)
- PORT MAP ( 2 => unnamed_net1,
- 1 => Vin);
+ PORT MAP ( 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : ENTITY RESISTOR
GENERIC MAP (
@@ -39,6 +32,28 @@ BEGIN
PORT MAP ( 2 => Vbase2,
1 => GND);
+ R3 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 1)
+ PORT MAP ( 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 1pF)
+ PORT MAP ( 1 => GND,
+ 2 => Vem2);
+
RE2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
@@ -46,6 +61,13 @@ BEGIN
PORT MAP ( 2 => Vem2,
1 => GND);
+ RC1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 3.3K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : ENTITY NPN_TRANSISTOR
GENERIC MAP (
device => NPN_TRANSISTOR,
@@ -54,40 +76,26 @@ BEGIN
1 => Vem2,
2 => Vbase2);
+ C1 : ENTITY CAPACITOR
+ GENERIC MAP (
+ symversion => 0.1,
+ device => CAPACITOR,
+ value => 2.2uF)
+ PORT MAP ( 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : ENTITY directive
GENERIC MAP (
device => directive,
value => .options TEMP=25)
;
- R3 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase2);
-
A2 : ENTITY include
GENERIC MAP (
device => include,
file => Simulation.cmd)
;
- RE1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 100)
- PORT MAP ( 2 => Vem1,
- 1 => GND);
-
- Q1 : ENTITY NPN_TRANSISTOR
- GENERIC MAP (
- device => NPN_TRANSISTOR,
- model-name => 2N3904)
- PORT MAP ( 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : ENTITY model
GENERIC MAP (
device => model,
@@ -95,12 +103,13 @@ BEGIN
model-name => 2N3904)
;
- R2 : ENTITY RESISTOR
+ VCC : ENTITY VOLTAGE_SOURCE
GENERIC MAP (
- device => RESISTOR,
- value => 2K)
- PORT MAP ( 2 => Vbase1,
- 1 => GND);
+ footprint => none,
+ device => VOLTAGE_SOURCE,
+ value => DC 15V)
+ PORT MAP ( 1 => Vcc,
+ 2 => GND);
Vinput : ENTITY vsin
GENERIC MAP (
@@ -110,59 +119,28 @@ BEGIN
PORT MAP ( 1 => Vin,
2 => GND);
- R1 : ENTITY RESISTOR
- GENERIC MAP (
- device => RESISTOR,
- value => 28K)
- PORT MAP ( 2 => Vcc,
- 1 => Vbase1);
-
- C2 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 2.2uF)
- PORT MAP ( 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : ENTITY CAPACITOR
+ CE1 : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 1pF)
PORT MAP ( 1 => GND,
- 2 => Vem2);
+ 2 => Vem1);
- C1 : ENTITY CAPACITOR
+ Cout : ENTITY CAPACITOR
GENERIC MAP (
symversion => 0.1,
device => CAPACITOR,
value => 2.2uF)
- PORT MAP ( 1 => unnamed_net1,
- 2 => Vbase1);
-
- CE1 : ENTITY CAPACITOR
- GENERIC MAP (
- symversion => 0.1,
- device => CAPACITOR,
- value => 1pF)
- PORT MAP ( 1 => GND,
- 2 => Vem1);
+ PORT MAP ( 1 => VColl2,
+ 2 => Vout);
- R8 : ENTITY RESISTOR
+ RL : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 1)
- PORT MAP ( 2 => unnamed_net2,
- 1 => Vcoll1);
-
- VCC : ENTITY VOLTAGE_SOURCE
- GENERIC MAP (
- footprint => none,
- device => VOLTAGE_SOURCE,
- value => DC 15V)
- PORT MAP ( 1 => Vcc,
- 2 => GND);
+ value => 100K)
+ PORT MAP ( 2 => Vout,
+ 1 => GND);
RC2 : ENTITY RESISTOR
GENERIC MAP (
@@ -171,17 +149,39 @@ BEGIN
PORT MAP ( 2 => Vcc,
1 => VColl2);
- RC1 : ENTITY RESISTOR
+ RE1 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 3.3K)
- PORT MAP ( 2 => Vcc,
- 1 => Vcoll1);
+ value => 100)
+ PORT MAP ( 2 => Vem1,
+ 1 => GND);
- RL : ENTITY RESISTOR
+ R2 : ENTITY RESISTOR
GENERIC MAP (
device => RESISTOR,
- value => 100K)
- PORT MAP ( 2 => Vout,
+ value => 2K)
+ PORT MAP ( 2 => Vbase1,
1 => GND);
+
+ R1 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 28K)
+ PORT MAP ( 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : ENTITY RESISTOR
+ GENERIC MAP (
+ device => RESISTOR,
+ value => 10)
+ PORT MAP ( 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : ENTITY NPN_TRANSISTOR
+ GENERIC MAP (
+ device => NPN_TRANSISTOR,
+ model-name => 2N3904)
+ PORT MAP ( 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/cascade-output.net b/gnetlist/tests/common/outputs/vams/cascade-output.net
index 9e52aae..fa06718 100644
--- a/gnetlist/tests/common/outputs/vams/cascade-output.net
+++ b/gnetlist/tests/common/outputs/vams/cascade-output.net
@@ -22,32 +22,16 @@ BEGIN
PORT MAP ( 1 => unnamed_net6,
2 => OPEN);
- AMP1 : ENTITY cascade-amp
- GENERIC MAP (
- IIP3 => -2,
- NF => 5,
- G => 12,
- footprint => none,
- device => cascade-amp)
- PORT MAP ( 1 => unnamed_net1,
- 2 => unnamed_net2);
-
- SOURCE : ENTITY cascade-source
- GENERIC MAP (
- BW => 1,
- CN => 70,
- C => 0,
- footprint => none,
- device => cascade-source)
- PORT MAP ( 1 => unnamed_net1);
-
- DEFAULTS : ENTITY cascade-defaults-top
+ T1 : ENTITY cascade-transformer
GENERIC MAP (
- RHO => 0,
ROUT => 50,
RIN => 50,
- device => cascade-defaults-top)
- PORT MAP ( 1 => GND);
+ NF => 0,
+ G => 0,
+ footprint => none,
+ device => cascade-transformer)
+ PORT MAP ( 1 => unnamed_net5,
+ 2 => unnamed_net6);
MX1 : ENTITY cascade-mixer
GENERIC MAP (
@@ -59,6 +43,15 @@ BEGIN
PORT MAP ( 1 => unnamed_net4,
2 => unnamed_net5);
+ FL1 : ENTITY cascade-filter
+ GENERIC MAP (
+ NF => 5.5,
+ G => -5.5,
+ device => cascade-filter,
+ footprint => none)
+ PORT MAP ( 1 => unnamed_net3,
+ 2 => unnamed_net4);
+
DEF1 : ENTITY cascade-defaults
GENERIC MAP (
footprint => none,
@@ -69,23 +62,30 @@ BEGIN
PORT MAP ( 1 => unnamed_net2,
2 => unnamed_net3);
- T1 : ENTITY cascade-transformer
+ AMP1 : ENTITY cascade-amp
GENERIC MAP (
- ROUT => 50,
- RIN => 50,
- NF => 0,
- G => 0,
+ IIP3 => -2,
+ NF => 5,
+ G => 12,
footprint => none,
- device => cascade-transformer)
- PORT MAP ( 1 => unnamed_net5,
- 2 => unnamed_net6);
+ device => cascade-amp)
+ PORT MAP ( 1 => unnamed_net1,
+ 2 => unnamed_net2);
- FL1 : ENTITY cascade-filter
+ SOURCE : ENTITY cascade-source
GENERIC MAP (
- NF => 5.5,
- G => -5.5,
- device => cascade-filter,
- footprint => none)
- PORT MAP ( 1 => unnamed_net3,
- 2 => unnamed_net4);
+ BW => 1,
+ CN => 70,
+ C => 0,
+ footprint => none,
+ device => cascade-source)
+ PORT MAP ( 1 => unnamed_net1);
+
+ DEFAULTS : ENTITY cascade-defaults-top
+ GENERIC MAP (
+ RHO => 0,
+ ROUT => 50,
+ RIN => 50,
+ device => cascade-defaults-top)
+ PORT MAP ( 1 => GND);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/multiequal-output.net b/gnetlist/tests/common/outputs/vams/multiequal-output.net
index 52043c4..4d8d95e 100644
--- a/gnetlist/tests/common/outputs/vams/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/vams/multiequal-output.net
@@ -13,14 +13,14 @@ BEGIN
PORT MAP ( 1 => unnamed_net1,
2 => GND);
- A1 : ENTITY options
- GENERIC MAP (
- value => abotol=1e-11)
-;
-
R1 : ENTITY RESISTOR
GENERIC MAP (
value => 20)
PORT MAP ( 2 => unnamed_net1,
1 => GND);
+
+ A1 : ENTITY options
+ GENERIC MAP (
+ value => abotol=1e-11)
+;
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/netattrib-output.net b/gnetlist/tests/common/outputs/vams/netattrib-output.net
index 39dc79a..ba111c8 100644
--- a/gnetlist/tests/common/outputs/vams/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/vams/netattrib-output.net
@@ -14,16 +14,6 @@ BEGIN
PORT MAP ( 1 => one,
2 => OPEN);
- U100 : ENTITY 7400
- GENERIC MAP (
- net => netattrib:5)
- PORT MAP ( 3 => one,
- 2 => OPEN,
- 1 => OPEN,
- 14 => Vcc,
- 7 => GND,
- 5 => netattrib);
-
U300 : ENTITY 7404
PORT MAP ( 1 => one,
2 => unnamed_net1,
@@ -35,4 +25,14 @@ BEGIN
2 => netattrib,
7 => GND,
14 => Vcc);
+
+ U100 : ENTITY 7400
+ GENERIC MAP (
+ net => netattrib:5)
+ PORT MAP ( 3 => one,
+ 2 => OPEN,
+ 1 => OPEN,
+ 14 => Vcc,
+ 7 => GND,
+ 5 => netattrib);
END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/powersupply-output.net b/gnetlist/tests/common/outputs/vams/powersupply-output.net
index a90b651..92782b5 100644
--- a/gnetlist/tests/common/outputs/vams/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/vams/powersupply-output.net
@@ -16,27 +16,23 @@ ARCHITECTURE default_architecture OF default_entity IS
BEGIN
-- Architecture statement part
- F1 : ENTITY FUSE
- PORT MAP ( 1 => two,
- 2 => three);
-
- R2 : ENTITY RESISTOR
- GENERIC MAP (
- value => 220)
+ U2 : ENTITY LM317
PORT MAP ( 2 => eleven,
+ 3 => eight,
1 => ten);
- CONN1 : ENTITY MAINS_CONNECTOR
- PORT MAP ( 1 => one,
- 2 => five,
- 3 => GND);
-
C4 : ENTITY POLARIZED_CAPACITOR
GENERIC MAP (
value => 1uf)
PORT MAP ( 1 => eleven,
2 => nine);
+ C3 : ENTITY POLARIZED_CAPACITOR
+ GENERIC MAP (
+ value => 22uF)
+ PORT MAP ( 1 => ten,
+ 2 => nine);
+
R1 : ENTITY VARIABLE_RESISTOR
GENERIC MAP (
value => 5k)
@@ -44,21 +40,17 @@ BEGIN
2 => ten,
1 => nine);
- C3 : ENTITY POLARIZED_CAPACITOR
- GENERIC MAP (
- value => 22uF)
- PORT MAP ( 1 => ten,
- 2 => nine);
-
C2 : ENTITY POLARIZED_CAPACITOR
GENERIC MAP (
value => 0.1uF)
PORT MAP ( 1 => eight,
2 => nine);
- S1 : ENTITY SPST
- PORT MAP ( 2 => two,
- 1 => one);
+ R2 : ENTITY RESISTOR
+ GENERIC MAP (
+ value => 220)
+ PORT MAP ( 2 => eleven,
+ 1 => ten);
C1 : ENTITY POLARIZED_CAPACITOR
GENERIC MAP (
@@ -66,16 +58,24 @@ BEGIN
PORT MAP ( 1 => eight,
2 => nine);
+ S1 : ENTITY SPST
+ PORT MAP ( 2 => two,
+ 1 => one);
+
+ CONN1 : ENTITY MAINS_CONNECTOR
+ PORT MAP ( 1 => one,
+ 2 => five,
+ 3 => GND);
+
T1 : ENTITY transformer
PORT MAP ( 2 => five,
1 => three,
4 => seven,
3 => six);
- U2 : ENTITY LM317
- PORT MAP ( 2 => eleven,
- 3 => eight,
- 1 => ten);
+ F1 : ENTITY FUSE
+ PORT MAP ( 1 => two,
+ 2 => three);
U1 : ENTITY DIODE-BRIDGE
PORT MAP ( 1 => eight,
diff --git a/gnetlist/tests/common/outputs/verilog/JD-output.net b/gnetlist/tests/common/outputs/verilog/JD-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
index 0d5313b..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
@@ -25,23 +25,48 @@ wire m ;
/* continuous assignments */
/* Package instantiations */
-vpulse V1 (
- .\1 ( i ),
- .\2 ( GND )
- );
+model A1 ( );
CAPACITOR Cm (
.\1 ( m ),
.\2 ( GND )
);
-model A1 ( );
+CAPACITOR Cp (
+ .\1 ( p ),
+ .\2 ( GND )
+ );
+
+RESISTOR Rlp (
+ .\2 ( Vdd1 ),
+ .\1 ( p )
+ );
+
+RESISTOR Rlm (
+ .\2 ( GND ),
+ .\1 ( m )
+ );
+
+VOLTAGE_SOURCE Vdd (
+ .\1 ( Vdd1 ),
+ .\2 ( GND )
+ );
+
+vpulse V1 (
+ .\1 ( i ),
+ .\2 ( GND )
+ );
RESISTOR Rt (
.\2 ( m ),
.\1 ( p )
);
+RESISTOR Rb (
+ .\2 ( LVH ),
+ .\1 ( GND )
+ );
+
PMOS_TRANSISTOR M1 (
.S ( Vdd1 ),
.B ( Vdd1 ),
@@ -59,29 +84,4 @@ LVD X1 (
.\7 ( GND )
);
-RESISTOR Rlp (
- .\2 ( Vdd1 ),
- .\1 ( p )
- );
-
-VOLTAGE_SOURCE Vdd (
- .\1 ( Vdd1 ),
- .\2 ( GND )
- );
-
-RESISTOR Rlm (
- .\2 ( GND ),
- .\1 ( m )
- );
-
-CAPACITOR Cp (
- .\1 ( p ),
- .\2 ( GND )
- );
-
-RESISTOR Rb (
- .\2 ( LVH ),
- .\1 ( GND )
- );
-
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
index dec17e9..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
@@ -31,14 +31,9 @@ wire Vcoll1 ;
/* continuous assignments */
/* Package instantiations */
-CAPACITOR Cout (
- .\1 ( VColl2 ),
- .\2 ( Vout )
- );
-
-RESISTOR R5 (
- .\2 ( unnamed_net1 ),
- .\1 ( Vin )
+CAPACITOR C2 (
+ .\1 ( unnamed_net2 ),
+ .\2 ( Vbase2 )
);
RESISTOR R4 (
@@ -46,42 +41,51 @@ RESISTOR R4 (
.\1 ( GND )
);
+RESISTOR R3 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase2 )
+ );
+
+RESISTOR R8 (
+ .\2 ( unnamed_net2 ),
+ .\1 ( Vcoll1 )
+ );
+
+CAPACITOR CE2 (
+ .\1 ( GND ),
+ .\2 ( Vem2 )
+ );
+
RESISTOR RE2 (
.\2 ( Vem2 ),
.\1 ( GND )
);
+RESISTOR RC1 (
+ .\2 ( Vcc ),
+ .\1 ( Vcoll1 )
+ );
+
NPN_TRANSISTOR Q2 (
.\3 ( VColl2 ),
.\1 ( Vem2 ),
.\2 ( Vbase2 )
);
-directive A3 ( );
-
-RESISTOR R3 (
- .\2 ( Vcc ),
- .\1 ( Vbase2 )
+CAPACITOR C1 (
+ .\1 ( unnamed_net1 ),
+ .\2 ( Vbase1 )
);
-include A2 ( );
-
-RESISTOR RE1 (
- .\2 ( Vem1 ),
- .\1 ( GND )
- );
+directive A3 ( );
-NPN_TRANSISTOR Q1 (
- .\3 ( Vcoll1 ),
- .\1 ( Vem1 ),
- .\2 ( Vbase1 )
- );
+include A2 ( );
model A1 ( );
-RESISTOR R2 (
- .\2 ( Vbase1 ),
- .\1 ( GND )
+VOLTAGE_SOURCE VCC (
+ .\1 ( Vcc ),
+ .\2 ( GND )
);
vsin Vinput (
@@ -89,39 +93,19 @@ vsin Vinput (
.\2 ( GND )
);
-RESISTOR R1 (
- .\2 ( Vcc ),
- .\1 ( Vbase1 )
- );
-
-CAPACITOR C2 (
- .\1 ( unnamed_net2 ),
- .\2 ( Vbase2 )
- );
-
-CAPACITOR CE2 (
- .\1 ( GND ),
- .\2 ( Vem2 )
- );
-
-CAPACITOR C1 (
- .\1 ( unnamed_net1 ),
- .\2 ( Vbase1 )
- );
-
CAPACITOR CE1 (
.\1 ( GND ),
.\2 ( Vem1 )
);
-RESISTOR R8 (
- .\2 ( unnamed_net2 ),
- .\1 ( Vcoll1 )
+CAPACITOR Cout (
+ .\1 ( VColl2 ),
+ .\2 ( Vout )
);
-VOLTAGE_SOURCE VCC (
- .\1 ( Vcc ),
- .\2 ( GND )
+RESISTOR RL (
+ .\2 ( Vout ),
+ .\1 ( GND )
);
RESISTOR RC2 (
@@ -129,14 +113,30 @@ RESISTOR RC2 (
.\1 ( VColl2 )
);
-RESISTOR RC1 (
- .\2 ( Vcc ),
- .\1 ( Vcoll1 )
+RESISTOR RE1 (
+ .\2 ( Vem1 ),
+ .\1 ( GND )
);
-RESISTOR RL (
- .\2 ( Vout ),
+RESISTOR R2 (
+ .\2 ( Vbase1 ),
.\1 ( GND )
);
+RESISTOR R1 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase1 )
+ );
+
+RESISTOR R5 (
+ .\2 ( unnamed_net1 ),
+ .\1 ( Vin )
+ );
+
+NPN_TRANSISTOR Q1 (
+ .\3 ( Vcoll1 ),
+ .\1 ( Vem1 ),
+ .\2 ( Vbase1 )
+ );
+
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
index dec17e9..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
@@ -31,14 +31,9 @@ wire Vcoll1 ;
/* continuous assignments */
/* Package instantiations */
-CAPACITOR Cout (
- .\1 ( VColl2 ),
- .\2 ( Vout )
- );
-
-RESISTOR R5 (
- .\2 ( unnamed_net1 ),
- .\1 ( Vin )
+CAPACITOR C2 (
+ .\1 ( unnamed_net2 ),
+ .\2 ( Vbase2 )
);
RESISTOR R4 (
@@ -46,42 +41,51 @@ RESISTOR R4 (
.\1 ( GND )
);
+RESISTOR R3 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase2 )
+ );
+
+RESISTOR R8 (
+ .\2 ( unnamed_net2 ),
+ .\1 ( Vcoll1 )
+ );
+
+CAPACITOR CE2 (
+ .\1 ( GND ),
+ .\2 ( Vem2 )
+ );
+
RESISTOR RE2 (
.\2 ( Vem2 ),
.\1 ( GND )
);
+RESISTOR RC1 (
+ .\2 ( Vcc ),
+ .\1 ( Vcoll1 )
+ );
+
NPN_TRANSISTOR Q2 (
.\3 ( VColl2 ),
.\1 ( Vem2 ),
.\2 ( Vbase2 )
);
-directive A3 ( );
-
-RESISTOR R3 (
- .\2 ( Vcc ),
- .\1 ( Vbase2 )
+CAPACITOR C1 (
+ .\1 ( unnamed_net1 ),
+ .\2 ( Vbase1 )
);
-include A2 ( );
-
-RESISTOR RE1 (
- .\2 ( Vem1 ),
- .\1 ( GND )
- );
+directive A3 ( );
-NPN_TRANSISTOR Q1 (
- .\3 ( Vcoll1 ),
- .\1 ( Vem1 ),
- .\2 ( Vbase1 )
- );
+include A2 ( );
model A1 ( );
-RESISTOR R2 (
- .\2 ( Vbase1 ),
- .\1 ( GND )
+VOLTAGE_SOURCE VCC (
+ .\1 ( Vcc ),
+ .\2 ( GND )
);
vsin Vinput (
@@ -89,39 +93,19 @@ vsin Vinput (
.\2 ( GND )
);
-RESISTOR R1 (
- .\2 ( Vcc ),
- .\1 ( Vbase1 )
- );
-
-CAPACITOR C2 (
- .\1 ( unnamed_net2 ),
- .\2 ( Vbase2 )
- );
-
-CAPACITOR CE2 (
- .\1 ( GND ),
- .\2 ( Vem2 )
- );
-
-CAPACITOR C1 (
- .\1 ( unnamed_net1 ),
- .\2 ( Vbase1 )
- );
-
CAPACITOR CE1 (
.\1 ( GND ),
.\2 ( Vem1 )
);
-RESISTOR R8 (
- .\2 ( unnamed_net2 ),
- .\1 ( Vcoll1 )
+CAPACITOR Cout (
+ .\1 ( VColl2 ),
+ .\2 ( Vout )
);
-VOLTAGE_SOURCE VCC (
- .\1 ( Vcc ),
- .\2 ( GND )
+RESISTOR RL (
+ .\2 ( Vout ),
+ .\1 ( GND )
);
RESISTOR RC2 (
@@ -129,14 +113,30 @@ RESISTOR RC2 (
.\1 ( VColl2 )
);
-RESISTOR RC1 (
- .\2 ( Vcc ),
- .\1 ( Vcoll1 )
+RESISTOR RE1 (
+ .\2 ( Vem1 ),
+ .\1 ( GND )
);
-RESISTOR RL (
- .\2 ( Vout ),
+RESISTOR R2 (
+ .\2 ( Vbase1 ),
.\1 ( GND )
);
+RESISTOR R1 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase1 )
+ );
+
+RESISTOR R5 (
+ .\2 ( unnamed_net1 ),
+ .\1 ( Vin )
+ );
+
+NPN_TRANSISTOR Q1 (
+ .\3 ( Vcoll1 ),
+ .\1 ( Vem1 ),
+ .\2 ( Vbase1 )
+ );
+
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
index dec17e9..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
@@ -31,14 +31,9 @@ wire Vcoll1 ;
/* continuous assignments */
/* Package instantiations */
-CAPACITOR Cout (
- .\1 ( VColl2 ),
- .\2 ( Vout )
- );
-
-RESISTOR R5 (
- .\2 ( unnamed_net1 ),
- .\1 ( Vin )
+CAPACITOR C2 (
+ .\1 ( unnamed_net2 ),
+ .\2 ( Vbase2 )
);
RESISTOR R4 (
@@ -46,42 +41,51 @@ RESISTOR R4 (
.\1 ( GND )
);
+RESISTOR R3 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase2 )
+ );
+
+RESISTOR R8 (
+ .\2 ( unnamed_net2 ),
+ .\1 ( Vcoll1 )
+ );
+
+CAPACITOR CE2 (
+ .\1 ( GND ),
+ .\2 ( Vem2 )
+ );
+
RESISTOR RE2 (
.\2 ( Vem2 ),
.\1 ( GND )
);
+RESISTOR RC1 (
+ .\2 ( Vcc ),
+ .\1 ( Vcoll1 )
+ );
+
NPN_TRANSISTOR Q2 (
.\3 ( VColl2 ),
.\1 ( Vem2 ),
.\2 ( Vbase2 )
);
-directive A3 ( );
-
-RESISTOR R3 (
- .\2 ( Vcc ),
- .\1 ( Vbase2 )
+CAPACITOR C1 (
+ .\1 ( unnamed_net1 ),
+ .\2 ( Vbase1 )
);
-include A2 ( );
-
-RESISTOR RE1 (
- .\2 ( Vem1 ),
- .\1 ( GND )
- );
+directive A3 ( );
-NPN_TRANSISTOR Q1 (
- .\3 ( Vcoll1 ),
- .\1 ( Vem1 ),
- .\2 ( Vbase1 )
- );
+include A2 ( );
model A1 ( );
-RESISTOR R2 (
- .\2 ( Vbase1 ),
- .\1 ( GND )
+VOLTAGE_SOURCE VCC (
+ .\1 ( Vcc ),
+ .\2 ( GND )
);
vsin Vinput (
@@ -89,39 +93,19 @@ vsin Vinput (
.\2 ( GND )
);
-RESISTOR R1 (
- .\2 ( Vcc ),
- .\1 ( Vbase1 )
- );
-
-CAPACITOR C2 (
- .\1 ( unnamed_net2 ),
- .\2 ( Vbase2 )
- );
-
-CAPACITOR CE2 (
- .\1 ( GND ),
- .\2 ( Vem2 )
- );
-
-CAPACITOR C1 (
- .\1 ( unnamed_net1 ),
- .\2 ( Vbase1 )
- );
-
CAPACITOR CE1 (
.\1 ( GND ),
.\2 ( Vem1 )
);
-RESISTOR R8 (
- .\2 ( unnamed_net2 ),
- .\1 ( Vcoll1 )
+CAPACITOR Cout (
+ .\1 ( VColl2 ),
+ .\2 ( Vout )
);
-VOLTAGE_SOURCE VCC (
- .\1 ( Vcc ),
- .\2 ( GND )
+RESISTOR RL (
+ .\2 ( Vout ),
+ .\1 ( GND )
);
RESISTOR RC2 (
@@ -129,14 +113,30 @@ RESISTOR RC2 (
.\1 ( VColl2 )
);
-RESISTOR RC1 (
- .\2 ( Vcc ),
- .\1 ( Vcoll1 )
+RESISTOR RE1 (
+ .\2 ( Vem1 ),
+ .\1 ( GND )
);
-RESISTOR RL (
- .\2 ( Vout ),
+RESISTOR R2 (
+ .\2 ( Vbase1 ),
.\1 ( GND )
);
+RESISTOR R1 (
+ .\2 ( Vcc ),
+ .\1 ( Vbase1 )
+ );
+
+RESISTOR R5 (
+ .\2 ( unnamed_net1 ),
+ .\1 ( Vin )
+ );
+
+NPN_TRANSISTOR Q1 (
+ .\3 ( Vcoll1 ),
+ .\1 ( Vem1 ),
+ .\2 ( Vbase1 )
+ );
+
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/cascade-output.net b/gnetlist/tests/common/outputs/verilog/cascade-output.net
index af96ecc..5af04ac 100644
--- a/gnetlist/tests/common/outputs/verilog/cascade-output.net
+++ b/gnetlist/tests/common/outputs/verilog/cascade-output.net
@@ -30,17 +30,9 @@ wire GND ;
.\1 ( unnamed_net6 )
);
-\cascade-amp AMP1 (
- .\1 ( unnamed_net1 ),
- .\2 ( unnamed_net2 )
- );
-
-\cascade-source SOURCE (
- .\1 ( unnamed_net1 )
- );
-
-\cascade-defaults-top DEFAULTS (
- .\1 ( GND )
+\cascade-transformer T1 (
+ .\1 ( unnamed_net5 ),
+ .\2 ( unnamed_net6 )
);
\cascade-mixer MX1 (
@@ -48,19 +40,27 @@ wire GND ;
.\2 ( unnamed_net5 )
);
+\cascade-filter FL1 (
+ .\1 ( unnamed_net3 ),
+ .\2 ( unnamed_net4 )
+ );
+
\cascade-defaults DEF1 (
.\1 ( unnamed_net2 ),
.\2 ( unnamed_net3 )
);
-\cascade-transformer T1 (
- .\1 ( unnamed_net5 ),
- .\2 ( unnamed_net6 )
+\cascade-amp AMP1 (
+ .\1 ( unnamed_net1 ),
+ .\2 ( unnamed_net2 )
);
-\cascade-filter FL1 (
- .\1 ( unnamed_net3 ),
- .\2 ( unnamed_net4 )
+\cascade-source SOURCE (
+ .\1 ( unnamed_net1 )
+ );
+
+\cascade-defaults-top DEFAULTS (
+ .\1 ( GND )
);
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/multiequal-output.net b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
index 2d57b47..5a2fe51 100644
--- a/gnetlist/tests/common/outputs/verilog/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
@@ -26,11 +26,11 @@ VOLTAGE_SOURCE V1 (
.\2 ( GND )
);
-options A1 ( );
-
RESISTOR R1 (
.\2 ( unnamed_net1 ),
.\1 ( GND )
);
+options A1 ( );
+
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/netattrib-output.net b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
index 1e1836c..dba917e 100644
--- a/gnetlist/tests/common/outputs/verilog/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
@@ -28,13 +28,6 @@ FUSE F1 (
.\1 ( one )
);
-\7400 U100 (
- .\3 ( one ),
- .\14 ( Vcc ),
- .\7 ( GND ),
- .\5 ( netattrib )
- );
-
\7404 U300 (
.\1 ( one ),
.\2 ( unnamed_net1 ),
@@ -49,4 +42,11 @@ FUSE F1 (
.\14 ( Vcc )
);
+\7400 U100 (
+ .\3 ( one ),
+ .\14 ( Vcc ),
+ .\7 ( GND ),
+ .\5 ( netattrib )
+ );
+
endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/powersupply-output.net b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
index 9386f4b..3611994 100644
--- a/gnetlist/tests/common/outputs/verilog/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
@@ -30,39 +30,39 @@ wire eight ;
/* continuous assignments */
/* Package instantiations */
-FUSE F1 (
- .\1 ( two ),
- .\2 ( three )
- );
-
-RESISTOR R2 (
+LM317 U2 (
.\2 ( eleven ),
+ .\3 ( eight ),
.\1 ( ten )
);
-MAINS_CONNECTOR CONN1 (
- .\1 ( one ),
- .\2 ( five ),
- .\3 ( GND )
- );
-
POLARIZED_CAPACITOR C4 (
.\1 ( eleven ),
.\2 ( nine )
);
+POLARIZED_CAPACITOR C3 (
+ .\1 ( ten ),
+ .\2 ( nine )
+ );
+
VARIABLE_RESISTOR R1 (
.\3 ( nine ),
.\2 ( ten ),
.\1 ( nine )
);
-POLARIZED_CAPACITOR C3 (
- .\1 ( ten ),
+POLARIZED_CAPACITOR C2 (
+ .\1 ( eight ),
.\2 ( nine )
);
-POLARIZED_CAPACITOR C2 (
+RESISTOR R2 (
+ .\2 ( eleven ),
+ .\1 ( ten )
+ );
+
+POLARIZED_CAPACITOR C1 (
.\1 ( eight ),
.\2 ( nine )
);
@@ -72,9 +72,10 @@ SPST S1 (
.\1 ( one )
);
-POLARIZED_CAPACITOR C1 (
- .\1 ( eight ),
- .\2 ( nine )
+MAINS_CONNECTOR CONN1 (
+ .\1 ( one ),
+ .\2 ( five ),
+ .\3 ( GND )
);
transformer T1 (
@@ -84,10 +85,9 @@ transformer T1 (
.\3 ( six )
);
-LM317 U2 (
- .\2 ( eleven ),
- .\3 ( eight ),
- .\1 ( ten )
+FUSE F1 (
+ .\1 ( two ),
+ .\2 ( three )
);
\DIODE-BRIDGE U1 (
diff --git a/gnetlist/tests/common/outputs/vhdl/JD-output.net b/gnetlist/tests/common/outputs/vhdl/JD-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
index 534f455..d3589de 100644
--- a/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT LVD
END COMPONENT ;
- COMPONENT CAPACITOR
+ COMPONENT PMOS_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT LVD
+ COMPONENT vpulse
END COMPONENT ;
- COMPONENT PMOS_TRANSISTOR
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT model
+ COMPONENT CAPACITOR
END COMPONENT ;
- COMPONENT vpulse
+ COMPONENT model
END COMPONENT ;
SIGNAL Vdd1 : Std_Logic;
@@ -39,24 +39,49 @@ ARCHITECTURE netlist OF not found IS
SIGNAL m : Std_Logic;
BEGIN
-- Architecture statement part
- V1 : vpulse
- PORT MAP (
- 1 => i,
- 2 => GND);
+ A1 : model
+;
Cm : CAPACITOR
PORT MAP (
1 => m,
2 => GND);
- A1 : model
-;
+ Cp : CAPACITOR
+ PORT MAP (
+ 1 => p,
+ 2 => GND);
+
+ Rlp : RESISTOR
+ PORT MAP (
+ 2 => Vdd1,
+ 1 => p);
+
+ Rlm : RESISTOR
+ PORT MAP (
+ 2 => GND,
+ 1 => m);
+
+ Vdd : VOLTAGE_SOURCE
+ PORT MAP (
+ 1 => Vdd1,
+ 2 => GND);
+
+ V1 : vpulse
+ PORT MAP (
+ 1 => i,
+ 2 => GND);
Rt : RESISTOR
PORT MAP (
2 => m,
1 => p);
+ Rb : RESISTOR
+ PORT MAP (
+ 2 => LVH,
+ 1 => GND);
+
M1 : PMOS_TRANSISTOR
PORT MAP (
S => Vdd1,
@@ -74,30 +99,5 @@ BEGIN
6 => Vdd1,
7 => GND);
- Rlp : RESISTOR
- PORT MAP (
- 2 => Vdd1,
- 1 => p);
-
- Vdd : VOLTAGE_SOURCE
- PORT MAP (
- 1 => Vdd1,
- 2 => GND);
-
- Rlm : RESISTOR
- PORT MAP (
- 2 => GND,
- 1 => m);
-
- Cp : CAPACITOR
- PORT MAP (
- 1 => p,
- 2 => GND);
-
- Rb : RESISTOR
- PORT MAP (
- 2 => LVH,
- 1 => GND);
-
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
index 30a9a84..35595e0 100644
--- a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
@@ -10,10 +10,10 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT NPN_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
COMPONENT CAPACITOR
@@ -22,10 +22,10 @@ ARCHITECTURE netlist OF not found IS
COMPONENT vsin
END COMPONENT ;
- COMPONENT model
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT NPN_TRANSISTOR
+ COMPONENT model
END COMPONENT ;
COMPONENT include
@@ -48,116 +48,116 @@ ARCHITECTURE netlist OF not found IS
SIGNAL Vcoll1 : Std_Logic;
BEGIN
-- Architecture statement part
- Cout : CAPACITOR
- PORT MAP (
- 1 => VColl2,
- 2 => Vout);
-
- R5 : RESISTOR
+ C2 : CAPACITOR
PORT MAP (
- 2 => unnamed_net1,
- 1 => Vin);
+ 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : RESISTOR
PORT MAP (
2 => Vbase2,
1 => GND);
+ R3 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : CAPACITOR
+ PORT MAP (
+ 1 => GND,
+ 2 => Vem2);
+
RE2 : RESISTOR
PORT MAP (
2 => Vem2,
1 => GND);
+ RC1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : NPN_TRANSISTOR
PORT MAP (
3 => VColl2,
1 => Vem2,
2 => Vbase2);
+ C1 : CAPACITOR
+ PORT MAP (
+ 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : directive
;
- R3 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase2);
-
A2 : include
;
- RE1 : RESISTOR
- PORT MAP (
- 2 => Vem1,
- 1 => GND);
-
- Q1 : NPN_TRANSISTOR
- PORT MAP (
- 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : model
;
- R2 : RESISTOR
+ VCC : VOLTAGE_SOURCE
PORT MAP (
- 2 => Vbase1,
- 1 => GND);
+ 1 => Vcc,
+ 2 => GND);
Vinput : vsin
PORT MAP (
1 => Vin,
2 => GND);
- R1 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase1);
-
- C2 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : CAPACITOR
- PORT MAP (
- 1 => GND,
- 2 => Vem2);
-
- C1 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net1,
- 2 => Vbase1);
-
CE1 : CAPACITOR
PORT MAP (
1 => GND,
2 => Vem1);
- R8 : RESISTOR
+ Cout : CAPACITOR
PORT MAP (
- 2 => unnamed_net2,
- 1 => Vcoll1);
+ 1 => VColl2,
+ 2 => Vout);
- VCC : VOLTAGE_SOURCE
+ RL : RESISTOR
PORT MAP (
- 1 => Vcc,
- 2 => GND);
+ 2 => Vout,
+ 1 => GND);
RC2 : RESISTOR
PORT MAP (
2 => Vcc,
1 => VColl2);
- RC1 : RESISTOR
+ RE1 : RESISTOR
PORT MAP (
- 2 => Vcc,
- 1 => Vcoll1);
+ 2 => Vem1,
+ 1 => GND);
- RL : RESISTOR
+ R2 : RESISTOR
PORT MAP (
- 2 => Vout,
+ 2 => Vbase1,
1 => GND);
+ R1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : NPN_TRANSISTOR
+ PORT MAP (
+ 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
+
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
index 30a9a84..35595e0 100644
--- a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
@@ -10,10 +10,10 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT NPN_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
COMPONENT CAPACITOR
@@ -22,10 +22,10 @@ ARCHITECTURE netlist OF not found IS
COMPONENT vsin
END COMPONENT ;
- COMPONENT model
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT NPN_TRANSISTOR
+ COMPONENT model
END COMPONENT ;
COMPONENT include
@@ -48,116 +48,116 @@ ARCHITECTURE netlist OF not found IS
SIGNAL Vcoll1 : Std_Logic;
BEGIN
-- Architecture statement part
- Cout : CAPACITOR
- PORT MAP (
- 1 => VColl2,
- 2 => Vout);
-
- R5 : RESISTOR
+ C2 : CAPACITOR
PORT MAP (
- 2 => unnamed_net1,
- 1 => Vin);
+ 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : RESISTOR
PORT MAP (
2 => Vbase2,
1 => GND);
+ R3 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : CAPACITOR
+ PORT MAP (
+ 1 => GND,
+ 2 => Vem2);
+
RE2 : RESISTOR
PORT MAP (
2 => Vem2,
1 => GND);
+ RC1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : NPN_TRANSISTOR
PORT MAP (
3 => VColl2,
1 => Vem2,
2 => Vbase2);
+ C1 : CAPACITOR
+ PORT MAP (
+ 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : directive
;
- R3 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase2);
-
A2 : include
;
- RE1 : RESISTOR
- PORT MAP (
- 2 => Vem1,
- 1 => GND);
-
- Q1 : NPN_TRANSISTOR
- PORT MAP (
- 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : model
;
- R2 : RESISTOR
+ VCC : VOLTAGE_SOURCE
PORT MAP (
- 2 => Vbase1,
- 1 => GND);
+ 1 => Vcc,
+ 2 => GND);
Vinput : vsin
PORT MAP (
1 => Vin,
2 => GND);
- R1 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase1);
-
- C2 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : CAPACITOR
- PORT MAP (
- 1 => GND,
- 2 => Vem2);
-
- C1 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net1,
- 2 => Vbase1);
-
CE1 : CAPACITOR
PORT MAP (
1 => GND,
2 => Vem1);
- R8 : RESISTOR
+ Cout : CAPACITOR
PORT MAP (
- 2 => unnamed_net2,
- 1 => Vcoll1);
+ 1 => VColl2,
+ 2 => Vout);
- VCC : VOLTAGE_SOURCE
+ RL : RESISTOR
PORT MAP (
- 1 => Vcc,
- 2 => GND);
+ 2 => Vout,
+ 1 => GND);
RC2 : RESISTOR
PORT MAP (
2 => Vcc,
1 => VColl2);
- RC1 : RESISTOR
+ RE1 : RESISTOR
PORT MAP (
- 2 => Vcc,
- 1 => Vcoll1);
+ 2 => Vem1,
+ 1 => GND);
- RL : RESISTOR
+ R2 : RESISTOR
PORT MAP (
- 2 => Vout,
+ 2 => Vbase1,
1 => GND);
+ R1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : NPN_TRANSISTOR
+ PORT MAP (
+ 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
+
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
index 30a9a84..35595e0 100644
--- a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
@@ -10,10 +10,10 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT NPN_TRANSISTOR
END COMPONENT ;
- COMPONENT VOLTAGE_SOURCE
+ COMPONENT RESISTOR
END COMPONENT ;
COMPONENT CAPACITOR
@@ -22,10 +22,10 @@ ARCHITECTURE netlist OF not found IS
COMPONENT vsin
END COMPONENT ;
- COMPONENT model
+ COMPONENT VOLTAGE_SOURCE
END COMPONENT ;
- COMPONENT NPN_TRANSISTOR
+ COMPONENT model
END COMPONENT ;
COMPONENT include
@@ -48,116 +48,116 @@ ARCHITECTURE netlist OF not found IS
SIGNAL Vcoll1 : Std_Logic;
BEGIN
-- Architecture statement part
- Cout : CAPACITOR
- PORT MAP (
- 1 => VColl2,
- 2 => Vout);
-
- R5 : RESISTOR
+ C2 : CAPACITOR
PORT MAP (
- 2 => unnamed_net1,
- 1 => Vin);
+ 1 => unnamed_net2,
+ 2 => Vbase2);
R4 : RESISTOR
PORT MAP (
2 => Vbase2,
1 => GND);
+ R3 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase2);
+
+ R8 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net2,
+ 1 => Vcoll1);
+
+ CE2 : CAPACITOR
+ PORT MAP (
+ 1 => GND,
+ 2 => Vem2);
+
RE2 : RESISTOR
PORT MAP (
2 => Vem2,
1 => GND);
+ RC1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vcoll1);
+
Q2 : NPN_TRANSISTOR
PORT MAP (
3 => VColl2,
1 => Vem2,
2 => Vbase2);
+ C1 : CAPACITOR
+ PORT MAP (
+ 1 => unnamed_net1,
+ 2 => Vbase1);
+
A3 : directive
;
- R3 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase2);
-
A2 : include
;
- RE1 : RESISTOR
- PORT MAP (
- 2 => Vem1,
- 1 => GND);
-
- Q1 : NPN_TRANSISTOR
- PORT MAP (
- 3 => Vcoll1,
- 1 => Vem1,
- 2 => Vbase1);
-
A1 : model
;
- R2 : RESISTOR
+ VCC : VOLTAGE_SOURCE
PORT MAP (
- 2 => Vbase1,
- 1 => GND);
+ 1 => Vcc,
+ 2 => GND);
Vinput : vsin
PORT MAP (
1 => Vin,
2 => GND);
- R1 : RESISTOR
- PORT MAP (
- 2 => Vcc,
- 1 => Vbase1);
-
- C2 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net2,
- 2 => Vbase2);
-
- CE2 : CAPACITOR
- PORT MAP (
- 1 => GND,
- 2 => Vem2);
-
- C1 : CAPACITOR
- PORT MAP (
- 1 => unnamed_net1,
- 2 => Vbase1);
-
CE1 : CAPACITOR
PORT MAP (
1 => GND,
2 => Vem1);
- R8 : RESISTOR
+ Cout : CAPACITOR
PORT MAP (
- 2 => unnamed_net2,
- 1 => Vcoll1);
+ 1 => VColl2,
+ 2 => Vout);
- VCC : VOLTAGE_SOURCE
+ RL : RESISTOR
PORT MAP (
- 1 => Vcc,
- 2 => GND);
+ 2 => Vout,
+ 1 => GND);
RC2 : RESISTOR
PORT MAP (
2 => Vcc,
1 => VColl2);
- RC1 : RESISTOR
+ RE1 : RESISTOR
PORT MAP (
- 2 => Vcc,
- 1 => Vcoll1);
+ 2 => Vem1,
+ 1 => GND);
- RL : RESISTOR
+ R2 : RESISTOR
PORT MAP (
- 2 => Vout,
+ 2 => Vbase1,
1 => GND);
+ R1 : RESISTOR
+ PORT MAP (
+ 2 => Vcc,
+ 1 => Vbase1);
+
+ R5 : RESISTOR
+ PORT MAP (
+ 2 => unnamed_net1,
+ 1 => Vin);
+
+ Q1 : NPN_TRANSISTOR
+ PORT MAP (
+ 3 => Vcoll1,
+ 1 => Vem1,
+ 2 => Vbase1);
+
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/cascade-output.net b/gnetlist/tests/common/outputs/vhdl/cascade-output.net
index 3ff2e72..5c70356 100644
--- a/gnetlist/tests/common/outputs/vhdl/cascade-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/cascade-output.net
@@ -10,25 +10,25 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT cascade-filter
+ COMPONENT cascade-defaults-top
END COMPONENT ;
- COMPONENT cascade-transformer
+ COMPONENT cascade-source
END COMPONENT ;
- COMPONENT cascade-defaults
+ COMPONENT cascade-amp
END COMPONENT ;
- COMPONENT cascade-mixer
+ COMPONENT cascade-defaults
END COMPONENT ;
- COMPONENT cascade-defaults-top
+ COMPONENT cascade-filter
END COMPONENT ;
- COMPONENT cascade-source
+ COMPONENT cascade-mixer
END COMPONENT ;
- COMPONENT cascade-amp
+ COMPONENT cascade-transformer
END COMPONENT ;
SIGNAL unnamed_net6 : Std_Logic;
@@ -45,38 +45,38 @@ BEGIN
1 => unnamed_net6,
2 => OPEN);
- AMP1 : cascade-amp
- PORT MAP (
- 1 => unnamed_net1,
- 2 => unnamed_net2);
-
- SOURCE : cascade-source
- PORT MAP (
- 1 => unnamed_net1);
-
- DEFAULTS : cascade-defaults-top
+ T1 : cascade-transformer
PORT MAP (
- 1 => GND);
+ 1 => unnamed_net5,
+ 2 => unnamed_net6);
MX1 : cascade-mixer
PORT MAP (
1 => unnamed_net4,
2 => unnamed_net5);
+ FL1 : cascade-filter
+ PORT MAP (
+ 1 => unnamed_net3,
+ 2 => unnamed_net4);
+
DEF1 : cascade-defaults
PORT MAP (
1 => unnamed_net2,
2 => unnamed_net3);
- T1 : cascade-transformer
+ AMP1 : cascade-amp
PORT MAP (
- 1 => unnamed_net5,
- 2 => unnamed_net6);
+ 1 => unnamed_net1,
+ 2 => unnamed_net2);
- FL1 : cascade-filter
+ SOURCE : cascade-source
PORT MAP (
- 1 => unnamed_net3,
- 2 => unnamed_net4);
+ 1 => unnamed_net1);
+
+ DEFAULTS : cascade-defaults-top
+ PORT MAP (
+ 1 => GND);
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/multiequal-output.net b/gnetlist/tests/common/outputs/vhdl/multiequal-output.net
index 68da18d..cd7166f 100644
--- a/gnetlist/tests/common/outputs/vhdl/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/multiequal-output.net
@@ -10,10 +10,10 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT RESISTOR
+ COMPONENT options
END COMPONENT ;
- COMPONENT options
+ COMPONENT RESISTOR
END COMPONENT ;
COMPONENT VOLTAGE_SOURCE
@@ -28,13 +28,13 @@ BEGIN
1 => unnamed_net1,
2 => GND);
- A1 : options
-;
-
R1 : RESISTOR
PORT MAP (
2 => unnamed_net1,
1 => GND);
+ A1 : options
+;
+
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/netattrib-output.net b/gnetlist/tests/common/outputs/vhdl/netattrib-output.net
index a97e18e..f36d919 100644
--- a/gnetlist/tests/common/outputs/vhdl/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/netattrib-output.net
@@ -10,10 +10,10 @@ END not found;
-- Secondary unit
ARCHITECTURE netlist OF not found IS
- COMPONENT 7404
+ COMPONENT 7400
END COMPONENT ;
- COMPONENT 7400
+ COMPONENT 7404
END COMPONENT ;
COMPONENT FUSE
@@ -31,15 +31,6 @@ BEGIN
1 => one,
2 => OPEN);
- U100 : 7400
- PORT MAP (
- 3 => one,
- 2 => OPEN,
- 1 => OPEN,
- 14 => Vcc,
- 7 => GND,
- 5 => netattrib);
-
U300 : 7404
PORT MAP (
1 => one,
@@ -54,5 +45,14 @@ BEGIN
7 => GND,
14 => Vcc);
+ U100 : 7400
+ PORT MAP (
+ 3 => one,
+ 2 => OPEN,
+ 1 => OPEN,
+ 14 => Vcc,
+ 7 => GND,
+ 5 => netattrib);
+
-- Signal assignment part
END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/powersupply-output.net b/gnetlist/tests/common/outputs/vhdl/powersupply-output.net
index b815feb..c05b54f 100644
--- a/gnetlist/tests/common/outputs/vhdl/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/vhdl/powersupply-output.net
@@ -13,28 +13,28 @@ ARCHITECTURE netlist OF not found IS
COMPONENT DIODE-BRIDGE
END COMPONENT ;
- COMPONENT LM317
+ COMPONENT FUSE
END COMPONENT ;
COMPONENT transformer
END COMPONENT ;
- COMPONENT POLARIZED_CAPACITOR
+ COMPONENT MAINS_CONNECTOR
END COMPONENT ;
COMPONENT SPST
END COMPONENT ;
- COMPONENT VARIABLE_RESISTOR
+ COMPONENT POLARIZED_CAPACITOR
END COMPONENT ;
- COMPONENT MAINS_CONNECTOR
+ COMPONENT RESISTOR
END COMPONENT ;
- COMPONENT RESISTOR
+ COMPONENT VARIABLE_RESISTOR
END COMPONENT ;
- COMPONENT FUSE
+ COMPONENT LM317
END COMPONENT ;
SIGNAL ten : Std_Logic;
@@ -50,39 +50,39 @@ ARCHITECTURE netlist OF not found IS
SIGNAL eight : Std_Logic;
BEGIN
-- Architecture statement part
- F1 : FUSE
- PORT MAP (
- 1 => two,
- 2 => three);
-
- R2 : RESISTOR
+ U2 : LM317
PORT MAP (
2 => eleven,
+ 3 => eight,
1 => ten);
- CONN1 : MAINS_CONNECTOR
- PORT MAP (
- 1 => one,
- 2 => five,
- 3 => GND);
-
C4 : POLARIZED_CAPACITOR
PORT MAP (
1 => eleven,
2 => nine);
+ C3 : POLARIZED_CAPACITOR
+ PORT MAP (
+ 1 => ten,
+ 2 => nine);
+
R1 : VARIABLE_RESISTOR
PORT MAP (
3 => nine,
2 => ten,
1 => nine);
- C3 : POLARIZED_CAPACITOR
+ C2 : POLARIZED_CAPACITOR
PORT MAP (
- 1 => ten,
+ 1 => eight,
2 => nine);
- C2 : POLARIZED_CAPACITOR
+ R2 : RESISTOR
+ PORT MAP (
+ 2 => eleven,
+ 1 => ten);
+
+ C1 : POLARIZED_CAPACITOR
PORT MAP (
1 => eight,
2 => nine);
@@ -92,10 +92,11 @@ BEGIN
2 => two,
1 => one);
- C1 : POLARIZED_CAPACITOR
+ CONN1 : MAINS_CONNECTOR
PORT MAP (
- 1 => eight,
- 2 => nine);
+ 1 => one,
+ 2 => five,
+ 3 => GND);
T1 : transformer
PORT MAP (
@@ -104,11 +105,10 @@ BEGIN
4 => seven,
3 => six);
- U2 : LM317
+ F1 : FUSE
PORT MAP (
- 2 => eleven,
- 3 => eight,
- 1 => ten);
+ 1 => two,
+ 2 => three);
U1 : DIODE-BRIDGE
PORT MAP (
diff --git a/gnetlist/tests/common/outputs/vipec/JD-output.net b/gnetlist/tests/common/outputs/vipec/JD-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include-output.net b/gnetlist/tests/common/outputs/vipec/JD_Include-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net b/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
index c7cd2ab..48899a3 100644
--- a/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 3 0 % V1
- CAP 5 0 C=20p % Cm
error % A1
- RES 4 5 R=1k % Rt
- error 2 2 1 1 % M1
- error 3 0 2 5 4 1 0 % X1
+ CAP 5 0 C=20p % Cm
+ CAP 4 0 C=20p % Cp
RES 4 1 R=1meg % Rlp
- error 1 0 % Vdd
RES 5 0 R=500k % Rlm
- CAP 4 0 C=20p % Cp
+ error 1 0 % Vdd
+ error 3 0 % V1
+ RES 4 5 R=1k % Rt
RES 0 2 R=5.6k % Rb
+ error 2 2 1 1 % M1
+ error 3 0 2 5 4 1 0 % X1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
index a5eda3f..b030f3e 100644
--- a/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
@@ -2,29 +2,29 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- CAP 5 4 C=2.2uF % Cout
- RES 7 8 R=10 % R5
+ CAP 1 2 C=2.2uF % C2
RES 0 2 R=2.8K % R4
+ RES 2 6 R=28K % R3
+ RES 11 1 R=1 % R8
+ CAP 0 3 C=1pF % CE2
RES 0 3 R=100 % RE2
+ RES 11 6 R=3.3K % RC1
error 5 2 3 % Q2
+ CAP 8 9 C=2.2uF % C1
error % A3
- RES 2 6 R=28K % R3
error % A2
- RES 0 10 R=100 % RE1
- error 11 9 10 % Q1
error % A1
- RES 0 9 R=2K % R2
+ error 6 0 % VCC
error 7 0 % Vinput
- RES 9 6 R=28K % R1
- CAP 1 2 C=2.2uF % C2
- CAP 0 3 C=1pF % CE2
- CAP 8 9 C=2.2uF % C1
CAP 0 10 C=1pF % CE1
- RES 11 1 R=1 % R8
- error 6 0 % VCC
- RES 5 6 R=1K % RC2
- RES 11 6 R=3.3K % RC1
+ CAP 5 4 C=2.2uF % Cout
RES 0 4 R=100K % RL
+ RES 5 6 R=1K % RC2
+ RES 0 10 R=100 % RE1
+ RES 0 9 R=2K % R2
+ RES 9 6 R=28K % R1
+ RES 7 8 R=10 % R5
+ error 11 9 10 % Q1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
index a5eda3f..b030f3e 100644
--- a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
@@ -2,29 +2,29 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- CAP 5 4 C=2.2uF % Cout
- RES 7 8 R=10 % R5
+ CAP 1 2 C=2.2uF % C2
RES 0 2 R=2.8K % R4
+ RES 2 6 R=28K % R3
+ RES 11 1 R=1 % R8
+ CAP 0 3 C=1pF % CE2
RES 0 3 R=100 % RE2
+ RES 11 6 R=3.3K % RC1
error 5 2 3 % Q2
+ CAP 8 9 C=2.2uF % C1
error % A3
- RES 2 6 R=28K % R3
error % A2
- RES 0 10 R=100 % RE1
- error 11 9 10 % Q1
error % A1
- RES 0 9 R=2K % R2
+ error 6 0 % VCC
error 7 0 % Vinput
- RES 9 6 R=28K % R1
- CAP 1 2 C=2.2uF % C2
- CAP 0 3 C=1pF % CE2
- CAP 8 9 C=2.2uF % C1
CAP 0 10 C=1pF % CE1
- RES 11 1 R=1 % R8
- error 6 0 % VCC
- RES 5 6 R=1K % RC2
- RES 11 6 R=3.3K % RC1
+ CAP 5 4 C=2.2uF % Cout
RES 0 4 R=100K % RL
+ RES 5 6 R=1K % RC2
+ RES 0 10 R=100 % RE1
+ RES 0 9 R=2K % R2
+ RES 9 6 R=28K % R1
+ RES 7 8 R=10 % R5
+ error 11 9 10 % Q1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
index a5eda3f..b030f3e 100644
--- a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
@@ -2,29 +2,29 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- CAP 5 4 C=2.2uF % Cout
- RES 7 8 R=10 % R5
+ CAP 1 2 C=2.2uF % C2
RES 0 2 R=2.8K % R4
+ RES 2 6 R=28K % R3
+ RES 11 1 R=1 % R8
+ CAP 0 3 C=1pF % CE2
RES 0 3 R=100 % RE2
+ RES 11 6 R=3.3K % RC1
error 5 2 3 % Q2
+ CAP 8 9 C=2.2uF % C1
error % A3
- RES 2 6 R=28K % R3
error % A2
- RES 0 10 R=100 % RE1
- error 11 9 10 % Q1
error % A1
- RES 0 9 R=2K % R2
+ error 6 0 % VCC
error 7 0 % Vinput
- RES 9 6 R=28K % R1
- CAP 1 2 C=2.2uF % C2
- CAP 0 3 C=1pF % CE2
- CAP 8 9 C=2.2uF % C1
CAP 0 10 C=1pF % CE1
- RES 11 1 R=1 % R8
- error 6 0 % VCC
- RES 5 6 R=1K % RC2
- RES 11 6 R=3.3K % RC1
+ CAP 5 4 C=2.2uF % Cout
RES 0 4 R=100K % RL
+ RES 5 6 R=1K % RC2
+ RES 0 10 R=100 % RE1
+ RES 0 9 R=2K % R2
+ RES 9 6 R=28K % R1
+ RES 7 8 R=10 % R5
+ error 11 9 10 % Q1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/cascade-output.net b/gnetlist/tests/common/outputs/vipec/cascade-output.net
index 75b0b79..d369aac 100644
--- a/gnetlist/tests/common/outputs/vipec/cascade-output.net
+++ b/gnetlist/tests/common/outputs/vipec/cascade-output.net
@@ -3,13 +3,13 @@
% Based on code by Bas Gieltjes
CKT
error 1 #<unspecified> % AMP2
+ error 2 1 % T1
+ error 3 2 % MX1
+ error 4 3 % FL1
+ error 5 4 % DEF1
error 6 5 % AMP1
error 6 % SOURCE
error #<unspecified> % DEFAULTS
- error 3 2 % MX1
- error 5 4 % DEF1
- error 2 1 % T1
- error 4 3 % FL1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/multiequal-output.net b/gnetlist/tests/common/outputs/vipec/multiequal-output.net
index a800cc8..818ce82 100644
--- a/gnetlist/tests/common/outputs/vipec/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/vipec/multiequal-output.net
@@ -3,8 +3,8 @@
% Based on code by Bas Gieltjes
CKT
error 1 0 % V1
- error % A1
RES 0 1 R=20 % R1
+ error % A1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/netattrib-output.net b/gnetlist/tests/common/outputs/vipec/netattrib-output.net
index 9685438..6f9f3c3 100644
--- a/gnetlist/tests/common/outputs/vipec/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/vipec/netattrib-output.net
@@ -3,9 +3,9 @@
% Based on code by Bas Gieltjes
CKT
error 4 #<unspecified> % F1
- error #<unspecified> #<unspecified> 4 #<unspecified> #<unspecified> #<unspecified> % U100
error 4 1 #<unspecified> #<unspecified> % U300
error 4 2 #<unspecified> #<unspecified> % U200
+ error #<unspecified> #<unspecified> 4 #<unspecified> #<unspecified> #<unspecified> % U100
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/common/outputs/vipec/powersupply-output.net b/gnetlist/tests/common/outputs/vipec/powersupply-output.net
index 6e9bd91..7e018f9 100644
--- a/gnetlist/tests/common/outputs/vipec/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/vipec/powersupply-output.net
@@ -2,17 +2,17 @@
% Written by Matthew Ettus
% Based on code by Bas Gieltjes
CKT
- error 6 5 % F1
- RES 1 2 R=220 % R2
- error 3 4 0 % CONN1
+ error 1 2 10 % U2
error 2 9 % C4
- error 9 1 9 % R1
error 1 9 % C3
+ error 9 1 9 % R1
error 10 9 % C2
- error 3 6 % S1
+ RES 1 2 R=220 % R2
error 10 9 % C1
+ error 3 6 % S1
+ error 3 4 0 % CONN1
error 5 4 7 8 % T1
- error 1 2 10 % U2
+ error 6 5 % F1
error 10 9 8 7 % U1
DEF2P #<unspecified> #<unspecified>
TERM 50 50
diff --git a/gnetlist/tests/hierarchy/hierarchy.geda b/gnetlist/tests/hierarchy/hierarchy.geda
index 4bf29fe..7fae39f 100644
--- a/gnetlist/tests/hierarchy/hierarchy.geda
+++ b/gnetlist/tests/hierarchy/hierarchy.geda
@@ -8,9 +8,9 @@ END header
START components
Uunder/Umiddle/Urock/Qrock device=PNP_TRANSISTOR
-Utop/Umiddle/Urock/Qrock device=PNP_TRANSISTOR
U2 device=7404
U1 device=7404
+Utop/Umiddle/Urock/Qrock device=PNP_TRANSISTOR
END components
diff --git a/gnetlist/tests/multiequal.spice-sdb b/gnetlist/tests/multiequal.spice-sdb
index d9ccdb8..93b391f 100644
--- a/gnetlist/tests/multiequal.spice-sdb
+++ b/gnetlist/tests/multiequal.spice-sdb
@@ -1,4 +1,4 @@
-* gnetlist -o new_multiequal.spice-sdb -g spice-sdb ./multiequal.sch
+* ../src/gnetlist -o ../tests/new_multiequal.spice-sdb -g spice-sdb ./multiequal.sch
*********************************************************
* Spice file generated by gnetlist *
* spice-sdb version 4.28.2007 by SDB -- *
@@ -7,6 +7,6 @@
*********************************************************
*============== Begin SPICE netlist of main design ============
V1 1 0 DC 1V
-.OPTIONS abotol=1e-11
R1 0 1 20
+.OPTIONS abotol=1e-11
.end
diff --git a/gnetlist/tests/netattrib.geda b/gnetlist/tests/netattrib.geda
index 684efb0..5910ebd 100644
--- a/gnetlist/tests/netattrib.geda
+++ b/gnetlist/tests/netattrib.geda
@@ -8,9 +8,9 @@ END header
START components
F1 device=FUSE
-U100 device=7400
U300 device=7404
U200 device=7404
+U100 device=7400
END components
diff --git a/gnetlist/tests/powersupply.allegro b/gnetlist/tests/powersupply.allegro
index a338584..c7a407b 100644
--- a/gnetlist/tests/powersupply.allegro
+++ b/gnetlist/tests/powersupply.allegro
@@ -1,16 +1,16 @@
(Allegro netlister by M. Ettus)
$PACKAGES
-! FUSE! FUSE; F1
-! RESISTOR! 220; R2
-! MAINS_CONNECTOR! MAINS_CONNECTOR; CONN1
+! LM317! LM317; U2
! POLARIZED_CAPACITOR! 1uf; C4
-! VARIABLE_RESISTOR! 5k; R1
! POLARIZED_CAPACITOR! 22uF; C3
+! VARIABLE_RESISTOR! 5k; R1
! POLARIZED_CAPACITOR! 0.1uF; C2
-! SPST! SPST; S1
+! RESISTOR! 220; R2
! POLARIZED_CAPACITOR! 2200uF; C1
+! SPST! SPST; S1
+! MAINS_CONNECTOR! MAINS_CONNECTOR; CONN1
! transformer! transformer; T1
-! LM317! LM317; U2
+! FUSE! FUSE; F1
! DIODE-BRIDGE! DIODE-BRIDGE; U1
$NETS
ten; U2.1,
diff --git a/gnetlist/tests/powersupply.bae b/gnetlist/tests/powersupply.bae
index 86ab354..0f6eea0 100644
--- a/gnetlist/tests/powersupply.bae
+++ b/gnetlist/tests/powersupply.bae
@@ -1,16 +1,16 @@
LAYOUT board;
PARTS
- F1 : unknown;
- R2 : unknown;
- CONN1 : unknown;
+ U2 : unknown;
C4 : unknown;
- R1 : unknown;
C3 : unknown;
+ R1 : unknown;
C2 : unknown;
- S1 : unknown;
+ R2 : unknown;
C1 : unknown;
+ S1 : unknown;
+ CONN1 : unknown;
T1 : unknown;
- U2 : unknown;
+ F1 : unknown;
U1 : unknown;
CONNECT
/'ten'/ U2.1=R1.2=C3.1=R2.1;
diff --git a/gnetlist/tests/powersupply.geda b/gnetlist/tests/powersupply.geda
index 3471ddb..b4bc97c 100644
--- a/gnetlist/tests/powersupply.geda
+++ b/gnetlist/tests/powersupply.geda
@@ -7,17 +7,17 @@ END header
START components
-F1 device=FUSE
-R2 device=RESISTOR
-CONN1 device=MAINS_CONNECTOR
+U2 device=LM317
C4 device=POLARIZED_CAPACITOR
-R1 device=VARIABLE_RESISTOR
C3 device=POLARIZED_CAPACITOR
+R1 device=VARIABLE_RESISTOR
C2 device=POLARIZED_CAPACITOR
-S1 device=SPST
+R2 device=RESISTOR
C1 device=POLARIZED_CAPACITOR
+S1 device=SPST
+CONN1 device=MAINS_CONNECTOR
T1 device=transformer
-U2 device=LM317
+F1 device=FUSE
U1 device=DIODE-BRIDGE
END components
diff --git a/gnetlist/tests/powersupply.maxascii b/gnetlist/tests/powersupply.maxascii
index dd9b9bd..2892cf5 100644
--- a/gnetlist/tests/powersupply.maxascii
+++ b/gnetlist/tests/powersupply.maxascii
@@ -1,16 +1,16 @@
*OrCAD
*START
-*COMP F1 "unknown"
-*COMP R2 "unknown"
-*COMP CONN1 "unknown"
+*COMP U2 "unknown"
*COMP C4 "unknown"
-*COMP R1 "unknown"
*COMP C3 "unknown"
+*COMP R1 "unknown"
*COMP C2 "unknown"
-*COMP S1 "unknown"
+*COMP R2 "unknown"
*COMP C1 "unknown"
+*COMP S1 "unknown"
+*COMP CONN1 "unknown"
*COMP T1 "unknown"
-*COMP U2 "unknown"
+*COMP F1 "unknown"
*COMP U1 "unknown"
*NET "ten"
*NET "ten" U2."1" R1."2" C3."1" R2."1"
diff --git a/gnetlist/tests/powersupply.pads b/gnetlist/tests/powersupply.pads
index 3aa5cd9..0688481 100644
--- a/gnetlist/tests/powersupply.pads
+++ b/gnetlist/tests/powersupply.pads
@@ -1,17 +1,17 @@
!PADS-POWERPCB-V3.0-MILS!
*PART*
-F1 unknown
-R2 unknown
-CONN1 unknown
+U2 unknown
C4 unknown
-R1 unknown
C3 unknown
+R1 unknown
C2 unknown
-S1 unknown
+R2 unknown
C1 unknown
+S1 unknown
+CONN1 unknown
T1 unknown
-U2 unknown
+F1 unknown
U1 unknown
*NET*
diff --git a/gnetlist/tests/powersupply.protelII b/gnetlist/tests/powersupply.protelII
index 0dd831a..a376138 100644
--- a/gnetlist/tests/powersupply.protelII
+++ b/gnetlist/tests/powersupply.protelII
@@ -1,13 +1,13 @@
PROTEL NETLIST 2.0
[
DESIGNATOR
-F1
+U2
FOOTPRINT
unknown
PARTTYPE
-FUSE
+LM317
DESCRIPTION
-FUSE
+LM317
Part Field 1
*
Part Field 2
@@ -59,13 +59,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R2
+C4
FOOTPRINT
unknown
PARTTYPE
-220
+1uf
DESCRIPTION
-RESISTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -117,13 +117,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-CONN1
+C3
FOOTPRINT
unknown
PARTTYPE
-MAINS_CONNECTOR
+22uF
DESCRIPTION
-MAINS_CONNECTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -175,13 +175,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C4
+R1
FOOTPRINT
unknown
PARTTYPE
-1uf
+5k
DESCRIPTION
-POLARIZED_CAPACITOR
+VARIABLE_RESISTOR
Part Field 1
*
Part Field 2
@@ -233,13 +233,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-R1
+C2
FOOTPRINT
unknown
PARTTYPE
-5k
+0.1uF
DESCRIPTION
-VARIABLE_RESISTOR
+POLARIZED_CAPACITOR
Part Field 1
*
Part Field 2
@@ -291,13 +291,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C3
+R2
FOOTPRINT
unknown
PARTTYPE
-22uF
+220
DESCRIPTION
-POLARIZED_CAPACITOR
+RESISTOR
Part Field 1
*
Part Field 2
@@ -349,11 +349,11 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C2
+C1
FOOTPRINT
unknown
PARTTYPE
-0.1uF
+2200uF
DESCRIPTION
POLARIZED_CAPACITOR
Part Field 1
@@ -465,13 +465,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-C1
+CONN1
FOOTPRINT
unknown
PARTTYPE
-2200uF
+MAINS_CONNECTOR
DESCRIPTION
-POLARIZED_CAPACITOR
+MAINS_CONNECTOR
Part Field 1
*
Part Field 2
@@ -581,13 +581,13 @@ LIBRARYFIELD8
]
[
DESIGNATOR
-U2
+F1
FOOTPRINT
unknown
PARTTYPE
-LM317
+FUSE
DESCRIPTION
-LM317
+FUSE
Part Field 1
*
Part Field 2
diff --git a/gnetlist/tests/powersupply.tango b/gnetlist/tests/powersupply.tango
index 96576c4..56453f0 100644
--- a/gnetlist/tests/powersupply.tango
+++ b/gnetlist/tests/powersupply.tango
@@ -1,29 +1,22 @@
[
-F1
+U2
PATTERN
-FUSE
-
+LM317
-]
-[
-R2
-PATTERN
-RESISTOR
-220
]
[
-CONN1
+C4
PATTERN
-MAINS_CONNECTOR
-
+POLARIZED_CAPACITOR
+1uf
]
[
-C4
+C3
PATTERN
POLARIZED_CAPACITOR
-1uf
+22uF
]
[
@@ -34,17 +27,24 @@ VARIABLE_RESISTOR
]
[
-C3
+C2
PATTERN
POLARIZED_CAPACITOR
-22uF
+0.1uF
]
[
-C2
+R2
+PATTERN
+RESISTOR
+220
+
+]
+[
+C1
PATTERN
POLARIZED_CAPACITOR
-0.1uF
+2200uF
]
[
@@ -55,10 +55,10 @@ SPST
]
[
-C1
+CONN1
PATTERN
-POLARIZED_CAPACITOR
-2200uF
+MAINS_CONNECTOR
+
]
[
@@ -69,9 +69,9 @@ transformer
]
[
-U2
+F1
PATTERN
-LM317
+FUSE
]
diff --git a/gnetlist/tests/stack_1.geda b/gnetlist/tests/stack_1.geda
index 0d2d410..6bf97c5 100644
--- a/gnetlist/tests/stack_1.geda
+++ b/gnetlist/tests/stack_1.geda
@@ -7,10 +7,10 @@ END header
START components
-U211 device=74191
U210 device=74541
-U109 device=AM9128
+U211 device=74191
U212 device=74191
+U109 device=AM9128
END components
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